Performance Architect - Modeling and Analysis

About SiFive

SiFive is an idea-to-silicon company founded by the inventors of RISC-V to simplify the design and production of custom SoCs.

As the leading commercial provider of RISC-V processor IP, SiFive is on a mission to help engineers design custom chips for domain-specific solutions for many markets, including 5G, edge AI, enterprise networking, storage, and consumer devices.

Industry-leading innovators, including six of the top ten semiconductor companies, are working with SiFive thanks to our proven success, deep expertise, and rich partner ecosystem. With SiFive’s rich IP ecosystem and accessible design platform, every market has access to the development of workload-focused hardware needed to design next-generation products.

Location: The ideal candidate for this position can work out of one of our US offices or remotely from home, collaborating with the HQ in San Mateo, CA. However, all positions are currently remote until further notice.

Responsibilities:

Person will be responsible for the modeling and analysis of High Performance Next-Generation super-scalar out-of-order RISC-V microprocessors. Candidate should have good knowledge of both Software programming and Hardware microarchitecture.

Requirements:

Require 5+ years of direct industry experience in cycle-level modeling of modern core micro-architectures, preferably using a discrete event simulation (DES) framework

Skills:

• Strong foundation in computer architecture of high performance out-of-order CPU designs. Awareness of known industry micro-architectures is a plus.

• Ability to independently analyze performance bottlenecks in micro-architecture and software stack. Awareness of potential security holes is a plus.

• Fluency in C++ 17, particularly with regard to standard idioms, templates, template specializations for code optimization, STL containers and basic STL algorithms

• Conversant in Python, sufficient to be comfortable writing object oriented Python scripts on the order of a few hundred lines of code

• Strong object-oriented programming (OOP) skills, including encapsulation, class coherency, inheritance and polymorphism

• Strong Discrete Event Simulation (DES) competency, particularly with regard to DES modeling techniques and best practices

• Strong software optimization and design skills for code efficiency, algorithms and data structures

• Familiarity with the Gamma et al Design Patterns and basic UML syntax (e.g. Observer, Composite, Adaptor, Proxy, Facade, etc.)

• Competency in software engineering best practices needed to maintain and refactor very large object oriented code bases

• Ability to research known techniques in branch prediction and data prefetching, and synthesize new, implementable approaches using those findings, keeping in mind both the performance uplift and also the implementation considerations for improvements

• Ability to work independently, but also provide clear progress readouts throughout

• Ability to use and adapt existing models and modeling infrastructure; ability to create new models if needed

• Vector

  • Good working knowledge of SIMD ISAs

  • Preferred familiarity with RISC-V Vector, latest spec 1.0

  • Ability to program using assembler to write custom tests for vector analysis

  • Strong knowledge of distributed SIMD hardware designs

Others:

• Familiar with git and branching/forking methodologies

• Strong background with Linux-based development environments including python/shell programming