Chip design, reimagined.

Introducing a fast, affordable and efficient new way to design silicon chips based on SiFive's cloud accelerated "Idea-to-Silicon" methodology.

Coming Soon
Chip Designer

Start with your idea, get it in silicon.

Chips are in everything you own. Yet until now, only the biggest players with the deepest pockets could create custom SoCs.

SiFive is changing all of that. Every entrepreneur, inventor and innovator can translate their dreams into silicon.

The Beginning

Let’s get real.

Introducing our first silicon proof points — built with the same technology that's behind the SiFive Chip Designer.
Freedom Everywhere


The FE310 is the first RISC-V Low-Power MCU SOC designed using SiFive's cloud accelerated 'Idea-to-Silicon' methodology and powered by SiFive's E31 standard core.


320+ MHz

Among the fastest on the market


1.61 DMIPs/MHz

E31 Standard Core

  • RV32I Base Integer Instruction Set, Version 2.0
  • “M” Standard Extension for Integer Multiplication and Division, Version 2.0
  • “A” Standard Extension for Atomic Instructions, Version 2.0
  • “C” Standard Extension for Compressed Instructions, Version 1.9
  • RISC‑V Privileged ISA Specification, Version 1.9.1
  • RISC‑V External Debug Support, Version 0.13

Additional Features

  • 16KB L1 Instruction Cache
  • 16KB Data SRAM Scratchpad
  • Hardware multiply/divide
  • Debug module
  • OTP non-volatile memory
  • Flexible clock generation with on-chip oscillators and PLLs
  • Peripherals including UARTs, QSPI, PWMs, and timers
  • Multiple power domains + low-power standby mode
Freedom Unleashed


The FU540 is the first 4+1 multi-core RISC-V Linux capable Application Processor SOC designed using SiFive's cloud accelerated 'Idea-to-Silicon' methodology and powered by SiFive's U54-MC standard core.


1.5 GHz+

4+1 Multi-Core Coherent Configuration



DDR4 with ECC

U54-MC Standard Core

  • 4× U54 RISC‑V Cores
  • 32 KiB 8-way L1 I-cache
  • 32 KiB 8-way L1 D-cache
  • 1× S5 RISC‑V Core
  • 16 KiB 2-way L1 I-cache
  • 8 KiB Data (DTIM).

Additional Features

  • 1x S5 RV64IMAC Management Core
  • Coherent 2 MB L2 Cache
  • 64-bit DDR4 with ECC
  • 1x Gigabit Ethernet
  • Built on a 28nm process
  • Linux-capable RISC‑V Template
  • 4x U54 RV64GC Application Cores
  • Sv39 Virtual Memory Support

What People
are Saying

The real benefit of RISC‑V is that it could enable companies to build chips that better meet their needs.

Klint Finley — Wired Business

Sutter Hill Ventures

SiFive is providing innovative solutions that will fundamentally change the semiconductor industry.

Stefan Dyckerhoff — Sutter Hill Ventures, Managing Director

RISC‑V offers a fresh approach that has the potential to help reduce SoC development time and cost significantly.

Raja Koduri — GM Edge Computing Solutions, Chief Architect, Intel

Custom silicon is going to be a big theme going forward as each use case may carry different needs. ...One-size-fits-all [chips] might not hit each sweet spot. That is the hole that a company like SiFive could fill.

Matthew Lynley — TechCrunch