Vastly customizable core IP.

Get best-in-class core IP developed by the inventors of RISC‑V and customize it to your exact specifications.

Design Core

Here’s how it works.

  • 01. Design

    Customize a SiFive Standard Core to meet the precise needs of your product.

  • 02. Evaluate

    Simulate with fully-functional, synthesizable Verilog RTL. Run your application code on an FPGA.

  • 03. License

    Licensing is straightforward and your custom RISC‑V core IP is available within weeks.

RISC‑V Cores

Start designing.

I want core that runs

E2 Series

Our smallest, lowest power, 32‑bit RISC‑V embedded cores

Compares with Arm

M0, M0+, M3, M4, M23, M33

Area

E3 Series

High performance 32‑bit RISC‑V embedded cores

Compares with Arm

R4, R5

Area

E7 Series

Our highest-performance 32-bit RISC-V embedded cores

Compares with Arm

M7, R7, R8

Area
E76 Core
E76-MC Core

S5 Series

64‑bit RISC-V embedded performance at 32‑bit price and area

Compares with Arm

R4, R5

Area

S7 Series

Our highest-performance 64-bit RISC-V embedded cores

Compares with Arm

M7, R7, R8

Area
S76 Core
S76-MC Core

U5 Series

RISC‑V Linux-capable application processors with high performance & maximum efficiency

Compares with Arm

A5, A7, A35, A53

Area
U54 Core
U54-MC Core

U7 Series

Our highest-performance RISC-V Linux-capable application processors

Compares with Arm

A55

Area
U74 Core
U74-MC Core
Core Series

Choose your foundation

Core Series provide powerful capabilities for your product ideas. Choose one of our silicon-proven RISC-V Standard Cores—or customize a core to get the precise results that you need.

Series
Overview

Area
Standard Cores
ARM Comparison
E2 Series
M0, M0+, M3, M4, M23, M33
E3 Series
R4, R5
E7 Series
M7, R7, R8
S5 Series
R4, R5
S7 Series
M7, R7, R8
U5 Series
A5, A7, A35, A53
U7 Series
A55

What People
are Saying

SiFive’s RISC‑V Core IP was 1/3 the power and 1/3 the area of competing solutions, and gave FADU the flexibility we needed in optimizing our architecture to achieve these groundbreaking products.

Jihyo Lee — CEO, FADU

SiFive’s founders invented the RISC‑V instruction set architecture, which puts them in the driver’s seat for customers who want the benefits that open source hardware development offers.

Drew Wingard — Sonics CTO

SiFive’s cloud-based approach provides flexibility and ease for design teams, and we look forward to exploring its benefits.

Raja Koduri — GM Edge Computing Solutions, Chief Architect, Intel

RISC‑V looks as if it’s on it’s way to becoming a disruptive force for devices operating at the edge.

Christine Hall — DataCenterKnowledge.com

Like ARM processors, [SiFive’s] U540 sips power, and they already seem capable of doing the type of heavy lifting required of servers.

Christine Hall — DataCenterKnowledge.com

Western Digital

RISC‑V will allow the entire industry to realize the benefits of next-generation architectures while also enabling us to create more purpose-built devices, platforms and storage systems for Big Data and Fast Data applications.

Mike Cordano — President & COO, Western Digital