While advanced digital and analog sensing based applications support the industry standard Predictive Maintenance 4.0 protocols (PdM 4.0), they must also be optimized for power-efficient performance in industrial, automotive, artificial intelligence and machine learning applications.
- 28nm, 40/45nm Process
SiFive’s “Idea-to-Silicon” Methodology
SiFive Templates enable solutions for when you need a market focused design based on proven IP but offering configuration options and the ability to incorporate your own IP. The SiFive template process will lower costs and deliver an SoC design for your specific needs.
Benefits of using "Idea-to-Silicon" Methodology
Ongoing product development costs on derivatives of existing chip designs are high and make it hard to integrate new IP. SiFive’s “Idea-to-Silicon” methodology can reduce cost and cycle time, while putting the hardware you need under your preferred software stack.
Combine SiFive’s standard cores with SoC IP from SiFive and Design Share partners with your own key technology to get your ideal end product.
SiFive templates are ideal starting points for entry into key markets where the SiFive IP portfolio offers a competitive advantage. Complete the configuration of the template to your specifications to create your own fine-tuned design for your market application.
SiFive’s “Idea-to-Silicon” methodology provides the opportunity to optimize layout for the power, performance and size requirement of your target market, and enables rapid iteration for ongoing product roadmap development for optimal time-to-market.