Lead Memory Subsystem Verification Engineer
SiFive is an idea-to-silicon company founded by the inventors of RISC-V to simplify the design and production of custom SoCs.
As the leading commercial provider of RISC-V processor IP, SiFive is on a mission to help engineers design custom chips for domain-specific solutions for many markets, including 5G, edge AI, enterprise networking, storage, and consumer devices.
Industry-leading innovators, including six of the top ten semiconductor companies, are working with SiFive thanks to our proven success, deep expertise, and rich partner ecosystem. With SiFive’s rich IP ecosystem and accessible design platform, every market has access to the development of workload-focused hardware needed to design next-generation products.
- Architect test methodologies applicable to a wide range of CPU and SoC designs for CPU memory sub-systems including Load-Store unit, various levels of caches, memory virtualization and industry standard bus protocols (e.g. AMBA and TileLink).
- Understand CPU caches and SoC designs from an architectural level and create effective verification strategies for these designs.
- Build test plans to implement these strategies, considering issues such as design feature priority, potential customer impact, coverage metrics generation and measurability, etc.
- Develop tools, test benches, and test suites (UVM, C++/C or otherwise, as needed) to execute test plans.
- Provide technical leadership for verification engineers and coordinate technical teams to execute our verification strategies to meet program goals.
- Collaborate closely with the design team on feature specifications, test plans and failure analysis.
- 7+ years of recent experience with standard verification tools and methodologies (UVM, Verdi/DVE, System Verilog, Verilog, Makefiles, scripting languages, etc.), especially in hands-on testbench development and test suite generation.
- Solid understanding of CPU and SoC memory architecture including Load-Store unit, various levels of caches, cache coherence protocols, virtual memory, bus interface units, and memory controllers.
- Experience with industry standard system bus protocols (e.g. AMBA AXI, AHB, APB) is preferred. Knowledge of TileLink is a plus.
- A thorough understanding of the high-level verification flow methodology (testplan generation, test generation, failure analysis, coverage analysis and closure).
- Ability to effectively assess the design verification metrics, remaining state space to be covered, and efficient methods to achieve verification closure.
- Verification experience in test planning, constrained random test generation, test stimulus, code coverage, functional coverage.
- Ability to learn languages and methodologies that are not part of the industry standard approach to verification (Scala, Chisel, etc).