At SiFive, you’ll be part of a fun, engaging team and be afforded the opportunity to grow within the company. You will bring fruition the new RISC-V architecture and enable its rapid adoption by implementing new tools, breakthrough design methods and services. We need people who are trail-blazers, aren’t afraid to take a chance, and don’t always “go with the flow”.

Responsibilities:

Configuration/Customize of RISC-V CPU according to different application requirement
Optimize the micro architecture of current RISC-V CPU core
Optimize or re-design the memory sub-system for CPU core
Define the micro architecture spec and C model for hardware engine of co-processor to RISC-V
Direction RTL coding of CPU building block and extension instruction hardware
Co-work with compiler team/partner to support extension feature of CPU

Qualifications:

BS degree or equivalent practical experience. MS in EE or CS is preferred.
8+years’ experience in CPU core development with RISC ISA
Knowledge of compiler principle and open source compiler
Strong experience of verification of CPU core according to ISA
Experience of DSP instruction and pipe-line design
Experience of cache implementation for instruction and data
Experience of CPU related verification methodology
Good people and communication skills in Mandarin and English

Big Plus:

Experience of chisel usage of RISC-V
Experience of IoT ASIC/SoC architecture design.
Experience of AI related hardware accelerator engineer, especially for CNN, DNN and SIMD/SIMT

Apply for This Job