San Mateo, CA

Physical Design / GateSim Validation Engineer

RISC-V is a groundbreaking CPU instruction set and architecture. Along with being an open-source instruction set, RISC-V is informed by decades of industry experience with various RISC processor designs, while being unencumbered with the necessity of backward compatibility. It is a unique opportunity to base a processor design on sound engineering principles, and the successful applicant will have comprehensive daily hands-on exposure to this architecture. While several companies are pursuing RISC-V design, only SiFive is founded and actively managed by the inventors of RISC-V. This is not an academic exercise; we have real customers and real silicon. 
You will develop methodology to run gatesim (GLS) on automated generated design in order to estimate accurate average/max power consumption, timing, modeling issues.

The Challenge

  • Developing efficient gatesim methodology to support auto-generated customized designs;
  • Applying to zero delay gatesims;
  • Providing high confidence tapeout for SoC products;
  • Developing process to interact with design, verification, and implement teams with gatesim.

What you bring to the challenge

  • Good waveform debugging skills:
  • Understanding timing issues;
  • Debugging through various IPs in gate level netlist;
  • Knowledge of X-prop issue;
  • Knowledge of Standard Delay Format (SDF);
  • Verilog modeling:
  • Good understanding of blocking / non-blocking assignments;
  • Good understanding of UDPs;
  • Knowledge of Simulation glitches / races;
  • Knowledge of Event queue.
SiFive is proud to be an equal employment opportunity workplace. We offer a competitive compensation package that includes flexible paid time off, health, vision and dental benefits, 401(k) plan, employee stock option program, and much more. If you yearn to be challenged and wish to work in an environment where the boundaries of your creativity and skills will be tested, then SiFive is place for you.