Shanghai/Chengdu
Engineering
Full-Time

Design Engineer

At SiFive, you’ll be part of a fun, engaging team and be afforded the opportunity to grow within the company. You will bring fruition the new RISC-V architecture and enable its rapid adoption by implementing new tools, breakthrough design methods and services. We need people who are trail-blazers, aren’t afraid to take a chance, and don’t always “go with the flow”.

Responsibilities:

  • Function/IP module coding and data path simulation
  • Chip level design and coding with good coding style
  • Co-work with software team to identify architecture requirements
  • Co-simulation with driver software program
  • Documentation for design spec in module level and chip level
  • IP module integration with direction of integration guide
  • FPGA prototyping development and debug
  • Evaluation of different architecture solutions
  • Define architecture of the CPU core and various hardware components surrounding the CPU, like local memory, interconnect and crypto accelerators

Qualifications:

  • Familiar with Tilelink/AMBA/AXI bus protocol
  • 4+ years of relevant experience on IP based front-end design
  • Familiar with EDA tools of simulator and synthesis, spyglass,
  • Experience with C/C++ program for driver or algorithm implementation
  • Experience of FPGA design and debug with JTAG
  • Good coding style for RTL design
  • Good people and communication skills in Mandarin and English

Big Plus:

  • Familiar with foundry lib, IP and process technology limitation
  • Familiar with tool chain (RTL, P&R, timing analysis/closure, power analysis, etc.)
  • Knowledge or project experiences of RISCV CPU
  • Knowledge of project experiences on SystemC modeling
  • Interest and experience for IP and chip design with chisel
  • Broad understanding to computer security and crypto algorithms like AES/SHA/RSA/ECC