At SiFive, you’ll be part of a fun, engaging team and be afforded the opportunity to grow within the company. You will bring fruition the new RISC-V architecture and enable its rapid adoption by implementing new tools, breakthrough design methods and services. We need people who are trail-blazers, aren’t afraid to take a chance, and don’t always “go with the flow”.
- Plan the verification of complex digital design blocks by fully understanding the design specification and interacting with design engineers to identify important verification scenarios
- Create verification environment or test bench using System Verilog, UVM and/or C++
- Identify and write all types of coverage measures for stimulus and corner-cases
- Debug tests with design engineers to deliver functionally correct design blocks
- Responsible for SoC's IP Level and Top Level verification, Pre-sim and Post-sim verification as owner
- Build test cases, analyze validation results, and improve validation quality
- Close coverage measures to identify verification holes and to show progress towards tape-out
- BS degree or equivalent practical experience. MS in EE or CS is preferred
- 3+ years of relevant experience on IP based SoC verification
- Familiar with Tilelink/AMBA/AXI bus protocol
- Experience with verification methodology such as UVM/OVM/VMM/SystemC/C++
- Experience with System Verilog and SVA and Functional Coverage
- Experience with the full verification life cycle and experience with functional coverage
- Experience with function verification for common SoC building blocks: I2C/UART/SPI/I2S/USB, etc.
- Strong problem solver, communicator and team player
- Good people and communication skills in Mandarin and English
- Scripting skills in Perl, tcl, shell, etc.
- Experience in the verification SoC with ARM MCU/CPU and DSP
- Experience in validation/verification for RISC CPU/MCU core design
- Experience in coding and simulation of chisel