San Mateo, CA
We are automating the design process to democratize access to silicon. As a DFT Architect in the Implementation group, you will shape the company-wide methodology to significantly scale the number of designs a single team can manage. We need out-of-the-box thinking to automate the DFT, this is an opportunity for a DFT expert to define unique methodologies.
- Help design a robust design for test methodology
- Deploy new DFT methodologies to company sites across the world
- Enable other engineers to execute all aspects of DFT insertion and simulation.
- Collaborate with other technical leads to revolutionize the chip design industry: Instead of the question being, “how many engineers it takes to do a chip?”, we want to reframe it to ask, “how many chips an engineer can make?"
- Join us as we create a fully automated online chip design methodology.
What you bring
- A minimum of 8 years of experience with DFT
- Experience managing all aspects of design for test for an SOC: scan, MBIST, and 3rd party IP integration
- Experience integrating DFT of complex mixed signal IPs
- Expertise in DFT IP reuse: IEEE 1500, core wrapping, and IEEE 1687
- Strong understanding of timing constraints
- Thorough knowledge of the RTL to GDS implementation flow
Education / Certifications
- Master’s degree required with emphasis in Electrical Engineering, Computer architecture, or Computer Science
SiFive is proud to be an equal employment opportunity workplace. We offer a competitive compensation package that includes flexible paid time off, health, vision and dental benefits, 401(k) plan, employee stock option program, and much more. If you yearn to be challenged and wish to work in an environment where the boundaries of your creativity and skills will be tested, then SiFive is place for you.