The SiFive Download

April 25, 2019

Welcome Back!

It’s been a while since our last newsletter - a lot has happened since we last reached out, not the least of which was the release of our latest core IP, the SiFive S2 Series Core IP, which is the world’s smallest 64-bit RISC-V based embedded core. Designed for edge computing loads, the S2 Series further adds to our extensive, vastly customizable, optimized, silicon-proven embedded core IP portfolio.

We’ve also expanded our offerings with a new IP enablement platform in 7 nm FinFET. The tapeout includes critical IP validation of our high bandwidth memory (HBM2E), 3.2 Gbps interface, 2GHz Ternary Content-Addressable Memory (TCAM) partner IP, a low-voltage differential signaling (LVDS) interface and other key IP building blocks.

Interested in trying out our newest releases? Swing by our website and sign up for access to SiFive Core Designer, which will allow you to access best-in-class SiFive core IP and the tools to customize it to your exact specifications. See what customers like DinoplusAI, Synaptics, Western Digital and others are using to develop their custom SiFive based RISC-V designs. And check out our new HiFive1 Rev B development board, available through CrowdSupply.

New Webinar Series

Back by popular demand, SiFive Sr. Product Marketing Manager Drew Barbier will give another series of webinars aimed at introducing a new audience to RISC-V and SiFive’s products and workflow. Webinar Series

  • May 7th, 10:30am PST: An Introduction to the RISC-V Architecture
    This webinar will introduce RISC-V Architecture. It will provide an overview of RISC-V Modes, Instructions and Extensions, Control and Status Registers, and Interrupts. It is targeted at embedded developers who are new to RISC-V.

  • May 15th, 10:30am PST: SiFive’s 2 Series Core IP
    This webinar will introduce SiFive’s 2 Series Core IP, SiFive’s smallest and most efficient RISC-V Processor IP, which is ideal for embedded applications from microcontrollers to control processors to IoT applications. This webinar will cover the 2 Series Core architecture, the configurability of the 2 Series, and the Core Local Interrupt Controller (CLIC).

  • May 23rd, 10:30am PST: From a Custom 2 Series Core to Hello World in 30 Minutes
    The last webinar will be very hands-on! Drew, the host, will walk through configuring a custom E2 core using SiFive Core Designer, and then use Freedom Studio to write software targeting the custom core in the included RTL testbench and on an FPGA.

Here, There and Everywhere ...

In addition to all this good news, we’ve also had a lot of really great experiences so far in 2019. We’ve seen so many of our customers and RISC-V enthusiasts at CES, Mobile World Congress, Embedded World and many other conferences. It’s been great to talk with you all about your interest in SiFive’s Core IP and Core Designer. Here’s an update on where we’ve been the past few weeks:

Building on the success We kicked off our global RISC-V Technical Symposia series with sessions in the Bay Area, Boston and Austin to great success, the first of more than 50 planned meetings around the world. The free events are designed to promote the open instruction set architecture and foster deeper collaboration and engagement with the global open-source community. In the coming months, we’ll bring the Symposia to China and Europe. Click the link above to find out where we’ll be next and register to attend a session near you. RISC-V Technical Symposia

We’ve been busy attending a number of industry events as well. Earlier this month, our CTO and cofounder, Yunsup Lee, spoke on “Extending and Optimizing 64-bit RISC-V Processors” at IP-SOC. Around the same time, our chief engineer and cofounder, Krste Asanovic, gave a talk during the Linley Spring Processor Conference on customizing RISC-V SoCs for artificial intelligence applications.

Forum Highlight
The SiFive Forums are buzzing! They are packed with valuable content that can answer your questions and satisfy your curiosity surrounding RISC-V, development boards, IP evaluations and much more. Here’s a peek at some of the threads that caught our attention (and will now have yours, too!):

SiFive in the Press
Want to see who has been talking about SiFive recently? Let's take a look!
Synaptics announces shift to RISC-V processors, by Gareth Halfacree,
Start developing for RISC-V with the $49 HiFive1 Revision B, by James Sanders, TechRepublic
CHIPS Alliance to curate building blocks for RISC-V chips, by Eric Brown, LinuxGizmos
HiFive1 Rev B wireless open source RISC-V development platform, by Julian Horsey, Geeky Gadgets
The Linux Foundation announces the CHIPS Alliance project for deeper open source hardware integration, by Sugandha Lahoti, Packt
SiFive Rolls Out RISC-V HiFive1 Rev B Development Platform, $49 USD With FE310-G002 SoC, by Michael Larabel, Phoronix

RISC-V in the News
We’re always keeping an eye on RISC-V; after all, our founders invented it! Check out the latest conversations around the RISC-V ISA:

8 RISC-V Companies to Watch by Christopher Wiltz, Design News
5 Key Takeaways from the RISC-V Roadshow in Boston, by Dan Mandell, VDC Research
Multi-core, Linux-ready RISC-V cores feature DSP, by Eric Brown, LinuxGizmos
Calista Redmond named CEO of RISC-V Foundation, by Staff, InsideHPC
Linux Foundation launches FOSSi-focused CHIPS Alliance, by Gareth Halfacree, Bit-tech
RISC-V Foundation Hosting Worldwide Series of Getting Started with RISC-V Events, by Gary Elinoff, All About Circuits
5 Key Takeaways from the RISC-V Roadshow in Boston, by Dan Mandell, VDC Research

We would love to hear from you - reply to this email with any questions or inquiries, and we will get right back to you!

Thanks for your continued support!

Until next time,
Jack and the team at SiFive

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