Webinar Series

Getting Started with SiFive’s SoC IPs

Introduction to SiFive’s SoC IPs: Interlaken, HBM, Ethernet, USB etc.

Chip-to-Chip Communication (Interlaken-LL) for Enterprise and Cloud

Interlaken chip-to-chip connectivity IP has been used for many years in networking and switching fabrics to move high throughput data between large chips. With advanced technology nodes, increasing chip sizes and CPU cluster-based designs, Interlaken has found a unique spot as the protocol of choice for low latency, high throughput chip-to-chip connectivity. SiFive is extending its 8th generation of Interlaken IP with the introduction of Interlaken-Low Latency (LL) IP, which will enable low latency chip-to-chip connectivity in HPC, AI/ML, enterprise and cloud applications. Interlaken-LL IP can provide up to 256Gbps of reliable and scalable throughput between two chips; whereas the standard Interlaken IP from SiFive provides throughput of up to 1.2Tbps.

Watch Recording

Webinar info

One hour

2020-03-19

Post Webinar Materials

Presentation Slides

2020-03-19

Q&A

2020-03-19

Hosted by

Ketan Mehta

Director of SoC IP Product Marketing

As the Director of SoC IP Product Marketing at SiFive, Ketan Mehta is responsible for Interlaken, Ethernet, HBM memory and other high-speed interfaces. With over 25 years of experience in engineering and product planning, Ketan has a rich background in IP connectivity solutions for various applications including networking, storage, data center and cloud. He received his M.S. degree in electrical engineering from The University of Texas at San Antonio, and his MBA from San Jose State University.

Sundeep Gupta

Senior Director of SoC IP

As the Senior Director of SoC IP at SiFive, Sundeep Gupta leads the company’s IP engineering effort and manages the entire soft IP portfolio including Interlaken, Ethernet, HBM, USB, LPDDR controller, and low speed peripherals. Sundeep has more than 21 years of experience in delivering high quality silicon and IPs. He earned his M.S. degree in electrical engineering from The Ohio State University, and his B.E. in electronics and telecommunications from the College of Engineering Pune.

Daniel Nenni

Daniel Nenni has worked in Silicon Valley for the past 30 years with computer manufacturers, electronic design automation software, and semiconductor intellectual property companies. He is the founder of SemiWiki.com, an open forum for semiconductor professionals, and the co-author of two books includingFabless: The Transformation of the Semiconductor IndustryandMobile Unleashed: The Origin and Evolution of ARM Processors in our Devices. Daniel is an internationally recognized business development professional for companies involved with the fabless semiconductor ecosystem.

About us

SiFive was founded by the creators of the free and open RISC-V architecture as a reaction to the end of conventional transistor scaling and escalating chip design costs.

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Webinar

Chip-to-Chip Communication (Interlaken-LL) for Enterprise and Cloud

Interlaken chip-to-chip connectivity IP has been used for many years in networking and switching fabrics to move high throughput data between large chips. With advanced technology nodes, increasing chip sizes and CPU cluster-based designs, Interlaken has found a unique spot as the protocol of choice for low latency, high throughput chip-to-chip connectivity. SiFive is extending its 8th generation of Interlaken IP with the introduction of Interlaken-Low Latency (LL) IP, which will enable low latency chip-to-chip connectivity in HPC, AI/ML, enterprise and cloud applications. Interlaken-LL IP can provide up to 256Gbps of reliable and scalable throughput between two chips; whereas the standard Interlaken IP from SiFive provides throughput of up to 1.2Tbps.

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