Upcoming Webinar Series

SiFive Connect

The SiFive Connect webinar series is designed to be highly educational and interactive, offering attendees a direct connection to industry experts. Each one-hour long webinar will take place twice on the same day – once at 9 a.m. PDT and again at 6 p.m. PDT enabling our global audience to choose the time that works best for them.

SiFive HBM2/2E IP Subsystem - Features and Implementation Guidelines

Webinar info

one-hour, 9:00 AM PDT and 6:00 PM PDT

2020-05-14

Details

Join us for our next SiFive Connect webinar to learn more about the features of the HBM2/2E IP subsystem and how to implement the IP in an SoC. We’ll also address the market applications for HBM2/2E IP.

SiFive’s HBM2/2E IP subsystem solution is architected and designed to provide the highest performance and flexibility for integrating high bandwidth memory (HBM) directly into next-generation ASIC and 2.5D SoC system-in-package (SiP) solutions. It supports the HBM2/2E JEDEC specification for a multitude of foundry technology nodes.

Key Learnings

  • Features of the HBM2/2E IP subsystem
  • Implementation guidelines for 2.5D SoC SiP
  • Market applications and other details

Target Audience

AI chip designers, DRAM memory controller designers, high-speed interface IP designers, IP application engineers, IP architects and system engineers.

Speakers

Ketan Mehta, Director, SoC IP Product Marketing, SiFive, Inc.

Pranav Kale, Staff Engineer, SoC IP Engineering, SiFive, Inc.

Ritam Das Adhikari, Manager, SoC IP Applications, SiFive, Inc.

Moderator

Michael Gianfagna, Analyst, SemiWiki

SiFive USB 3.2 IP Solutions Including Retimer for High-Speed Consumer Applications

Webinar info

one-hour, 9:00 AM PDT and 6:00 PM PDT

2020-06-18

Details

Join us in this webinar to learn more about our USB 3.2 IP solution, including Retimer, for high-speed consumer applications. We will review the IP engineering features, operations, configurations, protocols and implementation guidelines in detail.

SiFive's USB 3.2 Gen2 Retimer IP cores are compliant with the USB 3.2 Appendix E standard. USB 3.2 Gen 2 supports up to 10 Gbps of bandwidth. It includes a USB 3.2 Gen2 single lane PCS layer and supports all low power states.

Key Learnings

  • Features of the USB 3.2 Gen2 IP cores
  • Implementation guidelines – integration and testing
  • Market outlook, applications and other details

Target Audience

Consumer product chip designers, high-speed interface IP designers, IP application engineers, IP architects and system engineers.

Speakers

Ketan Mehta, Director, SoC IP Product Marketing, SiFive, Inc.

Vikas Aravind Kulkarni, Director, SoC IP Engineering, SiFive, Inc.

Moderator

Eric Esteve, Founder of IPnest and Analyst at SemiWiki

SiFive Storage Solutions

Webinar info

one-hour, 9:00 AM PDT and 6:00 PM PDT

2020-06-11

Details

Currently, there is a huge demand in the market for storage systems. Reliability, high endurance and robustness are the essential features, which are very much required for such systems. Therefore, SSD controller-based storage solutions are most preferred for data centers.

Join us in this webinar to learn more about our offerings for storage solutions based on SSD controllers. We will review the market needs, standards, engineering and methodology for designing a RISC-V based SoC/ASIC for storage solutions.

Key Learnings

  • Exploration of storage solutions
  • SSD Controllers – Reason for huge demand in the storage market
  • Engineering & Methodology – RISC-V based SoC/ASIC

Speaker

Sudhir Mallya, Senior Director, Vertical Marketing

SiFive Vision Solutions

Webinar info

one-hour, 9:00 AM PDT and 6:00 PM PDT

2020-06-25

Details

As the world moves toward the next industrial revolution, the need for artificial intelligence (AI) has become a quintessential requirement. Currently, data in the form of images is used as input to process the result/output, thereby enabling the human as well as the machine to make smart and intelligent decisions based on these processed outputs. For such intelligent decision making, we need a chip that can process real time data and provide us ~100% accurate results.

Join us in this webinar to learn more about our offerings for vision solutions. We will review the market needs, engineering and methodology for designing a RISC-V based SoC/ASIC for AI vision solutions.

Key Learnings

  • Exploration of vision solutions
  • AI – Market requirement and future needs
  • Engineering & Methodology – RISC-V based ASIC

Speaker

Christopher Moezzi, Vice President & General Manager, AI/ML Solutions

A Comprehensive Trace and Debug Solution for RISC-V ISA

Webinar info

one-hour, 9:00 AM PDT and 6:00 PM PDT

2020-07-16

See Details

Coming soon

SiFive Ethernet IP Subsystem

Webinar info

one-hour, 9:00 AM PDT and 6:00 PM PDT

2020-07-30

Details

Coming soon

SiFive Connect

The SiFive Connect webinar series is designed to be highly educational and interactive, offering attendees a direct connection to industry experts. Each one-hour long webinar will take place twice on the same day – once at 9 a.m. PDT and again at 6 p.m. PDT enabling our global audience to choose the time that works best for them.