Enhancements to SiFive’s RISC-V IP Portfolio in the 20G1 Release
Join us in this webinar to learn about all of the enhancements to the SiFive™ RISC-V IP portfolio introduced in the 20G1 release, which is now available.
Webinar 20G1 Release
10:30 am - 11:30 am PST / 1:30 pm - 2:30 pm EST
Join us in this webinar to learn about all of the enhancements to the SiFive™ RISC-V IP portfolio introduced in the 20G1 release, which is now available. Product manager Drew Barbier will dive deep into the product updates, including significant performance, power and area improvements, as well as new features like enhanced deterministic real-time capabilities, support for Xilinx UltraScale+-based VCU118 FPGA evaluation kit, support for FreeRTOS v.10, and the availability of fully integrated SiFive Shield™ Security and SiFive Insight™ Trace & Debug solutions. Numerous other enhancements will also be covered in this tutorial.
Director, SiFive Core IP Product Management
Drew has worked in the Semiconductor industry for over 10 years in various engineering and customer facing roles. At SiFive Drew is responsible for a variety of tasks including customer support, software and development tools, ecosystem development, documentation, and whatever makes the customer experience great.