SiFive's readily available RISC-V based platform includes a wide range of peripherals on AXI/Tile Link interfaces. The list of peripherals include, but are not limited to SPI, QSPI, UART, RTC, I2C and GPIOs. Please contact SiFive sales to find out about the complete range of peripherals with various configurations.
Peripherals (SPI, QSPI , RTC, I2C, WDT, UART, GPIO)
The SPI controller supports master-only operation over the single-lane, dual-lane, and quad-lane protocols. The baseline controller provides a FIFO-based interface for performing programmed I/O. Software initiates a transfer by enqueuing a frame in the transmit FIFO; when the transfer completes, the slave response is placed in the receive FIFO.
Quad SPI Flash Controller (QSPI)
The dedicated QSPI flash controller connects to external SPI flash devices that are used for execute-in-place code. SPI flash is not available in certain scenarios such as package testing or board designs not using SPI flash (e.g., just using on-chip OTP).
Real-Time Clock (RTC)
The real-time clock maintains time for the system and can also be used to generate interrupts for timed wakeup from sleep-mode or timer interrupts during normal operation.
I2C is a synchronous, multi-master, multi-slave, packet switched, single-ended, serial computer bus.
Watchdog Timer (WDT)
The WDT is used to cause a full power-on reset if either hardware or software errors cause the system to malfunction. The WDT can also be used as a programmable periodic interrupt source if the watchdog functionality is not required. The WDT is implemented as an upcounter in the Always-On domain that must be reset at regular intervals before the count reaches a preset threshold, or else it will trigger a full power-on reset.
The UART peripheral supports the following features:
• 8-N-1 and 8-N-2 formats: 8 data bits, no parity bit, 1 start bit, 1 or 2 stop bits
• 8-entry transmit and receive FIFO buffers with programmable watermark interrupts
• 16× Rx oversampling with 2/3 majority voting per bit
The GPIO controller is a peripheral device mapped in the internal memory map. It is responsible for low-level configuration of the actual GPIO pads on the device (direction, pull up-enable, and drive value), as well as selecting between various sources of the controls for these signals. The GPIO controller allows separate configuration of each of N GPIO bits.