SiFive Perspective: RISC-V SPMP Specification Ratification is a Leap Forward for Embedded Security

The broader RISC-V standards process continues to deliver innovation that responds dynamically to evolving market needs. If you didn’t see the announcement, in an important milestone for the open hardware ecosystem, the RISC-V Board of Directors officially ratified the S-mode Physical Memory Protection (SPMP) version 1.0 specification on August 20, 2026. This newly ratified SPMP capability is designed specifically to strengthen memory protection in embedded systems running Real Time Operating Systems (RTOS). SiFive is pleased to have played a role in this process as we continue to collaborate across the ecosystem to improve the RISC-V standard, and we are confident that SPMP will be rapidly adopted across the industry.

The Power of Open Collaboration Across the Supply Chain

What is probably most notable about the SPMP specification is the unprecedented level of teamwork it represents. The contributors to this specification include experts from leading companies, universities, and research organizations in several countries. Led by Bicheng Yang, under the governance of the RISC-V Privileged ISA Committee and the SPMP Task Group, this effort brought together voices from all parts of the semiconductor supply chain.

IP vendors such as SiFive, global silicon suppliers, OS developers, and hypervisor engineers all worked together closely to get the best possible solution to add these vital new capabilities to the RISC-V architecture.

What is Special About SPMP?

As embedded systems become more complex, the need for robust layering and separation of software increases dramatically. Historically, many simple embedded systems operated with flat memory models, which pose security and stability risks in modern edge and IoT applications.

The SPMP extension addresses this by enforcing stringent privilege levels and execution control. Specifically, SPMP provides hardware-enforced isolation that protects the supervisor mode (S-mode) RTOS from user mode (U-mode) tasks and applications. This means the architecture now fully and securely supports distinct layers:

• Machine Mode (M-mode): Where the hypervisor and firmware operate.
• Supervisor Mode (S-mode): Where the operating system (RTOS) securely runs, shielded from lower-level tasks.
• User Mode (U-mode): Where the individual tasks and applications execute.

By isolating the RTOS from potentially buggy or malicious user-level code, SPMP ensures high reliability. Similarly, isolating the M-mode hypervisor from the RTOS kernel provides another level of essential separation. Furthermore, SPMP acts as a cornerstone for a comprehensive new RISC-V security roadmap, complementing other upcoming security standards such as RISC-V Worlds (for secure global hardware partitioning).

What Comes Next? With the growth of hypervisors across many embedded systems, there are already lots of active efforts to extend SPMP to enable real-time hypervisors to be even more segregated and robust. Future developments will leverage SPMP as a foundation for hardware-enforced, software-defined virtualization and Trusted Execution Environments (TEEs).

One of the benefits of RISC-V is constant improvement and change with the input of a global community. The ratification of SPMP version 1.0 marks a new chapter for embedded security, and highlights the collaborative work that is pushing the boundaries of open computing to new levels.

Learn More & Get Involved

If you want to learn more about the technical details, read the official announcements, or view the specifications, some helpful links are below:

• RISC-V Tech Announce: SPMP Ratification
• RISC-V SPMP Atlassian Wiki
• Official RISC-V SPMP GitHub Repository

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Author

Richard York is a Product Director for SiFive and has worked in the semiconductor IP industry for almost 30 years, including more than 25 years at Arm. Automotive has been a key part of his career, managing IP products, roadmaps and ecosystems. He’s worked across the supply chain, with semiconductor companies, Tier Ones and OEMs, playing a major role in the adoption of processor IP in Semiconductor MCUs and SoCs.