SiFive congratulates Arm on its IPO, which represents a momentous step forward for the entire semiconductor ecosystem. This IPO has brought more awareness to the public about the critical role of computing architectures, specifically the instruction set architecture (ISA), and the need for high-quality, high-performance processor IP to drive our industry forward. Competition is essential for a healthy semiconductor industry, and we continue to hear from companies about the importance of having choice in the processor market, especially after the chip supply challenges of the last few years. Arm has helped focus a spotlight on the ISA and CPU IP, and is highlighting its criticality to the fastest growing areas of semiconductors, areas like datacenter and AI, automotive, consumer, and mobile. 

Part of the excitement has been a new recognition of how big the market opportunities are, and there is room for all of us. These markets need rapid innovation and customization, which are consistent themes in our conversations with customers. It’s no secret that SiFive’s founders developed RISC-V as a response to the limited customization options of closed, proprietary architectures. We work with global technology leaders and SiFive’s high-performance IP is being designed into everything from aerospace applications to automotive, the datacenter, wearables, and beyond. While the semiconductor landscape has evolved considerably since then, what hasn’t changed is that companies want design flexibility and freedom: SiFive and RISC-V make that possible. After all, there are no limits with RISC-V.


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Arm IPO Underscores the Ongoing Compute Supercycle 

SiFive recently received its official ASIL-B Ready Functional Safety Certificate from the SGS-TUV organization, and to understand the implications, I discussed this achievement with SiFive’s industry recognized Automotive Functional Safety experts, Priyanka Thachakuzhiyil Viswanathan, Director Functional Safety and Cybersecurity, and Monia Chiavacci, Sr. Principal Architect, Functional Safety. This is a great step forward for our customers. Here’s what I learned. 

In September 2022, we announced the SiFive Automotive™ E6-A, X280-A, and S7-A solutions to address the critical needs for current and future applications like infotainment, cockpit, connectivity, ADAS, and electrification, as the market transitions to zonal architectures and manufacturers require the energy efficiency, simplicity, security, and software flexibility that RISC-V offers. We partnered with TUV SGS in parallel to begin the first in a series of confirmation measures (confirmation measures include confirmations reviews, functional safety audit and FuSa assessment) for this product line. 

We are pleased to have achieved the first milestone, with TuV SGS ASIL -B Ready certification, for the SiFive E6-AB IP core from this automotive series product line. This is a confirmation that SiFive E6-AB Core Complex’s safety architecture can meet the hardware architectural metrics (SPFM and LFM) requirements for ASIL B. For mere mortals, such as myself, these refer to the Single Point Failure Metric and the Latent Fault Metric, which are relative hardware architectural metrics specified by ISO 26262 to quantify the effectiveness of a design against random hardware faults.

This means we have evidenced to TuV SGS, via our safety manual and safety analysis report (using the Failure Modes Effects and Diagnostic Analysis (FMEDA) and Dependent Failure Analysis (DFA)), that E6-AB Core Complex can meet the SPFM target >= 90% and LFM target>= 60%. This is a great demonstration of our automotive technical capability and strong commitment to customers requiring functional safety standards conformance, ensuring as a first step, that our IP technology is designed with a “Safety Architecture” that will address their functional safety needs in that foundational technology. Best of all, this certification was achieved solely based on the IP’s hardware safety mechanisms, meaning no software test library (STL) creation or integration is required for this part of an overall system certification.

This also prepares us for the next step, the functional safety assessment with TUV SUD, building upon this earlier foundation. This will include the following: <li> ASIL D systematic capability (Process) assessment for E6-AB, as well as the other variants in the family designed specifically with ASIL-D features, E6-AD and E6-AS
<li> ASIL B diagnostic capability assessment for E6-AB as part of FuSa assessment on top of already existing ASIL B ready certificate
<li> ASIL D diagnostic capability assessment for E6-AD and E6-AS in lock mode.


To be clear, this will add the assurances that the entire SiFive development process and the life cycle of our products conforms to the requirements for ASIL D, which is of the highest rigour possible as suggested by ISO 26262 for the design and development of products. From marketing requirements to RTL implementation and delivery, including customer support, errata management and product end-of-life policies and procedures, these robust processes ensure quality, and becomes a part of our ability to design, deliver and support our IP technology for our customers. 

With significant design wins with key automotive vendors, SiFive has strong momentum in automotive and this plan demonstrates to our customers that our products are developed to more stringent design and development processes than even those targeted for ASIL B applications. Our strong team of functional safety experts is working closely with our automotive cores design team to create exciting new automotive solutions. Customers can incorporate our products in applications requiring these specific higher integrity levels with confidence. 

For more information about our Automotive Solutions family of products, please visit our automotive [web pages](https://www.sifive.com/cores/automotive) or to talk to us about your specific challenges [contact sales](https://www.sifive.com/contact-sales).

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ASIL B Ready Certification for SiFive Automotive Solutions


**Bob Monkman (SiFive), with Bill Lamie (PX5) and Rafael Taubinger (IAR)**

I recently had a great conversation with Bill Lamie, President/CEO of PX5,  and Rafael Taubinger, Sr. Product Marketing Manager at IAR, regarding the recent port of the industrial-grade PX5 RTOS to the SiFive HiFive Rev B RISC-V development board (powered by a 32-bit SiFive RISC-V embedded microcontroller), using the IAR Embedded Workbench tools suite. I wanted to understand why Bill, who has been a serial innovator in embedded for decades, chose SiFive and IAR as the platform and development solutions, respectively, for his most recent venture. And, since I wasn’t yet familiar with the PX5 RTOS, I wanted to gain some insights into this latest technology. 
As a veteran of the RTOS market myself, I was super impressed that PX5 can be configured for minimal size, requiring less than 1KB of Flash and 1KB of RAM on 32-bit microcontrollers. The kernel features native POSIX threads API, making it portable and familiar to developers across the spectrum. The PX5 team has a particular focus on extensive validation and verification to enable use in safety-critical applications that require documented safety practices. 

This was a big reason they used the ubiquitous IAR Embedded Workbench tools as well. The IAR solutions have been around for 40 years and have been used in countless safety-critical use cases with worldwide customers. The available functional safety edition is certified by TÜV SÜD and complies with the requirements of ISO 26262, IEC 61508, IEC 62304 and many more standards. IAR has a complete development toolchain with a highly optimizing compiler, and a great debugger that has been one of Bill’s favorite debuggers for the 20+ years he has been working with the IAR team. He told us that he recently used IAR’s code coverage analysis tools to ensure 100% code coverage in his own test framework for the PX5 RTOS, and the code analysis tool IAR C-STAT to meet MISRA and other coding standards established to deliver demonstrably high-quality code to the market.

Like a fast growing number of software vendors in the market today, both PX5 and IAR recognize that the RISC-V open ISA standard is gaining tremendous momentum, and they’re intent on delivering verified commercial support for RISC-V to their customers as the inevitable demand grows. I asked Bill why he chose SiFive as a RISC-V go-to-market partner, and the answer there was also consistent with what we hear every day from the ecosystem. 
PX5 sees SiFive as a leading RISC-V IP provider by multiple measures. They appreciate that SiFive’s founders are the same team who invented the RISC-V Instruction Set Architecture (ISA) in 2010, and that SiFive is a key thought leader and innovator in the evolution of RISC-V ISA in the overall ecosystem. SiFive is addressing a broad swath of market segments, including the safety-critical applications that PX5 is seeking to be ready to address. SIFive supports a single, consistent instruction set across all of our product offerings, increasing portability, while reducing costs and maximizing the energy efficiency, simplicity, security, and flexibility upsides that RISC-V offers.

This all makes great sense, and we at SiFive appreciate the enthusiasm and trust of software partners like PX5 and IAR, who are working together with us to deliver terrific value to the market.
 
For a free evaluation of the Px5 RTOS on the SiFive HiFive1 RevB board, please [visit](https://px5rtos.com/free-rtos-download-evaluations) and scroll down to the SiFive section. 

More information about PX5 RTOS is available [here](www.px5rtos.com). 
For more information on IAR solutions for RISC-V, please [visit](www.iar.com/riscv). 



Expanding the RISC-V Ecosystem, with PX5, IAR and SiFive

You are invited to attend an upcoming [webinar](https://www.eventbrite.com/e/silicon-catalyst-webinar-sifive-maximizes-compute-density-with-its-risc-v-tickets-629304716347?utm_campaign=industry&utm_medium=social-organic&utm_source=linkedin&utm_content=field_high-tech_Silicon-Catalyst-Webinar_1-few_webinar-3rd-party_register_na_en_us&campaignID=7015w000001Cok2AAC&utm_term=silicon-catalyst-webinar) where Ansys will talking with SiFive's Phil Dworsky to discuss the pursuit of maximum compute density in our RISC-V processor cores. 

The presentation will cover topics such as managing dynamic power throughout the design process and creating efficient power distribution networks that meet voltage drop requirements. By attending, you will gain valuable insights into design flows that can help you achieve these objectives in your own projects. 

Don't miss out on this exciting opportunity to learn from industry experts and stay ahead of the curve. Register now to secure your spot.

You can register [HERE](https://www.eventbrite.com/e/silicon-catalyst-webinar-sifive-maximizes-compute-density-with-its-risc-v-tickets-629304716347?utm_campaign=industry&utm_medium=social-organic&utm_source=linkedin&utm_content=field_high-tech_Silicon-Catalyst-Webinar_1-few_webinar-3rd-party_register_na_en_us&campaignID=7015w000001Cok2AAC&utm_term=silicon-catalyst-webinar)


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Ansys Joint Webinar: SiFive Maximizes Compute Density With Its RISC-V Processor Cores

In March, SiFive announced the opening of its new office in the greater Boston area. 2022 was a monumental year for SiFive and 2023 is shaping up to be another strong year. Marlborough was an ideal location for the new office as the company continues to expand its footprint and serve our growing customer base located in Massachusetts and the surrounding Northeast region. 

The office will be led by Shubu Mukherjee, vice president of architecture at SiFive, with plans to grow its headcount in the next 12-to-24 months. The greater Boston area is rich in talent in all areas of semiconductor development, including architecture, RTL, digital verification, and physical design, as well as sales, marketing, and business development. Having a physical presence in the area will help reach both experienced professionals as well as tap into the strong University programs in the region.

 ![SiFive Boston team members celebrate opening](https://images.prismic.io/sifive/d325b28f-01dc-4270-bb0a-4464b7fe5938_img_0665.jpeg?auto=compress,format) 
SiFive is always seeking talented designers and engineers ready to make an impact on the world and help accelerate the adoption of RISC-V. You can always check our website for open roles. [Careers](https://www.sifive.com/careers) 


SiFive Expands U.S. Presence with New Office in Boston

As the inventors of RISC-V and performance density leaders, SiFive is committed to spreading the word about how this groundbreaking open architecture is reshaping the computing industry and ushering in new possibilities. Last week, we hosted the [SiFive Tech Forum in Hsinchu](https://www.youtube.com/watch?v=o8jrPQQvzGw), the technology heart of Taiwan, to bring together hardware engineers, developers, and other technology leaders to talk about the incredible momentum of RISC-V to-date and how SiFive is leading the RISC-V revolution. The event was well over subscribed, which highlighted the eagerness with which the attendees were keen to learn about the latest SiFive solutions. Read on to find out more about what we covered during the SiFive Tech Forum.  And you can view the presentations [here](https://www.youtube.com/@sifiveInc)

 ![Taiwan event](https://images.prismic.io/sifive/fc2afe63-cd62-4fa0-8654-7bfedee7ebee_IMG_4425.jpg?auto=compress,format)

 
Jack Kang, SVP, Business Development, Customer Experience, and Corporate Marketing kicked things off by talking about the RISC-V Revolution and emphasizing how RISC-V is inevitable and has no limits, and highlighted SiFive leadership in driving RISC-V into every technology market. There are billions of RISC-V cores in the market and the demand for the flexibility and freedom that RISC-V enables is growing stronger every day. SiFive’s RISC-V portfolio has already been adopted for a wide variety of markets – from aerospace to automotive to consumer devices, and the datacenter – and we’re rapidly expanding our global footprint as we work with the biggest and best technology companies across APAC, Europe, North America, and beyond. 


![A packed house](https://images.prismic.io/sifive/b9a70681-7f50-4d7f-853b-ed2e2d1d28ab_IMG_4399.jpg?auto=compress,format)

Our team then dove into the impressive compute performance and efficiency of SiFive’s new P600 and P400 series of RISC-V processors, which are perfectly tuned to offer the best power and performance efficiency and compute density for next generation wearables, the smart home, industrial automation, and other consumer devices. 

Another area we addressed is how SiFive is accelerating AI/ML innovation with our SiFive Intelligence solution. SiFive Intelligence is a high-performance AI dataflow processor with scalable vector compute resources to meet the complex processing and data management requirements of AI/ML applications, from extremely low power to high-performance compute. 

Of course, we also had to talk about automotive, a huge growth opportunity for SiFive and RISC-V. As the automotive market transitions to zonal architectures, manufacturers see significant benefits in the energy efficiency, simplicity, security, and software flexibility that RISC-V offers all within a single Instruction Set Architecture (ISA). SiFive offers the broadest range of high-end automotive applications and real-time automotive processors, offering industry-leading performance, with the lowest area and power consumption, and tailored to vehicle specific needs for safety, security, and performance. 

To finish off the day, we shared an update on the latest RISC-V tools, software, and development boards. We’re especially excited about the upcoming HiFive Pro P550 Development System (previously code-named Horse Creek) that we’re unveiling in partnership with Intel this summer. This high performance platform features a quad-core SiFive Performance™ P550 processor and is implemented in the Intel 4 technology platform. We also showcased how the RISC-V partner ecosystem is delivering the comprehensive range of solutions including compiler tool chains, integrated open application environments, advanced debug and trace solutions, application protocol middleware, real-time operating systems, and FPGA kits to meet the needs of the market now and in the future.  

We’d like to thank everyone who attended the SiFive Tech Forum, and our team’s hard work in making it a success!



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Unleashing the Potential of RISC-V: A Recap of the SiFive Tech Forum

SiFive is in attending 2023’s embedded world from March 14-16, and we’d love to see you there! Meet us in Nürnberg to learn about some of our recent announcements, including our new processors for wearables. These new processors, the P670 and P470, offer unrivaled choice and flexibility with the perfect balance of performance and efficiency. The P670 is ideal for applications like premium wearables, networking, robotics, and mobile. Meanwhile, the P470 – SiFive’s first efficiency-focused Out-of-Order, area optimized, vector processor – is designed for applications like wearables, consumer, and smart home devices.

In case you missed it, we also recently introduced new automotive processors. SiFive’s Automotive X280-A, E6-A, and S7-A solutions address critical needs for current and future automotive applications like infotainment, cockpit, connectivity, ADAS, and electrification. The X280-A (the automotive version of SiFive’s X280 vector processor) has industry-leading performance to meet the complex computing requirements of sensor fusion and ML intensive workloads. The E6-A series is designed for real-time, 32-bit applications including system control, hardware security modules (HSMs), and safety islands, and also serves as a standalone solution for microcontrollers. Additionally, the S7-A is a 64-bit, high-performance real-time core optimized for the needs of modern SoCs with performant safety islands. 

Let us know if you’d like to set up a meeting to learn more about these new products and how the open era of computing is transforming the semiconductor industry. SiFive saw record growth in 2022 driven by global demand for RISC-V and a growing awareness of it's compute density and power efficiency advantages.  We work closely with more than 100 leading customers in applications including automotive, AR/VR, client computing, datacenter, and the intelligent edge. To set up a meeting, please contact sifive@racepointglobal.com.   



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At the 2022 RISC-V Summit, SiFive highlighted collaborations with some of the world’s biggest companies in our 10+ talks on stage and with our demos. SiFive also gave an exclusive first look at an upcoming product, and three of our employees won awards.

One highlight was the keynote from SiFive’s CEO, Patrick Little: [“RISC-V Spotlight: RISC-V Everyone Wins”](https://www.youtube.com/watch?v=VxG87XLKPvM). Patrick highlighted how the momentum and excitement for RISC-V is growing and how today it is in billions of cores on the market and is being designed into a huge range of applications. Patrick covered the early vision for RISC-V and emphasized the importance of collaborating to build a strong community and ecosystem for RISC-V.

As part of our efforts to build out the RISC-V ecosystem, SiFive has partnered with Intel to develop the HiFive Pro P550 Development System (previously code-named Horse Creek). During his keynote, Patrick was joined on stage by Intel Foundry Services’ Bob Brennan to share a first look at this high performance platform that features a quad-core SiFive Performance™ P550 processor and is implemented in the Intel 4 technology platform. The board will enable a new generation of RISC-V software, continuing the tradition of SiFive HiFive boards that have helped drive the growth of the RISC-V ecosystem. The board will be commercially available in the summer of 2023. 

SiFive ecosystem partners and customers, including Ashling, AWS, Canonical Ubuntu, Codeplay, Google, Imperas, Intel, Lauterbach, Microchip, Qualcomm, Rice University, Solid Sands, Synopsys, and Tenstorrent, were featured throughout the event and in a panel session entitled [“It takes a village… to build an ecosystem,”](https://www.youtube.com/watch?v=kwQni8zo5w0) which reviewed the strong state of the RISC-V ecosystem as well as the next steps that key contributors are leading.

SiFive’s additional presentations throughout the event focused on our collaborations and partnerships to bring our high-performance RISC-V portfolio to automotive, [aerospace](https://www.youtube.com/watch?v=GrTjDgSpSmY), and beyond. For example, through our partnership with Microchip, SiFive is a part of NASA’s next generation High-Performance Spaceflight Computing (HPSC) processor, which delivers a 100x increase in computational capability to help propel next-generation planetary and surface missions. Jack Kang, SVP, Biz Dev, CX, Corp Marketing at SiFive, [summed up](https://www.youtube.com/watch?v=Fa3FJhhmrHc) why so many companies are choosing RISC-V and SiFive: “RISC-V products are just better. Better power, better performance, and more.” 

Jack also took some time to chat with RISC-V International’s CEO Calista Redmond about our momentum to-date and what’s ahead. 

SiFive continues to invest strongly in the RISC-V community, with many of our employees actively participating in RISC-V International’s technical committees. In recognition of these efforts, three of SiFive’s employees won awards from RISC-V International. Yunsup Lee, SiFive’s Co-Founder & Chief Technology Officer, received a Technical Contributor Award for his work as Chair of the Technical Steering Committee (TSC). Craig Topper, Principal Compiler Engineer, and Kito Cheng, Compiler Engineer, received Software Contributor Awards for their hard work on RISC-V technical committees. Check out the full list of winners [here](https://riscv.org/announcements/2022/12/risc-v-honors-outstanding-technical-and-community-contributions-for-2022/).

You can read more about SiFive’s latest activities and momentum in 2022 [here.](https://www.sifive.com/press/sifive-delivers-record-growth-in-2022-with-fast-growing) To watch SiFive’s presentations at the RISC-V Summit, visit [here](https://www.youtube.com/@RISCVInternational/videos).



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SiFive Makes a Splash at the RISC-V Summit with 10+ Talks, Demos, and a Surprise Product Reveal

SiFive has seen tremendous growth over the past few years with strong year-over-year revenue growth and is in the top 10% of the Inc. 5000 list of private companies. With more than 550 employees around the world, we’re continuing to grow our team and expand our footprint across different regions to meet the strong customer demand for SiFive’s innovative RISC-V IP.

India is one region in particular where we’re focused on building out our team. This month SiFive opened a new design center in Bangalore, India. We have around 90 employees working there currently, and the space has room for around 150 employees as we continue to grow. The Bangalore team is focused on leading edge CPU and platform design, verification, physical implementation and software.  

![SiFive Bangalore team](https://images.prismic.io/sifive/083356ef-c691-4f12-8727-da5b02eb3983_SiFive-BLR-Office.jpg?auto=compress,format) Our Bangalore Team

SiFive also recently opened a new office in Hyderabad, India where the team is working on CPU IP design, verification and software tooling. Additionally, SiFive has a team in Ahmedabad, India working on cutting-edge network-on-chip (NoC) technology.

These recent efforts to expand our presence underscore the massive potential we see in India for silicon innovation. While there is strong momentum for RISC-V all over the globe, the excitement for RISC-V in India is almost unparalleled. This push for RISC-V extends throughout academia, industry, and even the government. The Indian government announced the ambitious [Digital India RISC-V (DIR-V) program](https://pib.gov.in/PressReleasePage.aspx?PRID=1820621) earlier this year to leverage RISC-V to catalyze semiconductor innovation in the country.

We’re hiring in our offices around the world, so we encourage you to apply to work with the best and the brightest as we take high-performance products to the next level.  You’ll get to work alongside the founders of RISC-V as we transform the future of compute and prove that RISC-V has no limits. Learn learn more about our open positions and apply [here](https://www.sifive.com/careers).


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SiFive Expands Presence in India to Keep Up with the Company’s Ultra-fast Growth

 In the fast moving Semiconductor Industry, predictions and papers become obsolete fast and so it’s worth recognizing when a paper has a significant impact on our industry that also has a bit of a timeless nature. The paper, **A systematic methodology to compute the architectural vulnerability factors for a high-performance microprocessor** (you can read it [here](https://ieeexplore.ieee.org/abstract/document/1253181) was recognized during the award ceremony at MICRO 22 in Chicago October 4th, and we’re proud to share that our very own VP of Architecture, Shubu Mukherjee, (who was at Intel at the time it was written) was there to accept the award on behalf of his fellow authors, Christopher  Weaver, Joel Emer, Steve Reinhardt and Todd Austin.

![Shubu](https://images.prismic.io/sifive/9a5ad323-407b-4eb8-afb9-5cbf0d6b8b47_Slide1.jpeg?auto=compress,format)

The methodology highlighted in the paper has been the foundation for RAS work done by a number of companies over the past 20 years and continues to be used in the FuSa work happening at SiFive and many other companies.
The citation for the award reads:
This paper targets the problem of assessing the cost and reliability trade-offs in a microprocessor.  The authors introduce the concept of Architectural Vulnerability Factor (AVF) which estimates the probability that a fault in a particular hardware structure will result in a user-visible error.  This concept was introduced at a time when continued technology scaling caused the architecture community to stumble upon the "Reliability Wall" and there was significant industry concern about the reliability of computing at scale due to transient faults.  Both industry and academia invested significant efforts to ensure reliable program execution in the presence of such faults. The AVF analysis methodology allowed processor architects to reason about the impact of transient faults early enough in the design cycle to be able to prioritize protection decisions. The paper has had a significant impact on the technical community. At the time of this writing, it has had over 1200 citations on Google Scholar and has received over 40 citations each year for the past 15 years. AVF analysis is now an industry best practice.
 
At SiFive,  Shubu has been instrumental in driving new technologies and his past FuSa work is helping shape our new Automotive Portfolio.
 
Congratulations to Shubu and the other authors.  SiFive continues to attract some of the industry’s best technologists, and we’re proud to showcase their work.  To see our latest opportunities, please see our [careers page](https://www.sifive.com/careers).

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SiFive’s Shubu Mukherjee Recognized Along with Fellow Authors with SIGGMICRO’s Test of Time Award

At the AI Hardware Summit in Santa Clara,  September 14th,  Krste Asanovic, SiFive Co-Founder and Chief Architect, took to the stage with Cliff Young, Google TPU Architect and MLPerf Co-Founder, to reveal how the latest SiFive Intelligence™ X280 processor with the new SiFive Vector Coprocessor Interface Extension (VCIX) is being used as the AI Compute Host to provide flexible programming combined with the Google MXU (systolic matrix multiplier) accelerator in the datacenter. They also talked about why this type of architecture is becoming popular for AI/ML workloads, and how, with this configuration, SiFive provides essential compute capabilities so Google can focus on deep learning SOC development. A video of the talk is expected to be available in early October. 

![Krste and Cliff](https://images.prismic.io/sifive/f25531a2-a8c2-433a-8975-ebee195ec6cc_google+talk.jpg?auto=compress,format)

**SIFive Intelligence X280** 
![SiFive X280](https://images.prismic.io/sifive/772f6782-9114-4d36-aeed-a0592362d008_Slide1.jpeg?auto=compress,format)
The SiFive Intelligence X280 is a multi-core capable RISC-V processor with vector extension, optimized for AI/ML applications in the datacenter. 
As Krste explained, the X280 has a 64-bit applications processor plus an expanded vector unit supporting the RISC-V Vector 1.0 ratified standard, providing a full featured processor designed for vector compute executing standard software. The X280 has 32,  512-bit registers and allows you to gang multiple vector registers together to make a longer vector (up to 8 in a row). This allows operations at up to 4096-bits, which helps reduce power and increase optimizations on cohorts where you have longer vectors. 

SiFive also offers the SiFive Intelligence extensions, which add custom instructions to optimize AI/ML workloads. The X280 runs a full RISC-V software stack as well as a hypervisor. It is a highly efficient, Linux-capable processor  with full applications processor support, supporting up to 48-bit virtual memory space, and private L1 and L2 caches. The vector streams from the L2 cache and all cores share the L3 cache. With the latest X280, SiFive offers improved software compilers for higher performance, a very capable applications core, with a very wide vector unit,  and support for large cache coherent multi-processor configurations.
![Comparison chart](https://images.prismic.io/sifive/a31852c8-13a5-41e0-8c69-739ee9b55f4d_Slide2.jpeg?auto=compress,format)
The chart above shows an example of AI acceleration with Mobilenet, delivering a huge 24x speed up with the X280 standard Vector instructions (vs. the scalar ISA), and then another ~6x acceleration with the SiFive Intelligence extensions. Krste also pointed out that the X280 can run by itself, performing inference tasks at the edge, where it can also act as an apps processor and inference engine for smaller workloads.  

**Game-changing VCIX**
![VCIX overview](https://images.prismic.io/sifive/a79f175a-79c9-4920-8013-77859e16a145_Slide4.jpeg?auto=compress,format)

After the introduction of the X280, SiFive started seeing a lot of customers using it as a companion core. As shown above, the X280 has many features to accelerate AI and ML, but it’s not a massive AI accelerator that is traditionally built for datacenters. Customers building these massive accelerators found they had a bunch of complex compute that needed to be done that their accelerator “really didn’t know how to do.” For example, many found that you need a full featured software stack to run the code that’s not in the kernel that sits on the accelerator. To solve this challenge, customers realized they could put the X280 core next to their large accelerator where it could provide maintenance code and operations code, run kernels that the big accelerator couldn’t do, or provide other valuable extra functions. And the X280 core allowed them to run very fast.   

With this real-world customer feedback, SiFive set out to develop something more ideally suited to this use case. Working with customers like Google, SiFive came up with the Vector Coprocessor Interface eXtension (VCIX), which allows you to plug an accelerator directly into the vector register file of the X280 and communicate on the very fast order of 10 cycles in-and-out. This is helpful for adding complex instructions like color conversions, for example. Overall, VCIX gives you increased performance and much greater data bandwidth, because you go directly into the vector register file, coupled with much lower latency and simplified software. 

VCIX connects to the 32, 512-bit registers in the X280 directly and also to the scalar instruction stream, creating a high bandwidth, low latency path directly coupled to the instruction stream of the X280 scalar processor. Designers can not only offload some functions to the software accelerator, but also have the flexibility of having the X280 handle some functions itself. The benefit, as Krste highlighted, is that you can bring your own coprocessor into the RISC-V ecosystem and get a complete software stack and programming environment. You can run full Linux plus a hypervisor with full virtual memory and cache coherent support.  

**An elegant division of labor with the Google TPU**
![Google TPU](https://images.prismic.io/sifive/a98c5e95-3476-4cd3-9bd8-b093a30ee8c9_Slide6.jpeg?auto=compress,format)

As Cliff explained, Google has significant innovation and investment in their TPU technology, which they essentially built from “scratch” nine years ago. Recognizing the shift toward a more IP-oriented universe, Google wanted to focus on innovation in the most critical areas and where their real strengths and differentiation are, such as in the network and systolic array areas of the TPU. 

As Cliff explained, scalar and vector solutions are best left to experts in those technologies, so rather than Google reinventing the wheel, they looked for options and SiFive brought a solution. What if you could reuse a general purpose processor with a general purpose stack? Evaluating a general purpose core vs. accelerator, they looked at how, for example, you could make it easier to program. Looking at VCIX, Google saw an opportunity for flexibility and if you wanted to run Python, for example, right next to the core, you could do so with very low latency. 

He further highlighted the promise of VCIX, which is “to get accelerators and general purpose processors right close together.” Rather than hundreds of cycles for on-chip cache or thousands of cycle access through PCIe, you get the benefit of tens of cycles through vector register access.  
![SiFive and Google](https://images.prismic.io/sifive/d9248baa-8ca0-42bf-a67d-64b1432cecc8_Slide7.jpeg?auto=compress,format)
Cliff explained what he defined as an important “division of labor,” defining the technical and business operations between a companion core and MXU. A vector unit provides a wide path to memory, and much of the virtual labor is done in VCIX. There is no need to open decoders when you add the Interface overlay with its minimal instructions. And VCIX allows the sending and receiving of instructions with greater flexibility.  This flexibility and control allows a clean and efficient division of labor between the Google matrix multiplication unit (MXU) and the X280. 
As Cliff concluded, with SiFive VCIX-based general purpose cores “hybridized” with Google MXUs, you can build a machine that lets you “have your cake and eat it too,“ taking full advantage of all the performance of the MXU and the programmability of a general CPU as well as the vector performance of the X280 processor. For Google and other customers, this delivers much more programmable, and flexible future machines. 

To learn more about how X280 can **accelerate your accelerator**, contact sales@sifive.com. 


google talk.jpg

SiFive Intelligence X280 as AI Compute Host: Google Datacenter Case Study

**The Next SiFive Revolution**

As SiFive announces its long-term plans to meet the rapidly changing needs of the automotive markets, this blog explores the many advantages the [SiFive Automotive™ portfolio](/cores/automotive) brings across a wide range of current and future applications, including; electrification, cockpit, ADAS, safety, and others. Our power efficient, flexible and high-performance cores are ideally suited for the most critical applications, and are of course, supported by the global RISC-V ecosystem.

**Why SiFive?**

Founded by the same engineers who invented the RISC-V ISA, SiFive is uniquely positioned to extend and broaden the reach of RISC-V based processors in new and growing markets. The rate of SiFive innovation and product development in the last few years has been astounding. SiFive has grown rapidly, and today offers not only the most comprehensive portfolio of RISC-V IP, but is rapidly approaching performance at the high-end that matches or exceeds any CPU IP vendor. SiFive’s growing portfolio of IP, ranging from small 32-bit real time CPUs all the way up to high-performance 64-bit application processors, singles out SiFive as the only RISC-V IP supplier that can cater to the entire spectrum of automotive compute requirements as a one stop shop. From our CEO, who grew Qualcomm’s automotive division, to our many automotive SOC experts, we are a team that uniquely understands the needs of today’s automotive manufacturer.

**A Portfolio Approach**

SiFive’s roadmap delivers a portfolio of products that meets the requirements of the vast majority of automotive CPU applications, including MCUs, MPUs and, soon, SoCs. We often read about macro trends in automotive electronic architecture design, including centralization of computing, increased compute at the sensing edge, increased SW complexity due to mixed criticality support, and a shift from domain to zonal controllers, to list but a few of today’s trends. The implications are a need for newer, more capable ECUs, and a higher degree of mixed criticality functional integration into fewer devices, at the price of increased software complexity. Despite the evolution in electronic architectures, the variety of automotive semiconductor products continues to remain broad, from small MCUs all the way to complex SoCs; however, there are significant commonalities across the many use cases including functional safety and security. Virtually every electronic device in a vehicle must comply with ISO26262, ISO21434, and additional local standards as applicable, such as UNECE WP.29 r155. SiFive Automotive products provide tailored levels of integrity, with area optimized products for both ASIL B and ASIL D, while in-field configurable integrity levels can be enabled through the available split-lock variants.

**Introducing the SiFive Automotive Family of Products**

SiFive has launched its new product portfolio and the first three SiFive Automotive product series, each with area and performance optimized variants for their intended use. SiFive is the only RISC-V IP supplier to offer multiple processor series that optimally meet automotive designers’ exact compute, integrity, and security requirements across a broad range of computing applications, from MCUs to complex SoCs.  All of the product variants offer best-in-class levels of functional safety and security capabilities, with a high degree of configurability to different integrity levels. The E6-A is the first commercially available offering. The E6-A is a 32-bit real-time core, with broad availability later in 2022. By the second half of 2023, two more product series will be added to the portfolio, the X280-A and S7-A. The X280-A is a vector capable processor ideally suited for edge sensing in ADAS, sensor fusion applications, and any ML/AI accelerated functionality in the vehicle. The S7-A is an optimized 64-bit CPU tailored for safety islands as often used in ADAS, gateways, and domain controllers. A standout feature of S7-A is native 64-bit support, meaning that the safety island can now access the same memory space as the application CPUs.

Later in 2023, a new high-end processor, configurable to up to 16-cores, will be added to the portfolio. Customers should expect best-in-class performance and ASIL support and a tailored automotive alternative for high performance CPU IP.  And much more is on the way in the coming months as the roadmap expands to meet market needs, and our SW, tools and OS partners add new levels of support.

All of the above could not have been possible without SiFive strategically adding top talent from the industry, both in CPU design and the automotive market, including, our CEO who managed the growth of Qualcomm’s automotive business, and a renowned safety expert and co-founder of Yogitech, among others. The automotive team benefits from investments in processor design that are foundational to the underlying technology, while also leveraging expertise in automotive R&D, functional safety, and security. Our team is ready to answer your automotive questions. 

**Ecosystem and Next Steps**

The automotive semiconductor market is dependent on advances from a broad range of SW, tool, and OS vendors, and their support for SiFive the RISC-V ecosystem is growing at a phenomenal pace. The ecosystem supporting RISC-V today is fast growing and reaching maturity, with many announcements in the pipeline.

SiFive is collaborating with a wide range of [automotive technology companies](/cores/automotive#partners) to create a robust and vibrant RISC-V community.

SiFive’s first automotive products are arriving in the market at a time of rapid growth and change and the company brings a modern architecture, supported by the broad global RISC-V ecosystem, with unique solutions for some of automotive’s most critical technologies. 

If you’d like to hear more, give us a call or visit our [Automotive](/cores/automotive) page for more information.




In June 2022, SiFive released an enhanced version of the market-leading SiFive® Intelligence™ X280 processor to take a further leap in performance for AI inference, image processing, and datacenter applications.

Alongside exciting new features including multi-cluster and SiFive WorldGuard trusted protection, the X280 now includes VCIX, SiFive’s new vector coprocessor accelerator interface, improving power and area efficiency, simplifying designs, and shortening design times.

The X280 shares equal success as a standalone processor as it does as a companion processor (to, for example, a custom accelerator) due to the broad range of applications that can benefit from its unique feature set that offers superior performance from the combined scalar and vector compute capabilities.

Modern workloads and applications often require the highest performance, but within a constrained power environment. Due to the excellent vector compute capabilities offered by the standard RISC-V Vector ISA and SiFive Intelligence Extensions, designers have been able to consolidate various specialized DSP accelerator functionality into a single X280 processor design thus maintaining a simpler system design and ease of programming, while still achieving the required performance and efficiency goals.

In certain situations, such as workloads requiring highly intensive computation on vector data, designers still require the use of heavily optimized custom accelerators to offload these tasks from the main processor. The challenge with this approach is that the custom accelerator needs to be designed to co-exist with the main processor, with some subtle design consequences in that the accelerator:
- will require access to, and use of an SoC system bus (for data transfers), potentially causing bus latency issues
- may need its own cache system or tightly coupled memory, for maintaining peak performance, with an associated increase in chip area
often requires a separate proprietary toolchain for programming, along with the separation of algorithm tasks increasing design time and reducing ease of programmability
![VCIX](https://images.prismic.io/sifive/40a18ebf-cbaa-4e50-9c7a-cc2f9ef7458a_Slide1.jpeg?auto=compress,format)
The SiFive Vector Coprocessor Interface Extension (VCIX) is a vector instruction-mapped interface, enabling a direct connection between the X280 vector ALU to a custom accelerator, allowing custom vector instructions to be executed on the accelerator from the vector pipeline. The custom vector instructions are executed from the standard SiFive software flow, utilizing the vector pipeline, with access to the full vector register set.



This powerful capability has many benefits to both hardware designers and software programmers as it can share some of the key processor resources, such as the vector register bank, main processor caching architecture, and memory system:
- A reduction and streamlining in both the design and test effort that is required when developing a customer accelerator due to the simpler design considerations
- Higher system performance, due to the significant reduction of computation cycles needed for specialized workloads
- Improved power and area efficiency by using the custom accelerator only when required, without the additional system area overhead 
- Easier to program, as custom vector instructions are executed from the standard SiFive software flow

Want to learn more? Contact us or access the other materials on our SiFive vectors page.
 


sifive-vectors-card-big-logo.png

Introducing the Latest SiFive® Intelligence™ X280 Processor Innovation - the Vector Coprocessor Interface Extension (VCIX)


With the 2021 launch of the SiFive® Intelligence™ X280, SiFive was the first company to release a RISC-V Vector 1.0 product, and it took the market by storm. The X280 has quickly achieved market-leading success, with design wins across a number of high performance applications including AI inference, Image Processing, and Datacenter applications. Customers include a U.S. government agency working on next generation aerospace/defense standards, a tier #1 global mobile image processor supplier, and a tier #1 global hyperscaler for AI, and the list grows daily.. 

With the latest release of the SiFive Intelligence X280, SiFive has several exciting new first-to-market features including:

- Vector Coprocessor interface: This innovative vector coprocessor accelerator interface enables better power and area efficiency with easier-to-program solutions. 

- Multi-cluster: The X280 now offers a coherent core complex of up to 4 clusters of 4-cores that scales to best-in-class multi-TOP performance.
WorldGuard: A hardware system security solution bringing trusted execution to protect AI/ML algorithms.

- Reference Platform: Introduction of the first X280 Reference Platform for reducing time-to-market for developers and the fast-growing RISC-V ecosystem

The Vector Coprocessor Interface extension (VCIX) solves two of the biggest challenges facing designers; system complexity and ease of programming:

- To reduce overall system complexity, VCIX enables designers to directly connect their own custom accelerator to the X280, utilizing and sharing the X280 processor system resources. This results in a far simpler, and more efficient, accelerator system design. 

- In order to solve the challenge of ease of programmability, VCIX enables a single toolchain to be used for programming both the X280 and the custom accelerator. As VCIX is a vector instruction-mapped interface, it gives a direct connection from the X280 vector ALU to a custom accelerator. This enables custom vector instructions to be executed on the accelerator directly from the vector pipeline as part of the standard SiFive software flow. 

Being able to share many of the fundamental processor resources, such as the vector register bank, main processor caching architecture, and memory system, brings many benefits:

- Improved the time to market due to the reduced design time for custom accelerators 

- Higher system performance for specialized workloads*
Better area optimization resulting in power and area efficiency gains

*Multi-core, Multi-cluster*

The X280 is the first RISC-V Vector processor that can be configured up to 16 cores in a coherent multi-cluster Core Complex, consisting of up to 4 cores in a coherent multi-core cluster and up to 4 coherent clusters. With these multi-core, multi-cluster configurations, SiFive also delivers the complete, configured fabric infrastructure alongside the processor to enable full coherency.

*WorldGuard*

WorldGuard, now available for the first time in a high core count system, provides a simple, yet powerful, way of enforcing hardware security by isolating code and data as well as preventing access to select peripherals. It allows different assets to be isolated into separate security worlds. This additional layer of protection can prevent rogue or bogus software running at any RISC-V privilege level, including Machine Mode, from accessing confidential data or tampering with the software. This allows sensitive firmware, like a home-grown AI/ML stack, to be isolated from more open software and also from intrusion by debug and trace capabilities.

*X280 Reference Platform*

This new resource enables easy and fast access to everything needed by SiFive customers and ecosystem partners to develop hardware and software that leverages all of the new capabilities in this latest release of the X280. The X280 Reference Platform (available in Q3) will comprise of a hardware target based on the Xilinx VCU118 FPGA board, a functional model target based on QEMU (and matching the FPGA hardware target), and a Linux-based BSP, as well as the full architectural specification of the platform. The X280 Reference Platform is intended to be easy to use by developers and the software ecosystem alike, making it easier than ever to get your application up and running with a real RISC-V vector-enabled platform. 

With the latest version of the X280, designers will continue to benefit from the success trajectory of SiFive vector processor designs, taking RISC-V and RISC-V Vectors further into new and exciting marketing applications.

For more information about SiFive vector solutions, visit sifive.com/technology/vectors. For more information about the SiFive Intelligence X280 visit sifive.com/cores/intelligence-x280


SiFive's RISC-V Leadership Strengthens with New Vector Solutions

If you haven’t seen it, SiFive is ranked in the top 10 percent of Inc.’s annual list [Here](https://www.inc.com/profile/sifive) of the fast-growing private companies in America which includes a wide range of industries. This ranking is a direct reflection of our impressive revenue growth the past three years and our momentum, forward trajectory, and leadership in the processor IP market. By the numbers, SiFive is ranked No. 413 overall, and we are excited to rank an impressive second (No. 2) in computer hardware. 

In addition to this prestigious ranking, SiFive continues to see validation from Wall Street. The company was named the first RISC-V unicorn following our Series F round of $175M and a valuation of $2.5B. We have design wins with more than 100 customers including several of the world’s largest hyperscale companies and 8 of the top 10 semiconductor companies, in applications ranging from automotive, AR/VR, client computing, data center, and intelligent edge.

“The accomplishment of building one of the fastest-growing companies in the U.S., in light of recent economic roadblocks, cannot be overstated,” says Scott Omelianuk, editor-in-chief of Inc. “Inc. is thrilled to honor the companies that have established themselves through innovation, hard work, and rising to the challenges of today.” 

According to Inc., companies on the 2022 Inc. 5000 are ranked according to percentage revenue growth from 2018 to 2021. To qualify, companies must have been founded and generating revenue by March 31, 2018. They must be U.S.-based, privately held, for-profit, and independent—not subsidiaries or divisions of other companies—as of December 31, 2021. The minimum revenue required for 2018 is $100,000; the minimum for 2021 is $2 million. 

SiFive is charting the RISC-V path for the future of compute. This win is a testament to our growth and market leadership. More to come! 


SiFive Ranks in Top 10 Percent of Inc.’s Fastest Growing Private Companies in America List 

Cambridge, with a long history of innovation and invention and a thriving tech ecosystem, is an obvious choice as a location for SiFive to continue its global expansion. We’re all about attracting the best talent, anywhere, and part of our mission and values is to also give back to, and be an active participant in the communities where we do business. As we expand in Cambridge we found a great partner with Cambridge United Football Club and this week announced our sponsorship as part of a week-long celebration. See the promotional video [Here](https://youtu.be/oh9_PX4jvC8)

![Winning combination](https://images.prismic.io/sifive/b8730eb3-e926-45e6-ae7a-f6bd5fff1f02_Large-+CU+logo+.webp?auto=compress,format)

Members of our executive and local team attended the first game of the season (they won) at Abbey Stadium which is an intimate location, steeped in history, that serves the local community.  Cambridge United Football Club competes in EFL League One, the third tier of the English professional football (soccer for you Americans) system. The club has seen meaningful success in recent years, having been promoted from EFL League Two in 2021, then exceeding all expectations in not only staying up in League One, but also upsetting Premier League Giants Newcastle United (the most expensive team in the world) in the FA cup in 2022. 

![SiFive meets the team](https://images.prismic.io/sifive/adcc6ab2-f07c-4417-bb74-a7d62e8b7ab9_52252074090_173e795eca_o.jpg?auto=compress,format)

Cambridge United's success on the pitch, with fewer resources than their competitors, mirrors the SiFive success story. The team maintains a [Community Trust](https://www.youtube.com/watch?v=vYks3_e8u1g) which is highly active in a variety of ways locally, including support of mental health education with player involvement, adaptive sports activities to drive empowerment with people with disabilities, youth volunteer training camps, senior lunches and activities, and “Over-50” community football leagues. They believe sport is a non-traditional education method and we are proud to support their efforts and look forward to a winning season. 
 
**A little education with the fun**
 
To start the week, Krste Asanovic, the founder of RISC-V and one of the founders of SiFive (and also a Cambridge Alum) gave a RISC-V overview at a crowded event at Abbey stadium where members of the Cambridge tech community dropped in to hear about technical innovations, job opportunities and other news from SiFive.
 
 ![Krste Asanovic](https://images.prismic.io/sifive/2dea7a72-16f6-4df8-8a73-926d2b3c2a5b_Krste+Speech.jpg?auto=compress,format)
 
In his talk, Krste explained how RISC-V started, how it has evolved to be a global phenomena, and how he sees it taking shape in the future. 

We recently announced our new office which will serve as a hub for R&D, engineering and marketing, and we’re actively hiring, taking advantage of the considerable tech talent in the greater Cambridge area. If you’re looking to work with an industry leader, innovator, and to change the way the semiconductor industry works, check out our open positions on our [careers page](https://www.sifive.com/careers).  



**SiFive is the market leader in RISC-V Vector processors with the flagship SiFive vector processor, the [SiFive Intelligence X280](https://www.sifive.com/cores/intelligence-x280), leading the charge as a clear favorite with customers, with solutions being designed into a broad range of applications ranging from computer vision, mobile ISP, Edge AI, to datacenter AI.**

The X280 is gaining significant market traction due to a number of factors, including:
<ul>
<li>Design Flexibility
<li>Power and performance efficiency
<li>Portability
<li>Ease of programmability
<li>Use of standard software
</ul>

This powerful combination gives customers the ability to develop a perfectly balanced solution to tackle the demands of modern workloads and ensure market success.

The X280 processor is a 64-bit RISC-V vector processor offering best-in-class high performance and efficiency targeting AI and ML workloads. The highly configurable multi-core, multi-cluster capable design has been optimized for the broadest range of applications requiring high-throughput, single-thread performance while under the tightest power and area constraints.

![SiFive Intelligence X280](https://images.prismic.io/sifive/34f4ec15-c03a-47cc-a3b4-da5cce0b5df3_SiFiveIntelligenceX280.png?auto=compress,format)

With a specific emphasis on AI/ML compute, the X280 features the powerful combination of the RISC-V Vector (512-bit vector length) and the SiFive Intelligence Extensions, tightly integrated with an 8-stage dual-issue in-order scalar pipeline.

Key Features include:
<ul>
<li>64-bit RISC-V ISA
<li>SiFive Intelligence Extensions, which are custom instructions that accelerate AI/ML performance critical operations
<li>Multi-core, multi-cluster processor configuration options, with up to 8 cores
<li>Loosely coupled vector computation pipeline and ALU implementing RISC-V Vector extension version 1.0
<li>Support for multiple data types
<li>512-bit vector register length 
<li>256-bit Vector ALU and Load/Store architecture
<li>Decoupled scalar and vector pipelines for optimum parallel execution of scalar and vector computation
<li>Virtual memory support, with up to 48-bit addressing
<li>High performance, flexible connectivity to SoC peripherals
</ul>

See the [X280 Product datasheet](https://www.sifive.com/document-file/x280-datasheet) for full details on X280 specifics.

SiFive has a strong customer base for its vector-based product line. We have worked with customers to further define a roadmap that adds some powerful new features and enhancements, higher performance vector-based processors, and wider vector registers. If you want to find out more about licensing the X280 then please [contact us](https://www.sifive.com/contact-sales) for more details.

Want to learn more about SiFive vectors, you can access the other materials on our [SiFive vectors page](https://www.sifive.com/technology/vectors).

If you’re excited about RISC-V Vectors and want to be part of the growing teams across the globe building the next generation of vector products from SiFive then get in touch. We have some great career opportunities in the USA, Taiwan, France, and the UK. Check out the [SiFive Careers page](https://www.sifive.com/careers) for all of the latest updates.

Stay current with the latest SiFive updates via [Facebook](https://www.facebook.com/SiFive/), [Instagram](https://www.instagram.com/sifive_inc/), [LinkedIn](https://www.linkedin.com/company/sifive), [Twitter](https://twitter.com/SiFive), and [YouTube](https://www.youtube.com/c/SiFiveInc).

Introduction To The SiFive Intelligence X280

**After describing the current 2022 broad SiFive Performance, Intelligence, and Essential Processor Product portfolio, this webinar introduction to the SiFive vector processors begins by identifying some of the challenges that exist for system designers and subsequent evolving application trends.**

[Click here to watch the full webinar:](https://youtu.be/IxH3iqNkbQY)
[![SemiIsraelWebinar](https://images.prismic.io/sifive/2985c8a9-ca93-4f08-9027-15bfa8e57033_SemiIsraelSiFiveVectorProcessors.png?auto=compress,format)](https://youtu.be/IxH3iqNkbQY)

The semiconductor market is constantly looking to simplify design cycles while striving for more portability and re-use, broader extensibility, and increasing design scalability. In parallel, modern neural networks are rapidly and continuously evolving requiring more powerful hardware and scalable software solutions. These trends align well with the desire for more open and community-supported solutions to enable collaboration on a large scale.

The webinar also describes the benefits of RISC-V Vectors and details why they provide more optimal solutions than those based on packed-SIMD solutions and wraps up with details on the software and hardware ecosystem available supporting the SiFive vector solutions.

The introduction of the SiFive® Performance™ P270 and SiFive Intelligence™ X280 processors brings to market the first available licensable IP to support the RISC-V Vector ISA 1.0 (ratified in late 2021). 

The X280 processor is a 64-bit RISC-V Linux-capable, RISC-V Vector processor, offering best-in-class high performance and efficiency targeting AI and ML workloads. It features the powerful combination of a RISC-V Vector ISA with a 512-bit vector register length, along with the SiFive Intelligence Extensions, tightly integrated with an 8-stage dual-issue in-order scalar pipeline and decoupled vector ALU pipeline. The SiFive Intelligence Extensions operations augment and extend the standard RISC-V Vector ISA and are specifically tuned for the acceleration of neural network computation.

![SiFive Intelligence X280](https://images.prismic.io/sifive/34f4ec15-c03a-47cc-a3b4-da5cce0b5df3_SiFiveIntelligenceX280.png?auto=compress,format)

The P270 processor is a 64-bit RISC-V Linux capable, RISC-V Vector enabled, application processor, offering best-in-class performance and efficiency for the broadest range of control and vector combined computation workloads. The P270 features the powerful combination of a RISC-V Vector ISA with a 256-bit vector length, integrated with an 8-stage, dual-issue, in-order scalar pipeline and decoupled vector ALU pipeline.

![SiFive Performance P270](https://images.prismic.io/sifive/da8ba38c-f2e0-42dc-b467-fb1915b1ef08_SiFivePerformanceP270.png?auto=compress,format)

Following the 2021 release of the P270 and X280 processors, SiFive has worked closely with customers to further define and build a vector roadmap that adds some powerful new features and enhancements, higher performance vector-based processors, along with wider vector registers. To find out more about licensing the P270 or X280, please [contact us](https://www.sifive.com/contact-sales) for more details; you can also [access the other materials on our SiFive vectors page](https://www.sifive.com/technology/vectors)

[Click here to watch the full webinar](https://youtu.be/IxH3iqNkbQY)

Stay current with the latest SiFive updates via [Facebook](https://www.facebook.com/SiFive/), [Instagram](https://www.instagram.com/sifive_inc/), [LinkedIn](https://www.linkedin.com/company/sifive), [Twitter](https://twitter.com/SiFive), and [YouTube](https://www.youtube.com/c/SiFiveInc).

**A great way to get to know more about popular SiFive vector processors, which are compatible with the RISC-V Vector (RVV) version 1.0 specification**

1.) The RISC-V Vector (RVV) ISA was ratified at version 1.0 by RISC-V International in December of 2021 but it’s fair to say it’s been a big part of the SiFive and RISC-V journey and was being contemplated by the original inventors of RISC-V, namely Krste Asanovic, Andrew Waterman and Yunsup Lee, right from the beginning of the inception of RISC-V at UC Berkeley back in 2015. In fact, Krste was actually working with vectors and developing vector processors as part of his Ph.D back in the late 90s . In one of his talks about the [history of RISC-V Vectors](https://youtu.be/NlZr19lFxRg?t=12), Krste explains that there is a running joke that the V in RISC-V secretly stands for vectors. 

2.) One of the key defining features of the RISC-V Vector ISA is that it is vector length agnostic. This means that software code that has been written for any RISC-V vector compliant processor will work on any other RISC-V vector processor. From a software reuse perspective, this has a huge reward with many benefits; imagine the case where a first-generation end-product was designed around a 256-bit length vector register processor, for example, the [SiFive® Performance™ P270](https://www.sifive.com/cores/performance-p200), due to it having the perfect balance of power, performance, and area for that first design. As the product gained market success, new requirements evolved for the second generation product resulting in improved performance from the longer vector register length processor, for example, the [SiFive Intelligence™ X280](https://www.sifive.com/cores/intelligence-x280) with its 512-bit length vector registers. In this situation not only will the software code execute directly on the X280, but the code performance will improve immensely, without having to change even one line of code. This results in much-reduced design and development time, therefore a much faster time to market for the second generation product, with a very appealing faster time to revenue.

3.) The RISC-V Vector ISA is a very clean and optimized set of instructions, with the base ISA numbering around just 300 instructions, far smaller than a typical packed-SIMD alternative. Crucially these powerful instructions can each do a lot of work. The key benefits this brings are two-fold in that, 
<ul>
<li>as instruction codings take up area in a chip, this area is decreased 
<li>compilers generate very dense code, reducing the area needed for code storage 
</ul>

By minimizing this area overhead this ultimately leads to better power efficiency with a smaller memory footprint. This [tutorial video](https://www.youtube.com/watch?v=S4fxBZD79gc), while recorded prior to the final ratification of the specification, gives a great amount of detail on the overall vector ISA and explains the design philosophy and why RISC-V Vectors is considered “The best vector ISA ever!”

4.) RVV evolved to where it is today as a powerful and more efficient (in code size, performance, and area) alternative to the inefficient use of packed-SIMD and GPUs for the processing of large datasets. From its inception one of the biggest drivers was that the ISA was efficient and scalable to all reasonable design points. This meant being equally as applicable to both low-cost designs as to the highest performance applications. For this reason the ISA needed to be able to support in-order, decoupled, or out-of-order microarchitectures, along with integer, fixed-point and/or floating point data types. In a [RISC-V workshop talk in 2015](https://youtu.be/NlZr19lFxRg), Krste further explains additional design considerations for the RISC-V Vector extension as:

<ul>
<li>being a great compiler target
<li>supporting both implicit auto-vectorization and explicit programming models
<li>able to work with virtualization layers
<li>fit into standard fixed 32-bit encoding space
<li>be a base for future vector extensions
</ul>

Importantly, the design considerations were also to not replicate or be like a GPU or packed-SIMD implementation. Krste also explains some of the problems with packed-SIMD and GPU implementations, explaining how they can lead to multiple new instructions being required, therefore chip size increases, (as new data types are introduced) but also additional code required for lots of corner case handling, increasing code size (therefore bill of materials (BOM) cost), along with requiring more power.

5.) If you have existing products and software utilizing packed-SIMD code, did you know that SiFive has tools to easily port your code to RISC-V vectors? SiFive Recode can easily take code designed and written for packed-SIMD implementations and port to SiFive vectors. Additionally, for new application code, we have been very active in the open source community to offer an LLVM-based auto-vectorizing compiler, to enable faster time to market.
 
6.) As modern workloads have evolved, more complex systems have been designed with customized accelerators such as DSPs (digital signal processors) and simple finite state machines (FSM), so as to offer the best performance for specific application workloads and algorithms. Whilst the performance gain can be impressive there are a number of shortfalls to this situation:

<ul>
<li>there can be increased power and chip area due to the need for the accelerator to match the speed of the main processor by implementing a cache system
<li>the accelerator may require a separate toolchain with associated increased software complexity (and potentially software design time)
</ul>

The X280 enables consolidation of custom accelerators and control processors, resulting in a more power efficient solution and ease of use and programmability, with standard software and out-of-the-the box open source toolchains.

7.) "Standard software" - two very important words to a software developer when working on complex designs. RVV is an open standard and much of the code written for RVV will be available in the open source domain. This allows developers to access the large and growing ecosystem of RVV-based algorithms, along with access to a full range of open source and commercial grade tools for compilation, modeling, debug and trace. The upside and key benefits of this are:

<ul>
<li>access to open source algorithms
<li>standardized and stable approach to algorithm development
<li>reduced development costs
<li>and crucially, enabling much faster time to market
</ul>

8.) RVV includes a broad range of data types; including floating point, integer, and fixed point that are efficiently executed on the same single Vector ALU; this simplifies the processor architecture, resulting in improved power efficiency and reduced chip area.

9.) SiFive has a strong customer base for its vector-based product line - in fact, it is one of the fastest licensed IP product lines. Following the 2021 release of the SiFive Performance P270 and SiFive Intelligence X280 processors, we have worked with customers to define a roadmap that adds some powerful new features and enhancements, higher performance vector-based processors, along with wider vector registers - watch out for more vector-based products throughout 2022 and beyond. If you want to find out more about licensing the P270 or X280 then please [contact us](https://www.sifive.com/contact-sales) for more details.

10.) Finally, if Vectors is your thing and you’re craving to be part of the growing teams across the globe building the next generation of products from SiFive then get in touch. We have some great career opportunities in the USA, Taiwan, France, and in the UK. Check out the [SiFive Careers page](https://www.sifive.com/careers) for all of the latest updates.

Want to learn more? [Contact us](https://www.sifive.com/contact-sales) or [access the other materials on our SiFive vectors page](https://www.sifive.com/technology/vectors)

Stay current with the latest SiFive updates via [Facebook](https://www.facebook.com/SiFive/), [Instagram](https://www.instagram.com/sifive_inc/), [LinkedIn](https://www.linkedin.com/company/sifive), [Twitter](https://twitter.com/SiFive), and [YouTube](https://www.youtube.com/c/SiFiveInc).

10 Important Things To Know About SiFive Vectors

**SiFive is the market leader in RISC-V Vector processors and has gained significant market traction, with solutions being designed into a broad range of applications ranging from computer vision, mobile ISP, Edge AI, to datacenter AI.**

As SiFive vector processors become the go-to workhorse processor for modern workloads, they are being chosen for stand-alone and companion processor designs in both large and small systems. As a growing list of customers use our designs, they feed back to us their requirements for next-generation devices, and SiFive is enhancing the current portfolio as well as investing heavily in new vector processors, and a long-term roadmap to take advantage of this exciting new solution. Current customers include:
<ul>
<li>A U.S. Federal agency for next generation aerospace/defense standards
<li>Tier #1 global mobile image processor solution
<li>Tier #1 global hyperscaler for AI datacenter/learning products
<li>Tier #1 storage product developer
<li>Tier #1 global automotive infotainment solution
<li>Large U.S. semiconductor company implementing an eFPGA system
<li>U.S. eFPGA company expanding into AI DataCenter applications
<li>Tier #1 U.S. aerospace application requiring state of the art microelectronics
</ul>

Tenstorrent, an AI semiconductor and software start-up developing next-generation computers, [announced the use of the SiFive® Intelligence™ X280 processor in their future AI training and inference processor](https://www.sifive.com/press/tenstorrent-selects-sifive-intelligence-x280-for-next-generation1). 

[Kinara (formerly known as DeepVision) licensed the X280](https://www.sifive.com/press/deep-vision-adopts-sifive-risc-v-to-add-opencv-enabled) (and other IP) to enhance the flexibility and functionality of their products to better support customers building applications for the fast-growing Internet of Things (IoT) markets like smart city, smart retail, automotive, and industrial.

SiFive vector processors are gaining momentum across these top-tier customers who are seeing the value and a number of key benefits. As customers share their requirements, in most cases the [SiFive Performance™ P200](https://www.sifive.com/cores/performance-p200) and [Intelligence X280](https://www.sifive.com/cores/intelligence-x280) fit perfectly well, and our roadmap instills the confidence that SiFive is looking to the future with further vector products in development now. 

Whatever your vector needs, SiFive can help! In addition to bringing trusted enterprise-ready RISC-V architecture, reduced BOM costs, and open standards, there are several key benefits that SiFive vector processors bring to designers, including:
<ul>
<li>Design flexibility
<li>Power and performance efficiency
<li>Portability
<li>Ease of programmability
<li>Use of standard software
</ul>

Let’s look at each of these in a bit more detail.

**Design Flexibility**

With RISC-V Vector Extensions, SiFive customers have tremendous freedom in both the way they design and also in the applications they pursue. The RISC-V ISA offers a compelling level of flexibility, and SiFive has capitalized on this with our product portfolio. SiFive currently has two vector products, one with 256-bit wide vectors and another with 512-bit wide vectors, along with an exciting roadmap taking us further into the higher performance market space. 

Due to the nature of the RISC-V architecture, SiFive is able to build fit-for-purpose products that align with customer requirements and application workloads. The RISC-V ISA baseline instructions number just 47, with the ability to add extensions as workloads require. This extends to the RISC-V Vector ISA, with its base ISA (numbering much less than a packed-SIMD implementation) and the ability to complement this with new workload-specific instructions, and then work with the RISC-V International team to bring this into the architecture as required. 

**Power and Performance Efficiency**

As we have seen with the flexibility of the RISC-V architecture, this also maps onto building fit-for-purpose products for our customers. Optimal system design achieves the right balance of performance for the application workload within a defined power constraint; when processing large data sets, it's about the optimum level of both scalar and vector performance. By selecting single core or multi-core, multi-cluster systems, companies are able to map this onto the required SiFive vector processor to achieve maximum performance efficiency, while meeting or exceeding their requirements for minimal area and power.

**Portability**

One of the most unique and powerful capabilities of the RISC-V Vector Extension is that the ISA is vector-length agnostic. This means that code written for a SiFive vector processor can run on any compatible RISC-V vector ISA processor, so it’s possible to experiment with different vector sizes to achieve the perfect balance of performance, power, and area for different application workloads. Also, with a growing base of open source software for vector processors, projects are easily portable between processors and applications for the same reason.

**Ease of Programmability**

A number of companies currently have designs that include one or more separate custom DSPs for performing specific application tasks. These custom DSPs needed to be designed to co-exist with the main processor, with some subtle design consequences, requiring in many cases the DSP to:

<ul>
<li>require access to, and use of the main system bus (for data transfers), potentially causing bus latency issues
<li>need its own cache system, for maintaining peak performance, with an associated increase in chip area
<li>require a separate proprietary toolchain for programming, along with the separation of algorithm tasks
</ul>

With the combined scalar and vector compute capabilities offered by SiFive vector application processors, companies have been able to consolidate the custom DSP functionality into the vector processor and still achieve performance and efficiency goals.

**Use of Standard Software**

RVV is an open standard, and much of the code written for RVV will be available in the open source domain. This allows developers to access the large and growing ecosystem of RVV-based algorithms, along with access to a full range of open source and [commercial grade tools](https://www.sifive.com/software) for compilation, modeling, debug, and trace. The upside and key benefits of this include:

<ul>
<li>access to open source algorithms
<li>standardized and stable approach to algorithm development 
<li>reduced development costs
<li>and, crucially, enabling much faster time to market
</ul>

Want to learn more? [Contact us](https://www.sifive.com/contact-sales) or [access the other materials on our SiFive vectors page](https://www.sifive.com/technology/vectors).

Stay current with the latest SiFive updates via [Facebook](https://www.facebook.com/SiFive/), [Instagram](https://www.instagram.com/sifive_inc/), [LinkedIn](https://www.linkedin.com/company/sifive), [Twitter](https://twitter.com/SiFive), and [YouTube](https://www.youtube.com/c/SiFiveInc).

SiFive - The Market Leader In RISC-V Vectors

**The RISC-V revolution continues to advance as the technology industry embraces open computing to address semiconductor design and business challenges**

Last week saw momentous announcements, with Intel Foundry Services (IFS) enabling RISC-V alongside other processor architectures as part of Intel’s dedication to an open ecosystem and to help make IFS become one of the world’s leading foundries. By joining RISC-V International and investing significant money and resources in the open specification RISC-V instruction set architecture, Intel is empowering the RISC-V ecosystem and helping drive further adoption of open computing. A great recap of these announcements is available from [EETimes](https://www.eetimes.com/a-big-week-for-risc-v/), and you can read the Intel original news [here](https://www.intel.com/content/www/us/en/newsroom/news/intel-launches-1-billion-fund-build-foundry-innovation-ecosystem.html), and the SiFive news [here]().
  

As always with big announcements, people want to know the bottom line - what does this mean? For SiFive, this week’s announcements mean opportunity, validation, and support for our vision of technology–a clear indication of the need for competitive processor IP to build SoCs that will support the market needs of automotive, data center, hyper scale, and edge computing platforms. Industry analysts predict there will be 25 billion RISC-V based AI SoCs in the next 5 years, representing a 34% CAGR for RISC-V CPU semiconductor IP(1).
 

We hear from our customers and partners that the need for specialized SoC design is key, along with a quick time to market. SiFive’s portfolio and approach enables a common, open standard to be the computing base, with focused products that align the hardware to the software. There is no incumbent in these market opportunities, enabling RISC-V and SiFive to win on our merits - something we are truly excited about! 
 

**Developing for RISC-V**

SiFive had a breakout year in 2021, as we entered performance-driven markets with new products to be part of the high-value silicon blocks that deliver the experiential uplift. We launched the SiFive Intelligence™ family in Q2 of 2021 and now have several licensees, following our first public win with AI leader Tenstorrent. Similarly, the SiFive Performance™ P550 has multiple licensees including Intel, as part of the IFS “Horse Creek” platform and SoC. Delivering 3x more performance per area than our competitor’s core, as well as being the fastest commercially available RISC-V processor IP at launch, contributed to why the SiFive Performance P550 will be at the forefront of Intel’s RISC-V development platform. We saw firsthand the power of seeding the industry with our SiFive HiFive line of developer boards, and our partnership with Intel will take those efforts to the next level.
 

As an IFS Accelerator - IP Alliance partner, SiFive will offer our industry-leading portfolio of RISC-V-based processor IP to customers of IFS, supported by our partnership with Intel’s $1B innovation fund, a collaboration between Intel Capital and IFS. In addition to investing in disruptive startups, Intel will dedicate expert open source software developers to collaborate with SiFive to enhance and grow the RISC-V ecosystem, using the “Horse Creek” Development system powered by SiFive Performance P550 processor cores.


**The Open Computing Era**

The RISC-V instruction set architecture was invented over a decade ago to enable freedom to innovate and avoid the pitfalls of proprietary technology, and SiFive is the vehicle the inventors of RISC-V has chosen to explore the commercial opportunities of the open specification. The open approach of RISC-V is combined with the collaborative nature of RISC-V International and the technical groups to enable contributions from many parts of the world. As part of these groups, premier members like SiFive and Intel are able to openly help develop the specifications and extensions that all parts of the RISC-V ecosystem can implement. From hardware to software, the open specification of RISC-V ensures an era of open computing is enabled.
 

This is what I mean by the headline “investment heard around the world.” We’re well past the time of “Is RISC-V going to take off?” and into “How high can it go?” The answer is that RISC-V has no limits, and SiFive is eager to show what our immensely talented team is capable of. We’re hiring at many levels and we’d love to hear from you if you think you’d be a good fit - please see our career options, [here](https://www.sifive.com/careers). This year, we’re going to deliver on our promise to bring the SiFive Performance P650 (2) to market, and continue to innovate and extend our performance leadership in RISC-V!
 

Footnotes:

1 - SemiCo Research report CC330-21, “[Analyzing the RISC-V CPU Market for SIP, SoCs, AI and Design Starts](https://semico.com/content/analyzing-risc-v-cpu-market-sip-socs-ai-and-design-starts)”

2 - Case study from The Linley Group by Techinsights, "[SiFive P650 Pumps Up Performance by 50%](https://www.sifive.com/resources/case-studies/sifive-p650-pumps-up-performance-by-50)" 
  

SiFive_Blog_Feb142022.png

**SiFive joins the Intel Foundry Services IP Alliance program to broadly enable innovative new computing platforms**

In 2021, SiFive evolved our industry-leading RISC-V portfolio of processor IP into three families, each with a focused purpose. The [SiFive Essential™](https://www.sifive.com/cores/essential), [SiFive Performance™](https://www.sifive.com/cores/performance), and [SiFive Intelligence™](https://www.sifive.com/cores/intelligence) families leverage the expertise of our company founders who created RISC-V and our talented engineers to build products that will address the entire semiconductor industry, from embedded applications to performance-driven uses and applications powered by AI/ML. The SiFive portfolio of RISC-V processors enables choice in the pureplay IP market to enable computing platforms optimized for the market application. 

As part of the mission to expand RISC-V to every market and application, SiFive works with leading semiconductor foundries to enable their customers to quickly adopt SiFive technology and optimize their designs. We’re excited to announce that SiFive is partnering with Intel Foundry Services (IFS) [Accelerator – IP Alliance program](https://www.intel.com/content/www/us/en/foundry/ifs-accelerator.html), to optimize SiFive IP for IFS customers and deliver maximum performance and value from both technologies. 
 
SiFive previously announced [a collaboration with Intel](https://www.sifive.com/blog/sifive-collaborates-with-new-intel-foundry-business) using the [SiFive Performance P550](https://www.sifive.com/press/sifive-performance-p550-core-sets-new-standard-as-highest) processor to build a RISC-V development platform, codenamed “Horse Creek,” combining Intel’s leading-edge interface IP such as a PCIe® and DDR with SiFive high-performance CPU IP. We’re excited to extend our relationship with IFS to ensure the full SiFive RISC-V processor portfolio is available to IFS customers, including the recently announced [SiFive Performance P650](https://www.sifive.com/press/sifive-raises-risc-v-performance-bar-with-new-best-in-class) processor. As the world’s fastest commercially available RISC-V processor IP, the SiFive Performance P650 extends RISC-V into new markets including automotive, AI/ML, client computing, data center, and mobile, among others. To stay informed on updates on the “Horse Creek” RISC-V developer board, please register [here](https://www.sifive.com/horse-creek-updates). 
 
“We are pleased to announce the IFS Ecosystem Alliance as a major step forward for Intel's foundry ambitions,” said Rahul Goyal, VP and GM of Intel Product & Design Ecosystem Enablement. “We are excited to have SiFive join the alliance. We look forward to partnering with SiFive to extend their leadership IP with IFS for the benefit of our mutual customers world-wide.” 

You can learn more about the SiFive portfolio in our recent presentations at the RISC-V summit, available for replay on YouTube here:
<ul> 
<li> <a href=https://youtu.be/jZ-1i9ZoSZ4>Keynote: The Future of RISC-V Has No Limits</a> (Yunsup Lee, Co-Founder & CTO, SiFive)</li>
<li> <a href=https://www.youtube.com/watch?v=UsiWahIy-r4>Implementing Functionally-safe RISC-V IP for Automotive and Safety Critical Applications</a> (Shubu Mukherjee, VP Architecture, SiFive)</li>
</ul>

At SiFive, you can work alongside experienced industry leaders and the inventors of RISC-V. We encourage you to consider SiFive as the next stage of your career, as we look for talented individuals in many areas to help accelerate our mission of greater choice in the pureplay processor IP market. You can view our career options [here](https://www.sifive.com/careers). 

Stay current with the latest SiFive updates via [Facebook](https://www.facebook.com/SiFive/), [Instagram](https://www.instagram.com/sifive_inc/), [LinkedIn](https://www.linkedin.com/company/sifive), [Twitter](https://twitter.com/SiFive), and [YouTube](https://www.youtube.com/c/SiFiveInc).

IFS-SiFive-Blog-1080x1080-Feb2022.png

**SiFive is aiming high with bold new technology for performance-driven applications**

SiFive transformed in 2021 and grew from leading RISC-V for embedded products into performance-demanding markets, creating real choice in the semiconductor processor IP market. Now, the SiFive portfolio features three distinct, market-focused product families, based on market requirements ranging from high-performance applications, machine learning and artificial intelligence processing, to embedded real-time deterministic and small application processors. Our RISC-V IP portfolio is designed around our focus to deliver processor IP for these demanding markets, combining the unlimited potential of RISC-V with the experience and talent of our team. 

This rapid progress was made possible by our partners and customers who believe and invest in RISC-V and the freedom it represents for technology. RISC-V has no limits, and all of us at SiFive are thankful and grateful for all our partner’s support in creating new products for the untapped potential of new and fast growing markets. In 2021, we reached significant milestones for our company with over 300 design wins at more than 100 companies, including 8 of the top 10 semiconductor companies; and we launched our new SiFive Intelligence™, SiFive Performance™, and SiFive Essential™ product brands with class-leading products in each family. 

**A Breakout Year** 
In 2021 we launched several new products. Most recently, we expanded the SiFive Essential family with the introduction of the SiFive Essential 6-Series processors, designed for mid-range applications; we also introduced the SiFive Performance P650, our fastest RISC-V processor, which will be available to lead customers in Q1 2022. Earlier this year we launched the SiFive Intelligence X280 for AI/ML markets, featuring SiFive Intelligence Extensions that build upon the RISC-V Vector extension to provide a platform for AI & ML with enhanced data types and support for TensorFlow Lite. The SiFive Intelligence X280 is a great inference processor and may be combined with existing hardened AI IP to enhance programmability and scalability by offering scalar and vector capabilities. The SiFive Performance P550 and SiFive Performance P270 processors for performance driven markets were also introduced in 2021, with up to 8-core coherent clusters and multiple clusters in an SoC, with heterogeneous mix+match options to allow for the right mix of processing capabilities. 


The RISC-V ecosystem has moved forward significantly in 2021 with important specifications ratified that unlock and enable hardware and software development in key markets. Working alongside the RISC-V community has been a pleasure for the many SiFive employees who contribute to the technical groups that develop RISC-V specifications as we all work together to build the technology and tools needed for virtualization, advanced interrupts, vector processing, and more. 

Building IP based on these new specifications is a key goal for SiFive, enabling our customers to quickly adopt the ratified standards. In 2021, SiFive offered three releases using our relentless innovation methodology to deliver new features in a software-like manner across our portfolio. SiFive increased efficiency and performance across our RISC-V processors, and introduced new features for cluster scalability, security, advanced power monitoring and control, and virtualization. 

**Raising The Bar in 2022** 
In 2022, we’ll continue to deliver high performance processor IP that will enable the creation of new computing platforms. From the metaverse to autonomous vehicles, natural language processing, recommendation systems, client computing devices and more, there is massive demand for RISC-V. We’re making the most of this demand by continuing to deliver high-performance processor IP packed full of performance and accompanied by the features our customers and partners require. If you didn’t catch them already, you can see some great pointers on what we’re doing in these talks from the 2021 RISC-V Summit: 

<ul> 
<li> <a href=https://youtu.be/jZ-1i9ZoSZ4>Keynote: The Future of RISC-V Has No Limits</a> (Yunsup Lee, Co-Founder & CTO, SiFive)</li>
<li> <a href=https://www.youtube.com/watch?v=-0xQ63xD3zA>Keynote: RISC-V State of the Union</a> (Krste Asanovic, Co-Founder & Chief Architect, SiFive, and Chairman of the Board, RISC-V International)</li>
<li> <a href=https://www.youtube.com/watch?v=UsiWahIy-r4>Implementing Functionally-safe RISC-V IP for Automotive and Safety Critical Applications</a> (Shubu Mukherjee, VP Architecture, SiFive)</li>
<li> <a href=https://www.youtube.com/watch?v=be5zBe-UHds>Continuous Innovation in Embedded RISC-V Processors</a> (Drew Barbier, director, product marketing, SiFive)</li>
</ul>

If you’d like to be part of the rapid rise of RISC-V, SiFive is looking for talented individuals in many areas. You’ll work alongside the inventors of RISC-V and leaders in the semiconductor industry as we design, develop, and deploy RISC-V technology for a variety of computing challenges. Please look at our careers page here for more information and take the next step to be part of the unlimited future of RISC-V! 
 
We wish all of you a prosperous and happy 2022! Keep up with SiFive news and announcements on social media: [Facebook](https://www.facebook.com/SiFive/), [Instagram](https://www.instagram.com/sifive_inc/), [LinkedIn](https://www.linkedin.com/company/sifive), [Twitter](https://twitter.com/SiFive), and [YouTube](https://www.youtube.com/c/SiFiveInc).

SiFive_Blog_RapidRiseOfRISCV_Jan2022.png

**The RISC-V Summit 2021 highlighted to the world that the future of RISC-V has no limits!**

2021 has been an outstanding year for SiFive, and the biggest in its history, starting with the introduction of the AI/ML focused [SiFive Intelligence™](https://www.sifive.com/cores/intelligence) and high performance [SiFive Performance™](https://www.sifive.com/cores/performance) series of processors and culminating with the announcement of the [SiFive Performance P600](https://www.sifive.com/cores/performance-p600) and latest SiFive 21G3 release as part of the [RISC-V Summit 2021](https://riscv.org/event/2021-risc-v-summit/). 

**Specifications** 
In parallel, RISC-V International has ratified an impressive [fifteen new specifications](https://riscv.org/announcements/2021/12/riscv-ratifies-15-new-specifications/). The new RISC-V Vector extension, as seen in the SiFive Intelligence X280 and SiFive Performance P270 products, and the RISC-V Hypervisor specification, now available in the SiFive Performance family of processors, are key technology enablers that will drive the continued growth of SiFive adoption further into an ever broadening range of applications and market segments. 

**Performance**
After a sneak peek at [The Linley Group Fall Processor Conference](https://www.tomshardware.com/uk/news/sifive-develops-ultra-high-performance-risc-v-core) back in October, SiFive recently took the wraps off our latest high performance processor, the [SiFive Performance P600](https://www.sifive.com/cores/performance-p600), SiFive's flagship product for 2022. The SiFive Performance P650 highlights SiFive’s commitment to continuously innovate and deliver a high-performance roadmap of RISC-V processors, and achieves a [leap in performance overall of over 50%](https://www.sifive.com/press/sifive-raises-risc-v-performance-bar-with-new-best-in-class) in just one year when compared to the SiFive Performance P550. 
The SiFive Performance P650 further extends its reach into the ultra high end market with a best in class 11+ SPECint2k6/GHz benchmark score, making the SiFive Performance P650 the highest performance licensable RISC-V processor. 
The SiFive Performance P650 will offer scalable performance with multi-core, multi-cluster processor configurations initially up to 16 cores, and includes the recently ratified Hypervisor extension. Our roadmap will, over time, extend to many-cluster capabilities that deliver 128-cores, or more, in an SoC.

**Relentless Innovation**
The SiFive 21G3 release includes the launch of the mid-range [SiFive Essential™](https://www.sifive.com/cores/essential) 6-series processor family along with a stack of further enhancements, including multi-cluster capability for the SiFive Performance family and SiFive Intelligence family.

The SiFive Essential 6-series is an eight-stage, single issue, in-order pipeline processor family targeting mid-range performance markets. The SiFive Essential 6-Series continues to deliver on SiFives’s commitment and investment in best in class performance processors with advanced features and configurability options including; RISC-V ISA B Extension for improved performance and code-density, and an optional half-precision FPU unit for area constrained applications, along with separate instruction tightly integrated memory (ITIM) and Instruction Cache (with an option for removing the i$ for specific market requirements).

![SiFive Essential Family](https://images.prismic.io/sifive/4d90a7c0-839b-44f5-96b5-59fe2f2380d9_SiFiveEssential762family.png?auto=compress,format)

The SiFive Performance P550 has gained a 10% increase in maximum frequency improvement and 10% dynamic power reduction as part of the latest release, achieving a 8.7+ SpecINT2k6/GHz benchmark, the market leading highest single thread performance metric. 

In AI/ML markets, the SiFive Intelligence X280, launched earlier this year, is already being designed into a multitude of machine learning products. To further extend its market applicability, BFLOAT16 matrix multiplication compute and quantization acceleration have been added to the SiFive Intelligence Extensions, delivering significant performance improvements across a wide range of machine learning workloads.

**Reach The Summit**
For SiFive, RISC-V, and the whole IP industry, 2021 was an inflection point with the expansion from great achievements in embedded control type applications to the opening up of the markets with ultra high-end processors like the SiFive Performance P550 & SiFive Performance P650, and AI/ML compute with advanced vector computation covered by the SiFive Performance P270 and SiFive Intelligence X280. The SiFive Performance P650 has raised the bar for high-performance and sets the stage for a phenomenal 2022 - stay tuned for more innovation announcements next year.

**SiFive Presentations at the 2021 RISC-V Summit**
SiFive delivered presentations and keynotes at the 2021 RISC-V Summit event highlighting the impressive progress and unlimited promise of RISC-V. You can view a representative few without a login required: 
<ul> 
<li> <a href=https://youtu.be/jZ-1i9ZoSZ4>Keynote: The Future of RISC-V Has No Limits</a> (Yunsup Lee, Co-Founder & CTO, SiFive)</li>
<li> <a href=https://www.youtube.com/watch?v=-0xQ63xD3zA>Keynote: RISC-V State of the Union</a> (Krste Asanovic, Co-Founder & Chief Architect, SiFive, and Chairman of the Board, RISC-V International)</li>
<li> <a href=https://www.youtube.com/watch?v=UsiWahIy-r4>Implementing Functionally-safe RISC-V IP for Automotive and Safety Critical Applications</a> (Shubu Mukherjee, VP Architecture, SiFive)</li>
<li> <a href=https://www.youtube.com/watch?v=be5zBe-UHds>Continuous Innovation in Embedded RISC-V Processors</a> (Drew Barbier, director, product marketing, SiFive)</li>
</ul>

**Keep Climbing**
I joined SiFive this year after spending more than twenty years’ in the IP industry, and I am wildly excited about the technology, growth opportunities, and direction SiFive is taking. As the first UK employee, I’m thrilled to see more people eager to join and the team expanding; if you’re interested in joining me and embracing the challenge here in the UK, USA, or further afield, check out the career opportunities at [SiFive.com/Careers](https://www.sifive.com/careers).

sifive-blog-logo.png

## The freedom of RISC-V enables a bright future for SiFive

What a time to be in the Semiconductors and CPU industry! As an industry, we are experiencing a perfect storm. With the rise of machine learning, cloud computing, and autonomous driving; the need for advancement in computing has never been greater. This is happening at a time when Moore’s law has considerably slowed and dennard scaling has come to an end. Architectural innovation is required to break out of the current logjam, but the closed nature of proprietary ISAs that have dominated our industry for three decades are unwieldy and unsuitable for application-specific computing needs going forward. 

> *"Moving forward, the logical path is to add extensions to the basic instruction sets on microprocessors for application domains"* 
> - [David Patterson](https://cacm.acm.org/magazines/2020/5/244325-will-risc-v-revolutionize-computing/fulltext?fbclid=IwAR2gT41IiQM9WUnP4gmgcUrgEhra2rE4I9MjwJjbmOchw26Ij0v6-WMauPQ) (Computing pioneer, Turing award winner, and father of RISC architecture), speaking to **CACM**

The open nature of the RISC-V ISA coupled with SiFive’s best-in-class design methodology makes it an ideal place to build the next computer. SiFive is already the premier supplier of RISC-V CPU to the industry, with 300+ design wins, 100+ customers, and 8 out of the top 10 semiconductor companies and I’m super excited to have the opportunity to be a part of this revolution. 

Today I’m thrilled and proud to announce that I have joined SiFive to lead the Engineering team to build the best-in-class processor IPs that will be at the heart of future computing platforms.

I’ve been lucky to be associated with both of the major computing platforms of the last 25 years. First at AMD, where I worked on their highest-performance x86 CPUs, and then at Apple, where I led the implementation of CPU IP in the A5X through A13 SoCs. It was humbling to have the opportunity to lead the first implementation of the 64-bit mobile CPU (cyclone) that changed the world. During this journey, I pioneered many low power design techniques and we hired & built one of the best CPU design teams. Fitting desktop CPU performance into a phone power envelope required re-thinking everything from architecture to floorplan to clocking to std cell library choices and novel ways to visualize power so the entire team could focus on power-first design. 

At SiFive we’re building best-in-class CPUs with a full range of performance options that give our customers more choice & flexibility. I’m looking forward to [scaling the team](https://www.sifive.com/careers) to achieve new heights in performance and power efficiency. To learn more about our capabilities and products, please come see me at the [RISC-V Summit](https://events.linuxfoundation.org/riscv-summit/register/), Dec 6-8.

RohitKumarIntroBlog111921.png

## In just a few short years, RISC-V has become a category of utmost importance in tech; but, things are just getting started.

In 2014, the inventors of RISC-V (and founders of SiFive) published a very [“modest”](http://people.eecs.berkeley.edu/~krste/papers/EECS-2014-146.pdf) goal: for RISC-V to become the standard ISA for all computing devices. Ambitious at the time, but now we can confidently state that RISC-V has made its impact in our industry and is here to stay. RISC-V has become hugely important – strategic to companies and governments alike – and has already made its way into billions of chips and thousands of companies.

And… we’re just getting started.

This week, you may have noticed SiFive unveiled a new look on our website and a clear focus on high performance as we continue to drive RISC-V forward and define the future of compute. RISC-V is inevitable, and we are accelerating that timeline.

To our internal teams, this energy, aggressiveness, and decisive roadmap is nothing new. We’ve been building successful products for years, and now we’re growing faster than ever. Our resolve has never been stronger: to build the best-in-class processor IP that will be at the heart of future computing platforms — from artificial intelligence, machine learning, automotive, data center, mobile, to consumer markets. As we rapidly accelerate our performance capabilities, RISC-V truly will have no limits.

I’ve never been prouder of SiFive’s talented, passionate, and forward-thinking engineering and product teams. We’ve built a world-class portfolio of processor IP with over 300 design wins at more than 100 different customers around the world, including 8 of the top 10 semiconductor companies.

To our customers: thank you for being part of our journey and shared vision of the future. We’re honored by your trust and partnership, and we hope we’ve delivered an incredible customer experience along the way; but, buckle up, because we’re about to turn the corner and take RISC-V to new heights of performance and capabilities. 

We’ll share more about our future plans at the upcoming [RISC-V Summit](https://events.linuxfoundation.org/riscv-summit/) on Dec 6-8, including details on our next-generation processor architecture that will be our fastest processor ever. We’re also hiring—across all positions and all career levels to accelerate our journey. If you’d like to work alongside the creators of RISC-V, collaborate with top industry partners, and help create the future of RISC-V, we invite you to [join us.](https://www.sifive.com/careers) 

The future of RISC-V has no limits. And I, for one, couldn’t be more excited!

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## Scalable High-Performance Computing SoC Design with RISC-V

Whether you refer to the design concept as a disaggregated die, tiles, chiplets, or good ol’ multi-chip modules, a growing trend among SoC designers is making the interposer act like a ‘mainboard’ to host multiple chips. Together, these chips form a coherent whole product intended for a specific market and offer both advanced workload performance and efficiency benefits.

[The technology industry is shifting](https://www.cnbc.com/2021/09/06/why-tesla-apple-google-and-facebook-are-designing-their-own-chips.html) to custom designs, replacing traditional general-purpose CPU and discrete accelerator platforms. Instead, the computing platform can implement application-specific processing requirements at many levels, down to the instruction set architecture (ISA). Enabling this industry shift is central to SiFive’s mission and why SiFive’s founders invented RISC-V a decade ago.
 
**Bet on yourself with RISC-V Chiplets**
Based on an easily extensible open specification, the RISC-V ISA lets semiconductor companies “bet on themselves” by leveraging targeted microarchitecture development to enable a developer-friendly approach to hardware and SoC design. Because software and hardware meet at the instruction set architecture, the open specification RISC-V ISA permits freedom of adoption, vendor, extension, and customization; key traits shared with successful open technologies, such as Ethernet or Linux.
 
SiFive is the leading provider of RISC-V-based processors and accelerator IP and is home to the inventors of RISC-V and LLVM. As part of the RISC-V Vector extension task group, we’re excited to drive and see worldwide adoption of RISC-V Vectors as a path to creating AI and ML-focused products in markets such as AIoT, automotive, aerospace, networking, storage, hyperscale computing, and the data center. SiFive is betting on ourselves to deliver high-performance, high-quality RISC-V-based IP that will enable next-generation computing platforms.

With over 200 design wins and a billion cores shipped, technology companies can double down on that bet by working with SiFive and granting themselves the freedom to innovate.
 
**AI in the data center and HPC**
Workloads well-suited for processing on chiplets need [die-to-die (D2D)](https://openfive.com/die-to-die-ip-subsystem/) communication to support the bandwidth requirements of the datasets. Combined with the advanced 2.5D packaging solutions from OpenFive, a SiFive business unit, and high performance, low power, and low latency HBM/D2D interface IP, designers can now create systems-on-chip (SoCs) that pack more compute power into smaller form factors for AI and HPC applications.
OpenFive delivers highly competitive SoCs with its spec-to-silicon design capabilities, customizable IP for AI/Cloud/HPC/storage/networking applications, and processor-agnostic, domain-specific architectures. 
The [OpenFive IP portfolio](https://openfive.com/ip/) includes: 
- Die-to-Die (D2D) interface IP for multi-die connectivity, including chiplets 
- High-Bandwidth Memory subsystem (HBM2/E & HBM3)
- Low-latency, high-throughput Interlaken interface IP for chip-to-chip connectivity 
- 800/400G Ethernet MAC/PCS subsystems 
- USB controller IP

**Architecting the Future**
The SiFive portfolio leads the industry as the broadest and most advanced RISC-V-based portfolio of processor IP, from the minds that created RISC-V. With [leading companies](https://www.tomshardware.com/uk/news/apple-looking-for-risc-v-programmers) implementing RISC-V-based designs for machine learning, computational vision, natural language processing, and other tasks, the need for scalable, flexible microarchitectures extends across many markets.

![RISC-V Chiplet Architecture Diagram](https://images.prismic.io/sifive/f3b221b4-135b-4595-ad2a-c22dd13d51b6_RISCvchipletsoutlineblog.png?auto=compress,format)

**SiFive RISC-V Chiplet Architecture IP**
- SiFive Performance™ family
 * [SiFive Performance P550](https://www.sifive.com/press/sifive-performance-p550-core-sets-new-standard-as-highest)
 * Advanced Out-of-Order 13-stage, triple issue pipeline
 * SPECInt 2006 8.65/GHz
 * Highest performance commercially available RISC-V processor _(1)_
 * [SiFive Performance P200](https://www.sifive.com/cores/performance-p200)
 * 8-stage, dual-issue, superscalar pipeline
 * 256b Vector unit for versatile compute capabilities
- SiFive Intelligence™ 
 * [SiFive Intellligence X280](https://www.sifive.com/blog/whats-new-in-ai--ml-from-sifive)
 * 8-stage dual-issue, superscalar pipeline
 * 512-bit Vector unit with SiFive Intelligence Extensions to supercharge ML performance _(2)_
 * Support for BF16/FP16/FP32/FP64, int8 to 64 fixed-point data types
- SiFive Recode™
 * Creates SiFive RISC-V Vector code from legacy Arm® Neon™ code to protect your existing software investment and migrate with confidence
- SiFive Essential™ family
 * [SiFive U/S/E class processors](https://www.sifive.com/cores/essential)
 * U class cores for 64-bit Linux-based application platforms
 * S class cores for 64-bit embedded applications
 * E class cores for 32-bit embedded applications
- OpenFive Die-to-Die Subsystem
 * Low latency, low-power, interface supporting up to 4Tbps/mm
 * Multi-cluster CPU connectivity
 * Network-on-Chip interface with support for AMBA® AXI and other coherent interfaces
 * Scalable, reliable links with very low BER, supporting end-to-end error correction & retransmission
- OpenFive High-Bandwidth Memory Subsystem
 * 7.2Gbps speeds for HBM3 standard

[SiFive](https://www.sifive.com/) and [OpenFive](https://www.openfive.com/) enable RISC-V-powered chiplet designs for AI/ML products today, accelerating the design of new high-performace computing platforms and leading the [RISC-V uprising](https://www.forbes.com/sites/karlfreund/2021/09/08/if-the-arm-deal-fails-nvidia-is-fine-but-arm-may-struggle/).

*1 – SiFive Performance P550 processor measured at 8.6 SpecINT2k6/GHz by SiFive engineering, July 2021.
2 – Matrix Multiplication Kernel (int8) execution time in common benchmark measured by SiFive engineering using SiFive Intelligence X280 processor vs. RVG64GCV RISC-V Vector configuration.
All trademarks referenced herein belong to their respective companies. Arm®, and Neon™ are trademarks or registered trademarks of Arm Limited (or its subsidiaries) in the US and/or elsewhere.*

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RISC-V Chiplets, Disaggregated Die, and Tiles 

# Leading the RISC-V uprising drives SiFive, home of the inventors of RISC-V, to continue to push forward with developing our product families and technologies.

## RISC-V for High-Performance Applications 
Earlier this year, we debuted the [SiFive Intelligence](https://www.sifive.com/cores/intelligence) family at the Linley Group [Spring Processor Conference](https://www.youtube.com/watch?v=3WyMdegWgh8), including one of our [lead customers, Tenstorrent](https://www.sifive.com/press/tenstorrent-selects-sifive-intelligence-x280-for-next-generation1), who will integrate the [SiFive Intelligence X280](https://www.sifive.com/cores/intelligence-x280) in a future product line. In June, we introduced the [SiFive Performance](https://www.sifive.com/cores/performance) family of processors, including the [SiFive Performance P500](https://www.sifive.com/cores/performance-p500) and [SiFive Performance P200](https://www.sifive.com/cores/performance-p200). 

With the SiFive 21G2 release, we are pleased to invite designers to evaluate these new processors, as well as discover the 21G2 release enhancements to the [SiFive Essential processor family](https://www.sifive.com/cores/essential). From the fastest RISC-V commercial processor IP available today, the SiFive Performance P550(1), to the newly enhanced SiFive Essential product lineup, SiFive offers the broadest and most capable RISC-V-based processor portfolio. We continue to work with technology innovators and industry leaders to develop new products that will push the envelope of computing capabilities. 

To ease smooth adoption of this new technology, SiFive Recode automatically translates existing Arm® Neon™ code to RISC-V Vector code for the SiFive Intelligence and SiFive Performance products that offer RISC-V Vector extension execution capability. Included in the SiFive Freedom toolchain are GCC and LLVM compilers specifically designed to help write software optimized for RISC-V and the RISC-V Vector extension. 

[Join us in September](https://community.riscv.org/events/details/risc-v-foundation-risc-v-forums-presents-risc-v-forum-vector-and-machine-learning) at the RISC-V Forum for RISC-V Vectors and Machine Learning to learn more about the potential for RISC-V Vectors, an open specification developed by Industry-leading companies & researchers, to address modern computing challenges. 
 
## Making Development Easier 
Developing ahead of silicon availability is key to a smooth and fast product development cycle. SiFive includes and supports Linux FPGA bitstreams with its SiFive Performance, Intelligence, and Essential application processors. The Linux software development platform is based on the Xilinx VCU118 to provide a fast, no-hassle mechanism to evaluate SiFive cores in an off-the-shelf environment. Included with the processor core bitstream is a functional peripheral subsystem, including common interfaces, and [SiFive Insight](https://www.sifive.com/technology/sifive-insight) Advanced Trace and Debug to enable processor evaluation. The SiFive Freedom SDK enables application development and workload modeling to help product evaluation as you program the FPGA, build your SD card, and boot into Linux to get started. 

## SiFive Relentless Innovation 
Driven by the market demand for workload-focused designs, SiFive processor cores are configurable with unmatched options for workload tuning. Our innovative methodology and automation enable us to deliver not just new products like the recently announced SiFive Performance family of processors, but also enhance and advance our existing product families. You can license access to cores, families, or the entire portfolio, ensuring you have the flexibility and scalability you need to fuel your product roadmap. 

We call this process SiFive [relentless innovation](https://www.sifive.com/risc-v-core-ip), and it’s the backbone of the SiFive 21G2 update that offers many new features and enhancements that are [now available](https://www.sifive.com/resources/webinar/introducing-sifive-performance-family). 

## Faster is Essential 
The SiFive Essential 7-series processor cores continue to offer enhanced performance, without significantly impacting power or area. With the SiFive 21G2 release, SiFive Essential 7-series processors offer up to 11% more performance than the 21G1 release(2), thanks to the enhanced design updates that reduce latency and improve instruction throughput. These performance improvements deliver important increases in efficiency for SiFive Essential 7-Series processors, which have applications in many markets including computational storage, edge computing, IoT, network baseband, virtual reality, and more.

## Programmable Remapping 
SiFive Essential S7, E7, S5, E5, S2, and E2 embedded and control processors now offer software programmable address remapping to enable data region remapping and ROM code patching, with support for both instruction and data addresses. The address remapper is configurable to provide a balanced trade-off between area use and functionality, offering up to 64 remap regions that can scale from 4 bytes to the full address space. 

The SiFive Essential family is silicon-proven IP in the world’s leading foundries, and offers SiFive Insight advanced trace and debugging capabilities to make it easy to integrate and productize RISC-V-based processors. For more information on the SiFive products discussed today, please watch our webinar replay, available now. 

Footnote 
1 - Based on SiFive Internal Engineering measurement of a geomean score of 8.65 SPECint2k6/GHz and 9.4 SPECfp2k6/GHz by SiFive Performance P550 in emulation using maximum performance configuration with simulated memory subsystem at 100ns memory latency (load to use) running the full SPECit 2006 benchmark. 
2 - The SiFive Essential 7-series 21G2 processors offer up to 11% higher score, comparing aggregate percentage increase of CoreMark/MHz and Dhrystone/MHz scores versus the 7-series 21G1 release processor scores, as measured by SiFive internal engineering team: SiFive U7 & S7 21G2 = 5.7 CoreMark/MHz & 3.2 Dhrystone/MHz; SiFive E7 21G2 = 5.7 CoreMark/MHz & 3.0 Dhrystone/MHz; SiFive U7 & S7 21G1 = 5.2 CoreMark/MHz & 2.8 Dhrystone/MHz; SiFive E7 21G1 = 5.2 CoreMark/MHz & 2.6 Dhrystone/MHz. 
All trademarks referenced herein belong to their respective companies. Arm and Neon are registered trademarks of Arm Limited (or its subsidiaries) in the US and/or elsewhere.

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Delivering on the Promise of Industry-Leading RISC-V Processors

## Introducing the new era of SiFive Performance for RISC-V

When I joined SiFive last year, I found a dedicated team working on great technology with a vision to do no less than to change the world.

As I talked to our customers and partners, it was clear that while we had satisfied users, the industry expected and desired greater things from SiFive. The message was loud and clear that SiFive needed to push the boundaries of what’s possible to bring high value, differentiated products to market. I knew that my job was to then enable and support our incredible collection of talent with the tools and resources needed for us to execute at a high level. 

This week marks an important milestone toward that mission, with the unveiling of new products that showcase our capabilities, reinforce our strategy, and are available today for evaluation and licensing. The announcement of the SiFive Performance family of processors heralds the arrival of a new era for both SiFive and for the RISC-V movement. Long gone are the days where RISC-V is only suited for cost-down replacements of legacy 32-bit architectures; from this point forward, SiFive and the RISC-V ISA will be mentioned in the same breath as the processor architectures that are powering today’s phones, laptops, and data centers. 

The arrival of the [SiFive Performance](https://www.sifive.com/press/sifive-performance-p550-core-sets-new-standard-as-highest) family of processors is proof that we’ve entered a new phase at SiFive, as we have just now delivered to lead customers the highest performance licensable RISC-V processor in the industry. However, “Performance” is more than simply a brand name for application processors with enviable benchmark scores; it represents an initiative within our company to continue to innovate to bring the highest possible performance processors to our partners’ SoCs. 

![SiFive PIE](https://images.prismic.io/sifive/ac74ec7b-d0b8-457b-9fa9-8f6849052cc9_SiFivePIE-Overview.png?auto=compress,format)

Followers of SiFive may recall that in April we announced another key initiative we call “Intelligence”; a software-centric approach to unleashing the power of RISC-V vector computing for machine learning applications. With our [SiFive Intelligence](https://www.sifive.com/cores/intelligence) X280 processor and support for popular CNN frameworks, we’re already enabling customers building machine learning silicon for both training and inference, in the datacenter and at the edge. 

I’d be remiss if I didn’t mention our portfolio of processors that have laid the groundwork for the innovation that we’re bringing to market today. These products that have been a part of 200 design wins are still a critical part of our journey and continue to evolve and improve with each new release. Going forward, we’ll refer to these fantastic and broadly adopted products as the [SiFive Essential](https://www.sifive.com/cores/essential) family of processor cores. 

Performance, Intelligence, Essential — words that demonstrate our vision, our mission, and our strategy. Now is an exciting time to work at SiFive. I encourage you to contact us to learn more about our great products, to watch our [upcoming webinars](https://www.sifive.com/resources/webinar/introducing-sifive-performance-family), and to let us know via social media how we’re doing . As we continue our business and technology growth, we’re hiring – please join us on our exciting journey! 

Stay tuned for more exciting announcements in the coming months: 
[Facebook](https://www.facebook.com/SiFive/), [Instagram](https://www.instagram.com/sifive_inc/), [LinkedIn](https://www.linkedin.com/company/sifive), [Twitter](https://twitter.com/SiFive), and [YouTube](https://www.youtube.com/c/SiFiveInc)

The Heart of SiFive is Performance, Intelligence, & Essential

**Introducing the SiFive Intelligence X280**

This week has been an exciting one for our team at SiFive, with a number of key announcements that are beginning to allow us to publicly share our strategy for the exponentially growing AI/ML market. While we are only scratching the surface of the impact AI/ML will have on our industry and our lives, it’s clear that the workloads, algorithms, and requirements are going to be constantly evolving and improving for the foreseeable future. 

These changing requirements make it exceedingly difficult to align workloads with purpose-built silicon. Hardwired accelerators may work well for matrix multiplication and convolution layers today but simply aren’t efficient or adaptable enough for more modern models, such as transformer-based models like BERT or recommendation models. What’s needed are adaptable AI and ML solutions with a flexible, future-proof approach enabled by efficient, programmable building blocks of hardware IP designed with a software-first ideology. 

This leads us to our biggest announcement this week, SiFive Intelligence. Today at the Linley Spring Processor Conference, Dr. Chris Lattner, President of Engineering and Product at SiFive, introduced the SiFive Intelligence X280. The SiFive Intelligence X280 extends RISC-V with SiFive Intelligence Extensions, integrating dedicated AI acceleration technology and extended data type support. SiFive Intelligence includes turnkey software solutions that utilize the X280's features to provide great AI inference performance and support for the full capability of TensorFlow Lite. The result is a programmable, scalable, and configurable platform to meet modern AI/ML processing requirements from the edge to the cloud, providing out-of-the-box compatibility with a wide range of popular machine learning models. 

We’re pleased to debut SiFive Intelligence and to be able to tell you that one of the first customers of the SiFive Intelligence X280 is AI developer Tenstorrent, an innovator in AI training and inference processors led by industry leaders Ljubisa Bajic and Jim Keller. The heterogeneous combination of Tenstorrent’s Tensix processing cores alongside the SiFive Intelligence X280 will bring efficiency and programmability to stay ahead of the requirements of next-generation AI workloads. Read more about [SiFive's collaboration with Tenstorrent](/press/tenstorrent-selects-sifive-intelligence-x280-for-next-generation1). 

This week also saw the announcement of a new partnership for SiFive, with Renesas licensing the SiFive RISC-V Core IP portfolio and collaborating with us on next-generation RISC-V solutions for the automotive markets. Our product portfolio includes 32 and 64-bit embedded real-time cores; advanced, high-performance RISC-V processor cores; and SiFive Intelligence. We’re excited to see what the future will bring as we collaborate to meet the automotive application requirements and the new AI workloads that will come from it. Read more details on the [Renesas blog post, Renesas and SiFive Partner to Jointly-Develop Next-Generation High-End RISC-V Solutions for Automotive Applications](https://www.renesas.com/us/en/about/press-room/renesas-and-sifive-partner-jointly-develop-next-generation-high-end-risc-v-solutions-automotive). 

The future of AI processing requires a software-first mindset built on a robust and open ecosystem like RISC-V. We combine RISC-V vectors and SiFive Intelligence Extensions to offer highly power- and memory-efficient compute without sacrificing programmability. RISC-V was invented by the founders of SiFive to build an instruction set architecture for the [new golden era of computing](https://cacm.acm.org/magazines/2019/2/234352-a-new-golden-age-for-computer-architecture/fulltext). The new [SiFive Intelligence line](/cores/intelligence), which is available now, combines all these elements to deliver the flexibility and performance needed by modern AI platforms.

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## OpenFive Tapes Out SoC for Advanced AI/HPC Solutions on TSMC 5nm Technology

Today, I am pleased to see OpenFive, a SiFive business unit that is the leading provider of customizable, silicon-focused solutions with differentiated IP, is continuing to make progress with AI design solutions with the creation of a reference design chiplet architecture using OpenFive Die-to-Die interface, OpenFive HBM3 IP subsystem, and SiFive 7-Series processor IP, for 2.5D-based SoCs. More details on the full announcement can be found on OpenFive’s announcement [here](https://openfive.com/pressrelease/), but today I want to call out the SiFive milestone of our first RISC-V processor core in 5nm. 

The SiFive RISC-V-based processor portfolio is the broadest in the industry, from our upcoming SiFive Intelligence processor cores featuring RISC-V vector capabilities to area-optimized real-time cores. SiFive believes that it takes more than great processor IP to be successful in these markets by offering class-leading advanced trace and debug IP enabled by SiFive Insight. SiFive Insight is delivered pre-integrated with SiFive processor cores and gives customers the tools they need to develop sophisticated applications and is well supported by leading industry tool vendors, IAR Systems, Lauterbach, and SEGGER. Uniquely, SiFive Insight is compatible with Arm® Coresight™ to simplify the use of RISC-V in mixed-ISA environments. 

SiFive addresses security needs with SiFive Shield, a pre-integrated, open, scalable platform architecture designed to enable whole SoC security for RISC-V designs. The SiFive Shield hardware cryptographic accelerator optionally enables the necessary elements to accelerate cryptography to securely boot an SoC, protect communications, and restrict access to the debug interface. 

SiFive regularly updates the processor portfolio as part of our ‘relentless innovation’ program, including the SiFive 21G1 release announced recently. You can learn more about the latest features and improvements, including support for half-precision data types for AI applications, [here](https://www.sifive.com/blog/sifive-core-ip-21g1). 

Dr. Chris Lattner, president of engineering and product at SiFive, will present the latest information on SiFive Intelligence at the Linley Virtual Spring Processor Conference on April 23rd. SiFive’s vision is to take a ‘software-first’ approach to SiFive Intelligence products, delivering flexible acceleration strategies that scale with the evolving nature of AI. Find out more and register for the conference, [here](https://www.sifive.com/blog/sifive-intelligence-at-linley-spring). 

AI has created an explosion of diverse architectures, increasing the need for building heterogeneous SoCs and using advanced foundry technology. SiFive and OpenFive IP are proven in TSMC 5nm process technology enabling more choice for leading semiconductor companies to define their next-generation AI-powered products for 5G, automotive, data center, edge, high-performance compute, or networking applications. 

To learn more about OpenFive’s idea-to-silicon methodology combined with TSMC 5nm capabilities to offer leading power-performance-area designs, please visit [OpenFive](https://openfive.com/).

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## Tremendous progress has been made in the last year bringing RISC-V vector (RVV) extensions to market in both hardware implementations and supporting compiler technologies. 

SiFive has gone a step further with the inclusion of new vector operations specifically tuned for the acceleration of machine learning operations. These new instructions, integrated with a multicore, Linux-capable, dual-issue microarchitecture, with up to 512b wide vectors, and bundled with TensorFlow Lite support, are well-suited for high-performance, low-power inference applications.

View more about <a href="https://www.sifive.com/cores/intelligence">SiFive Intelligence vector processing software and hardware</a> here.

At the upcoming Linley Spring Processor Conference 2021, Chris Lattner, SiFive’s President of Engineering and Product, will be presenting a technical update on SiFive’s vector processing solutions titled: “Enhancing RISC-V Vector Extensions to Accelerate Performance on ML Workloads.” In his talk, he will demonstrate how SiFive’s integrated software and hardware solution addresses low-power inference applications. Prior to SiFive, Chris led development teams (including TensorFlow infrastructure, MLIR, and other AI work) at Apple, Tesla and Google, and he is the creator of Clang, the compiler front end, as well as LLVM, the compiler infrastructure open source project.

Announced SiFive Intelligence vector processing Core IP includes products capable of supporting full-featured operating systems such as Linux.

We look forward to seeing you at the Linley event and sharing with you the updates to our vector processing solution.


More on SiFive RVV support:

<ul>
<li>SiFive collaborates to support RVV Intrinsics in popular GCC and LLVM compilers (<a href="/blog/risc-v-vector-extension-intrinsic-support">blog</a>)</li>
<li>Extending AI SoC design possibilities through Linux-capable vector processors (<a href="https://www.youtube.com/watch?v=WKNWx232rN4" target="_blank">video</a>)
<li>Introduction to SiFive Intelligence RVV Core IP (<a href="https://riscv.org/news/2020/05/sifive-the-direction-and-magnitude-of-sifive-intelligence-nick-knight-the-linley-group/" target="_blank">video</a>)</li>
</ul>

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SiFive Vector Processing Solutions To Be Highlighted at Linley Spring Processor Conference 2021

## The best just got better--SiFive’s latest Processor Core IP Portfolio release

We’re pleased to announce a comprehensive update to SiFive’s RISC-V Core IP Portfolio with the SiFive 21G1 release. This release brings important enhancements and new capabilities to SiFive® Core IP, the industry's broadest RISC-V IP Portfolio, ranging from the ultra-capable SiFive U7-Series to the extremely popular SiFive E2-Series, offering up to 35% more performance for bit processing algorithms; and up to 25% smaller code size. For a deep dive into the details of this exciting release, register to [watch the webinar on-demand]( /resources/webinar/sifive-21g1-release-webinar). 

## Improved Performance for IoT and AI Applications

There are several key enhancements to SiFive Core IP in the 21G1 release to improve computation throughput, not only through ISA and architecture, but also processor interface connectivity. The SiFive 2-Series and 7-Series processors are now available with the RISC-V “Bit Manipulation” extension, RV32B, with Zba and Zbb extensions. This gives much higher performance in bit processing algorithms, for example Cryptographic Hash algorithm can be accelerated by 35%. 

SiFive processors previously supported double and single precision floating point computation. In the 21G1 release, half precision floating point (FP16) has been added for a more complete floating point computation support. This has been added based on customer needs to reduce memory size and power consumption of floating point computation, as well as use in AI algorithm computation, which uses FP16 extensively. 

## Flexibility in SoC Hardware and Software Integration

This latest release improves SoC implementation of SiFive processors giving more flexibility and options in software programming and hardware connectivity. The organization of the memory map is now fully programmable, where SoC architects can set memory and block positioning to support legacy code or application specific requirements. 

For the U5 Series and U7 Series products (RV64 application processors), virtual addressing up to 48-bits and physical addressing up to 47-bits is supported with the new Sv48 option. This greatly extends the addressing range, allowing the SiFive cores to be easily integrated into large system designs with huge memory requirements. 

In the release, a new ultra low latency, high-bandwidth, interface is added to the 7-series processors, called the Core Local Port. This port is a dedicated interface for each processor, offering direct connectivity. High performance, time critical hardware blocks can be connected directly to the processor, giving low latency throughput, fully deterministic operation for time critical computation. In line with this, SiFive processors now support the new proposed RISC-V NMI specification, for mission critical applications. 

## Higher Performance, Smaller Code size

With the new computation features and data type support in this 21G1 release, high performance is achieved. However a key requirement from SiFive customers is reduction of code size, memory requirements, hence cost. As a result, SiFive has focused on improved libraries and toolchain support. A new and greatly improved C-library that has been fully integrated into the toolchain and SDK allows designers to easily achieve optimum performance, while reducing code size by up to 25% (compared to the previous 20G1 release). 

The processor enhancements in this release increase benchmark performance to 5.18 CoreMarks/MHz and 2.63 Dhrystone/MHz for 7-series processors. 

## Improved Trace, Debug and Security

SiFive Insight is the industry’s first pre-integrated debug and trace IP for RISC-V processor cores, enabling faster silicon bring-up, software/hardware integration, and application development. The Hardware Crypto Accelerator component already within SiFive processors (SiFive Shield) has been further extended with the addition of Public key accelerator (HCA-PKA). 

Uniquely, SiFive Insight features native Arm® CoreSight™ compatibility. By seamlessly integrating with Arm® CoreSight™, developers can integrate SiFive RISC-V based cores into mixed ISA designs and maintain their existing development environment. SiFive Insight has broad industry support from leading software companies such as [Green Hills Software](https://www.ghs.com/news/20200602_RISC-V_tools_support.html), [IAR Systems](https://www.iar.com/about-us/newsroom/press/?releaseId=3702222), [Lauterbach](https://www.lauterbach.com/frames.html?home.html), [SEGGER](https://www.segger.com/news/segger-announces-comprehensive-support-for-sifive-insight-debugtrace-platform/), with [SiFive Freedom Studio](https://www.sifive.com/boards) free tools also available. 

With this release, the Trace capability has been greatly enhanced with a variety of new capabilities. The type of tracing (history or branch) is now selectable, as well as the number of communication channels and trace buffer size. The History Trace Messages (HTM) offers 5x compression capability that is recommended for High-Performance multi-core implementations where large amounts of trace data is generated. 

## SiFive’s Best Portfolio Is Here

The SiFive 21G1 release offers new advanced computation capability with bit manipulation packages, half precision floating point, as well as code size reduction by up to 25%. SoC integration in terms of hardware and software has been optimized for more efficient computation, smaller size and faster time to market. 

By using SiFive’s latest release of Core IP, defining and adopting a high-performance, high-efficiency, secure RISC-V processor for your next application or real-time SoC has never been more attractive. Save time and effort with SiFive’s unique support for Arm CoreSight to minimize workflow disruption, and broad tool ecosystem support for SiFive Insight Advanced Trace and Debug. 

We can’t wait to engage with customers on the incredible new devices they’ll build using the substantial new capabilities of the faster, more efficient, more capable than ever SiFive Core IP portfolio. 

Please [contact us](https://www.sifive.com/contact-sales) if you would like to learn more about the SiFive 20G1 release directly from the team, or [watch the webinar on-demand]( /resources/webinar/sifive-21g1-release-webinar). 

**Footnotes 
(1) – 35% improved performance for bit manipulation computation algorithms based on SiFive internal engineering measurement of cryptographic hash function (nettle-sha256) running on a SiFive U7-Series (21G1) processor core. 
(2) – 25% smaller code size with update tools and C-libraries with 21G1 release, in comparison to same toolchain release in 20G1 release. The 25% is the best, largest amount of code size savings. 
(3) – Support for Half precision floating point for a wide range of applications including AI algorithm computation. 
Arm and CoreSight are registered trademarks or trademarks of Arm Limited (or its subsidiaries) in the US and/or elsewhere.

21G1 One Slider - Connect.png

**Enabling more choice for Next-Generation Heterogeneous Compute Platforms**

I am excited to see Intel's new [Foundry services business](https://newsroom.intel.com/news-releases/idm-manufacturing-innovation-product-leadership/#gs.wf5uq2) (IFS) in the U.S. and Europe increase the opportunity and choice for the semiconductor industry. We’re pleased to see Intel recognize the utility and opportunity for the RISC-V instruction set architecture in partnering to enable SiFive’s industry-leading Core IP portfolio to enable a new wave of leading-edge technology. 

SiFive is the leading provider of processor cores, accelerators, and SoC IP that technology companies will license to create workload-focused platforms based on the free and open RISC-V specification. While hyperscale computing requirements are increasing and being augmented by decentralized edge datacenters and endpoint on-device processing, the need for IP to power configurable platforms is growing stronger every day. The advantages of SiFive Core IP and the newly added choice of IFS' new business services and leading-edge high-performance capabilities enable our customers to develop these next-generation computing platforms. 

SiFive offers scalable, configurable, silicon-proven RISC-V processor cores pre-integrated with security, advanced trace, and debug features for workload-specific designs. SiFive’s industry-leading portfolio of processor IP scales from Linux-capable high-performance 64-bit multi-core clusters through to power and area-optimized real-time 64-bit and 32-bit cores. Chip designers can use SiFive’s pre-configured standard cores or configure cores optimized for their specific application using the award-winning SiFive Core Designer cloud-based tool. For mission-critical markets, SiFive’s Core IP supports deterministic operation, as described in this [technical paper](https://www.linleygroup.com/uploads/sifive-deterministic-processing-wp.pdf) (PDF) by semiconductor industry analyst, Linley Gwenapp. 

The RISC-V ecosystem is growing rapidly as more leading technology companies invest in RISC-V hardware and software development to secure their technology roadmaps and guide their own future product development. SiFive’s inclusion in the Intel Foundry Services business demonstrates the industry-wide support and adoption of RISC-V, especially in markets seeking high-performance, leading-edge technology. A wide range of software companies and developers are exploring the potential for RISC-V, which was recently demonstrated by running [AWS IoT Greengrass](https://pages.awscloud.com/embeddedworld21.html) on the SiFive HiFive Unmatched developer board, by Aicas. 

SiFive Core IP has been adopted worldwide and is available in products by leading technology companies including ArchiTek, BBC Learning, Coherent Logix, Innovium, FADU, Huami, MicroChip, Synaptics, Qualcomm, and Samsung. SiFive continues to develop new technologies for workload-focused platforms based on open standards to enable higher levels of performance, efficiency, and deeper vertical integration that will enable differentiated computing solutions. Last year, we unveiled the SiFive 20G1 release, and will soon announce the SiFive 21G1 release with new features and improvements as part of our continuous innovation program for our RISC-V IP portfolio. 

Learn more about SiFive processor IP [here](https://www.sifive.com/risc-v-core-ip), and more about the new Intel Foundry Services unit [here](https://www.intel.com/content/www/us/en/foundry/intel-foundry-services.html).

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SiFive collaborates with new Intel Foundry Services to enable innovative new RISC-V computing platforms

*SiFive RISC-V processors are powering flash drives in production as well as addressing emerging In-Storage Computing (ISC) needs*

In the current digital age, where data powers increasing levels of decision-making, industrial control and automation, efficient data storage, movement, and processing become the focal point of technological innovations in silicon, system, and software. At SiFive, we have been designing and optimizing RISC-V based domain-specific solutions to address the challenges of data-centric AI computing. Today, I’m thrilled to share some major progress we’ve made with our customers and partners in storage. 

Storage is always near and dear to the heart of RISC-V, with our good friend, Western Digital, being a strong believer, adopter, and promoter of the technology as well as playing a leadership role in RISC-V International. SiFive’s real-time processor cores had been adopted by storage leaders and innovators from very early on, and we continue to gain a strong foothold in this evolving market. More than 2 years ago in 2018, we announced that [FADU launched](https://www.sifive.com/press/fadu-launches-industry-leading-ssd-solutions-powered-by-sifive-risc-v-core-ip) industry-leading SSD solutions powered by SiFive RISC-V Core IP. SiFive’s S51 RISC-V core IP enabled FADU Annapurna controller with 64-bit processing capabilities at ultra-low power and greater efficiency, and according to FADU CEO Jihyo Lee, “SiFive’s RISC-V Core IP was 1/3 the power and 1/3 the area of competing solutions, and gave FADU the flexibility we needed in optimizing our architecture to achieve these groundbreaking products.” 

Fast-forward to Nov 2020, at the annual Flash Memory Summit (FMS), FADU announced its [second-generation RISC-V](https://fadutec.com/fadu-technology-announces-delta-ssd-gen4-platform-for-oem-and-hyperscale-data-center-storage/) powered DELTA SSD Gen4 Platform for OEM and hyperscale data center storage powered by SiFive’s S51 RISC-V core IP. FADU captured the honor of being awarded [Best of Show - Most Innovative Flash Memory Startup](https://fadutec.com/fadu-technology-awarded-best-of-show-most-innovative-flash-memory-startup-by-flash-memory-summit-2020/). We are thrilled that the deepened collaboration between FADU and SiFive came to fruition, and we congratulate the entire FADU team for their successful product launch as well as the well-deserved recognition. 

![](https://images.prismic.io/sifive/3af2974c-cab6-42dd-95a0-1a46ab41c6e4_fadussddelta.png?auto=compress,format)

The data-centric AI computing also inspired In-Storage Computing (ISC), another key trend in the storage industry that is aiming to enhance overall computing system efficiency by reducing movement of large amounts of data and processing the data where they are. SiFive has been working closely with InnoGrit Corporation, an emerging leader in advanced storage controllers and smart storage technologies, around leveraging SiFive 7-Series Core IP with both real-time and application processing capabilities as well as the unique SiFive Mix+Match technology to bring computing and intelligence closer to the storage device. The joint effort aims to produce solutions that can reduce I/O processing bottlenecks, enable faster decisions, and deliver more efficient storage utilization in data center and edge applications. 

When InnoGrit and SiFive set forth on this journey together to explore characteristics of storage domain specific processor architecture, we identified a few key features essential for ISC SoC design: 

1. The processor must act as a *responsive front-end processor* to handle essential flash control functions for read and write operations as well as Flash Translation Layer (FTL)
2. The processor also needs to have *application processing capabilities* with Linux support to run data analytics and other data manipulation tasks to increase the share of wallet for SSD controller and future-proof the product for ISC
3. The processor needs to have an *open and non-proprietary architecture* to reduce business risks and enhance product viability at a global scale 

After months of deep technical discussions and evaluation of SiFive’s portfolio of processor Core IP, it became obvious that SiFive’s 7 series RISC-V cores meets the above three requirements beautifully. 
1. SiFive’s E7 and S7 series of high-performance embedded processor cores can deliver low latency and real-time performance to enable fast and efficient data movement, as well as intelligent wear-leveling management to extend the life span and improve the reliability and durability of the SSD storage device.
2. SiFive’s U7 series of silicon-proven and power-efficient application processors can easily run Linux applications to enable various data processing, data analytics, and AI computation to execute within the storage devices itself. SiFive 7-Series Core IP is ideally suited for ISC with options of 32- or 64-bit processing in a silicon-proven package, including SiFive Insight advanced trace and debug, SiFive Shield security and hardware cryptographic accelerator, and integrated platform-level interrupt controller.
3. SiFive’s portfolio of processor Core IP has been built on one consistent, free, and open RISC-V instruction set architecture, invented by the SiFive founders 10 years ago. Development of the RISC-V ISA and extensions is governed by RISC-V International in open working groups composed of technology leaders and leading technology industry company representatives. 

When talking to Dr. Zining Wu, Co-Founder and CEO of InnoGrit Corporation, he told us, “InnoGrit is excited to work closely with SiFive, the leaders and inventors of RISC-V open-architecture, to bring intelligent data processing capabilities to storage devices for the AI Era of computing. We look forward to further integrating data computation and storage functions into InnoGrit ICs with SiFive’s silicon-proven 7 series processor IP that features real-time responsiveness and application workload processing capabilities.” 

Indeed, workload-focused platforms based on SiFive’s 7-Series RISC-V processor architecture enable higher-performance and more efficient data processing for data-centric computing from cloud to the edge. We will continue our technological collaboration with smart storage solution builders like InnoGrit and see RISC-V play an increasingly important role in storage technology evolution. 

Learn more about the latest SiFive 7-Series Core IP updates [here](https://www.sifive.com/blog/the-sifive-20g1-update-for-7-series-core-ip).

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SiFive Strengthens Foothold in Storage Applications for Data-Centric AI Computing

## Creating a RISC-V PC Ecosystem for Linux application development

Today, SiFive introduces the new HiFive platform for professional RISC-V developers, the HiFive Unmatched! The HiFive Unmatched enables developers to create the RISC-V-based software they need for RISC-V platforms. From real-time operating systems to custom Linux distributions, and the compilers, libraries, and applications that go with product design, developers can use the HiFive Unmatched to natively test and build RISC-V code. 

![SiFive HiFive Unmatched](https://images.prismic.io/sifive/22f77781-c477-44a0-950f-f14a099d8ad9_unmatched-board.png?auto=compress,format)

At the heart of the SiFive HiFive Unmatched board is the new SiFive FU740 SoC, a five-core heterogeneous, coherent processor with four SiFive U74 cores, and one SiFive S7 core. If you’ve been following SiFive for a while, you’ll know that the U-Series are SiFive’s Linux-capable 64-bit application processor cores, based on the RISC-V ISA that the founders of SiFive invented. SiFive S-Series cores are 64-bit real-time embedded cores designed to enable mission critical or deterministic processing. Combined in the SiFive FU740 using SiFive Mix+Match technology, the heterogeneous multicore complex offers a potent combination of application and real-time processing. You can learn more about the latest features and capabilities of SiFive 7-Series Core IP, [here](https://www.sifive.com/blog/the-sifive-20g1-update-for-7-series-core-ip). 

The SiFive HiFive Unmatched comes in the mini-ITX standard form factor to make it easy to build a RISC-V PC. For the first time, standard industry connectors such as ATX power supplies, PCI-Express(r) expansion, Gigabit Ethernet, and USB ports are present on a single-board RISC-V development system. 

The HiFive Unmatched includes 8GB of DDR4 memory, 32MB of QSPI flash memory, and a microSD card slot on the motherboard. For debugging and monitoring, developers can access the console output of the board through the built-in microUSB type-B connector. 

Expansion is simple with the onboard PCI-Express slots, including both a PCIe general purpose slot (PCIe Gen 3 x8) for graphics, FPGAs, or other accelerators; and, M.2 slots for NVME storage (PCIe Gen 3 x4) and Wi-Fi/Bluetooth modules (PCIe Gen 3 x1). Additionally, there are four USB 3.2 Gen 1 type A ports on the rear, next to the Gigabit Ethernet port, making it easy to connect your peripherals. 

The system will be shipped with a bootable SD card that includes Linux and popular system developer packages, with updates available for download from SiFive.com. From regression testing farms to individual developer contributions to the maturing RISC-V open software ecosystem, the SiFive HiFive Unmatched makes building exciting new applications and products more accessible than ever before. Priced at $665USD (suggested retail price), the system will be available for pre-order soon; please contact us [here](https://www.sifive.com/boards/hifive-unmatched) to register your interest.

HiFiveUnmatchedAnnouncement102920.png

The Heart of RISC-V Development is Unmatched

## Faster, More Efficient SiFive 7-Series Core IP

Today, we’re announcing the SiFive 20G1 6.0 update, which is focused on improving the 7-Series line of products. Our previous release, SiFive 20G1, was a comprehensive update that spanned from the 7-Series to the 2-Series, including U-, S-, and E-Cores. Similarly, the 20G1 6.0 update improves the performance, features, and functionality of SiFive 7-Series U-, S-, and E-Cores. 

Ever since the 7-Series [introduction](https://www.sifive.com/press/sifive-core-ip-7-series-creates-new-class-of-embedded) in 2018, SiFive has been able to bring advanced compute capabilities to embedded, industrial, and storage markets. These markets require high-performance compute in constrained thermal environments while being able to maintain real-time service guarantees. In addition, they also require access to stable software stacks providing functionality for Human Machine Interface (HMI), real-time control, and rich connectivity.

The SiFive 7-Series RISC-V processor cores can address all of these requirements. The 7-Series offers high-performance, multi-core compute, while still being extremely energy efficient. The 7-Series has many capabilities which make it suitable for real-time applications, and these real-time features apply across the 7-Series range: both the E7 and S7 Embedded cores as well as the U7 Application Cores. The 7-Series can scale to heterogeneous multi-core compute architectures via SiFive Mix+Match capabilities, allowing for a coherent mix of SiFive U- and S- cores in the same core complex complete with SiFive Insight Advanced Trace and Debug, SiFive Shield security, single 64-bit memory map, and interrupt controllers. These are all pre-integrated and verified in a single IP deliverable to save you time and engineering resources. And most importantly, the SiFive 7-Series is built on the open-source RISC-V ISA, bringing compatibility with the industry's fastest growing ecosystem. 

The 20G1 6.0 update builds on the improvements in the 20G1 release to enhance the capabilities of the 7-Series by further increasing performance and efficiency and adding features. Join Dany Nativel and me as we host a webinar showcasing these new improvements. We’ll also feature guest speaker, Jeff Hancock, a product manager at Mentor Graphics, who’ll talk about the latest Real-Time Operating System (RTOS) offering from Mentor, [Nucleus 4](https://www.mentor.com/embedded-software/nucleus/), which brings support for SiFive and RISC-V. He’ll also cover the importance of deterministic software and hardware for mission-critical markets.

[Register](https://www.sifive.com/resources/webinar/the-sifive-7-series-is-now-available-with-more-performance) for the webinar, and [sign up](https://info.sifive.com/sifive-newsletter-signup) for our newsletter to be notified of an new technical paper written by Linley Gwenapp, Principal Analyst for The Linley Group, on determinism and mission-critical applications.




The SiFive 20G1 Update for 7-Series Core IP

## A note from SiFive President & CEO, Patrick Little 

I’m honored to join SiFive to lead the brilliant, hard-working team of innovators and engineers who are responsible for creating some of the most impactful architectures in the technology industry. Ten years ago, an inspired team of computer scientists set out to invent a better way for hardware and software to talk to each other, free of legacy overhead and unencumbered by complexity, bringing the RISC-V Instruction Set Architecture to life. 

Five years later, encouraged by worldwide grassroots support, that same team launched SiFive and the RISC-V International organization, creating an inclusive and truly open business model for the technology industry to solve their computing challenges. RISC-V International is comprised of leading technology companies and scientists, enabling member companies and individual contributors to openly collaborate on the development and extension of the ISA. 

I’m just beginning to get to know the team and I’m immediately impressed by the passionate culture of SiFive, extending a warm welcome and demonstrating a rare energy of innovation and excellence that I’m excited to become a part of. Over the coming quarter, we’ll get to know each other better as we accelerate into the next phase of growth for the company, leveraging the inflection point that has coincided with my decision to join SiFive. 

**The Moment Is Now** 
Across the technology industry, a sharpened focus on workload-acceleration to solve next-generation computing challenges is driving demand for SiFive’s configurable RISC-V-based platforms. The industry wants choice in an open and free market that grants them control over their roadmaps, features, and partners; a choice that SiFive offers. 

I’m excited to see the increase in focus on SiFive’s industry-leading RISC-V-based portfolio. SiFive continues to drive the adoption of RISC-V for application and embedded designs, using our portfolio of configurable RISC-V-based microarchitectures with unique features such as pre-integrated security and advanced trace and debug capabilities, and the ability to mix and match cores in a heterogenous complex. We support this with a software and tool package to create a platform our customers can use to drive their own success. 

**Investing In The Roadmap** 
We’ll also continue to work hard on bringing our next-generation processor architectures to market, including the upcoming SiFive Intelligence processor architecture that tightly integrates vector capabilities into the scalar processor core. This tightly-integrated core, using a single ISA, enables a range of solutions for intense computational challenges, from deep learning in the data center to image, video, or audio processing at the edge. 

We’ll have more details on this at the Linley Group Fall Virtual Processor Conference, where Dr. Krste Asanovic, RISC-V co-inventor, SiFive co-founder and Chief Architect, will give a deep dive on the platform. 

To further enable professional developers, SiFive will launch a new HiFive board this year, to stand alongside the [Microchip PolarFire SoC](https://www.crowdsupply.com/microchip/polarfire-soc-icicle-kit) for developing RISC-V applications and solutions. The new SiFive HiFive board will be based on the upcoming SiFive FU740 SoC, details of which Dr. Yunsup Lee, RISC-V co-inventor, SiFive co-founder and Chief Technology Officer, will present at the Linley Group Fall Virtual Processor Conference. You can learn more about SiFive's presence at the conference [here](https://www.sifive.com/press/sifive-to-introduce-new-risc-v-processor-architecture). 

**What’s Your RISC-V Strategy?** 
Across the industry, technology and semiconductor companies are constantly evaluating the best new platform choice for their next-generation products. SiFive’s industry-leading RISC-V technology portfolio, combined with the talent and passion of this team, provides what we need to enable solutions for the workload-focused challenges of our customers to be successful. 

SiFive has consistently had a wide range of market opportunities and that is true now more than ever. We’re ready to work hard, identify the best customer opportunities, and build the products that will enable the most amazing new experiences in the industry. Let’s go change the world, SiFive!!! 

- Patrick

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## Building a secure foundation using the concept of randomness seems, on the surface, counter-intuitive.

As an aspect of entropy, randomness enables the generation of cryptographic methods to protect data, chips, and systems. By harnessing the nature of randomness as the basis of a secure system, it is possible to enhance the security of computer systems and protect vital information. 

In July, SiFive introduced the SiFive Shield hardware cryptographic accelerator (HCA), as part of the improvements contained in the SiFive 20G1 release. The SiFive Shield HCA block consists of the necessary elements to accelerate cryptography to securely boot an SoC, protect communications, and restrict access to the debug interface. 

I’m pleased to share with you that the SiFive HCA IP block includes a 100% digital true random number generator (TRNG) that has successfully passed a conformance evaluation against the stringent NIST SP-800-90B recommendation for entropy sources used for random bit generation. 

The SiFive HCA TRNG is a fully-digital IP block that offers customization options for the entropy source, including customization of the entropy rate. SiFive’s selected independent partner, 
Penumbra Security, Inc. (Penumbra) is a NVLAP-accredited Cryptographic and Security Testing laboratory under the Cryptographic Module Validation Program (CMVP) at National Institute of Standards and Technology (NIST). 

Happily, Penumbra asserts that SiFive’s method of customizing the entropy rate is effective, and demonstrated targeted entropy rates between 64.9% entropy and 92.4% entropy with the predicted entropy rates aligning with the actual entropy rates. Once integrated, the TRNG can be evaluated and certified against NIST SP-800-90C standard since through an additional SP-800-90A conditioning step enabled via SiFive software library that leverages the SiFive HCA hardware SHA/AES. 

The SiFive HCA block can be added into SiFive RISC-V processor cores, alongside other SiFive Shield components such as SiFive WorldGuard. SiFive WorldGuard enables true multi-domain security with multiple hardware enforced domains available for securely processing data across the whole SoC, even in multi-core designs with many primary bus controllers. SiFive Shield is portable and scalable with broad process technology support to ensure consistency over time. 

The SiFive 20G1 release with SiFive HCA block is available now. You can read more about the SiFive 20G1 release in our blog, [here](https://www.sifive.com/blog/sifive-core-ip-20g1).

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Randomness is Secure with SiFive Shield HCA

## The RISC-V Vector extension (RVV) enables processor cores based on the RISC-V instruction set architecture to process data arrays, alongside traditional scalar operations to accelerate the computation of single instruction streams on large data sets. 

The RISC-V International vector working group is composed of experts from industry and academia, to create a standard extension that can be ratified for general adoption among any who choose to adopt RVV. 

We’re incredibly pleased to announce that a team from SiFive and the Barcelona Supercomputing Center have collaborated to create a new API to support RISC-V Vector Intrinsics in popular compilers, GCC and LLVM. The API is available now on GitHub, [here](https://github.com/riscv/rvv-intrinsic-doc). 

As RISC-V continues to work towards ratification of the final version of the RISC-V Vector Extension, support will continue to be updated and added to create an industry-wide tool chain to enable widespread adoption of vector processing based on RISC-V. 

We have implemented the majority of the API in GCC to validate the currently proposed 1.0 specification. In addition to the RISC-V Vector specification, we have also implemented support for scalar and vector FP16 (Zfh), atomics (Zvamo), and segmented load/store (Zvlsseg) intrinsics. Full support of the currently proposed 1.0 specification has been implemented in the assembler. 

The team has integrated RVV intrinsics into risc-gnu-toolchain, so you can build the intrinsic enabled GNU toolchain as usual. We’ve also verified using our internal test suite and a few internal projects. We have extensively tested the intrinsics and our teams have used the intrinsics to implement different vector algorithms to help validate the vector implementation. 

In the near future, RISC-V Vector intrinsics will be implemented in the LLVM compiler and the work will be submitted upstream. This announcement also serves as a call-to-arms for the RISC-V community, to review and assist as we update the current implementation to the latest RISC-V Vector 1.0 draft specification. 

The hardware and software teams at SiFive are hard at work on SiFive Intelligence, our range of processor IP featuring RISC-V cores with vector capabilities. We’ll have more details on these cores later this year. Until then, we’re excited for the progress being made on building the ecosystem for converged processor cores that include scalable vector capabilities, to help design the domain-specific computing solutions needed for today’s computing challenges. 

Domain-specific architectures based on open standards enable deeper levels of performance, efficiency, and vertical integration to provide differentiated computing solutions. The focus of SiFive IP business unit is creating incredible processor core architectures that take a step forward from general purpose CPUs and GPUs housed together in a system, to a deeper level of compute convergence. The industry-wide interest and support for RISC-V Vector extensions is a great indicator of the potential of SiFive Intelligence. 

You can learn more about SiFive Intelligence in this [video presentation](https://riscv.org/2020/05/sifive-the-direction-and-magnitude-of-sifive-intelligence-nick-knight-the-linley-group/) from the Linley Group Spring Processor Conference - it'll be a great reminder ahead of the next set of details we unveil, later this year.

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RISC-V Vector Extension Intrinsic Support

## OpenFive is a solution-centric and processor agnostic custom silicon business unit dedicated to building optimized domain-specific SoCs

Today, I am excited to announce the launch of OpenFive, a self-contained and autonomous custom silicon business unit of SiFive, Inc. OpenFive is solution-centric and uniquely positioned to design processor agnostic SoCs and deliver high-quality silicon. 

![OpenFive Custom Silicon Business Unit](https://images.prismic.io/sifive/1881cd91-fe60-4f34-acd8-af7b37a3c13a_Openfive.png?auto=compress,format)

The demand for domain-specific silicon and workload-focused architecture is driven by several key factors. General purpose processors used to be the workhorses for the majority of computing tasks. With transistor cost increasing, and the end of [Dennard scaling](https://ieeexplore.ieee.org/document/9162812), general purpose processors have become very power hungry and performance increases are hard to find from process technology alone - architecture plays a key role in workload acceleration. 

We’re not alone in seeing this opportunity, as leading technology companies are embracing domain-specific accelerators targeted for applications such as AI training/inference, network virtualization and computational storage. Domain-specific or workload-focused silicon enable the cost-effective, scalable products desired by technology companies who want to own their roadmap and vertically integrate their products with hardware and software IP. 

OpenFive is built around a balance of silicon expertise and customizable IP, including a focused portfolio of SoC IP to enable key design features. OpenFive’s advanced design methodologies enable the use of leading edge foundry nodes, including 5nm, with 2.5D packaging technology, to build Artificial Intelligence, Edge Computing, HPC, and Networking solutions. 

The OpenFive IP portfolio includes low-latency, high-throughput Interlaken connectivity fabric, 400/800G Ethernet, High-bandwidth memory (HBM2/E), USB subsystem IP, and die-to-die interconnect IP for next-generation heterogeneous chiplet-style products. OpenFive’s broad industry expertise enables us to develop SoCs with a variety of processor cores, including RISC-V ISA as well as processors from Arm, Cadence, CEVA, and Synopsys. 

This ISA-agnostic and open approach will help accelerate the adoption of RISC-V in new designs, as chip designers look for the best IP for each functional block inside their SoC designs. The open, free RISC-V ISA is the basis for the SiFive Core IP portfolio - the broadest in the industry. SiFive cores, along with other RISC-V based cores, and cores from other ISAs, can make a heterogeneous mix of application, embedded, and microcontrollers to enable a modern domain-specific design. 

We’re incredibly excited about the opportunity that domain-specific silicon offers OpenFive customers in their next-generation products. With a heritage and expertise spanning more than 15 years, over 150M units shipped, and more than 350 tape-outs, OpenFive’s end-to-end expertise in Architecture, Design Implementation, Software, Silicon Validation and Manufacturing enable the design and delivery of high-quality silicon, with first-time-right results. 

For more information on the portfolio of IP and silicon solutions OpenFive can provide for your new vertically-integrated, differentiated design project, please connect with us [here](https://www.openfive.com). 

*All trademarks referenced herein belong to their respective companies.*

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OpenFive's Customizable Silicon-Focused Solutions

## SiFive's Best Processor Portfolio Is Here

We’re pleased to announce a comprehensive update to SiFive’s RISC-V IP Portfolio with the SiFive 20G1 release. This release brings important enhancements and new capabilities to SiFive Core IP, the industry's broadest RISC-V IP Portfolio, ranging from the ultra-capable SiFive U7-Series to the extremely popular SiFive E2-Series, offering up to 2.8x more performance(1); up to 25% lower power(2); and up to 11% smaller area(3). 

## Setting the Standard for RISC-V Cores

SiFive offers processor cores based on the free and open RISC-V ISA - after all, SiFive was founded by the inventors of RISC-V. The mission of SiFive is to enable the development of domain-specific silicon, and market feedback combined with SiFive customer experience tells us that a processor core must include all of the necessary components to integrate, secure, and develop software for the CPU core - [SiFive Shield](https://www.sifive.com/blog/sifive-shield-an-open-scalable-platform-architecture), and [SiFive Insight](https://www.sifive.com/soc-ip/sifive-insight). 


## Accelerating Product Development

SiFive Insight is the industry’s first pre-integrated debug and trace IP for RISC-V processor cores, enabling faster silicon bring-up, software/hardware integration, and application development. 

Uniquely, SiFive Insight features native Arm® CoreSight™ compatibility. By seamlessly integrating with Arm® CoreSight™, developers can integrate SiFive RISC-V based cores into mixed ISA designs and maintain their existing development environment. SiFive Insight has broad industry support from leading software companies such as [Green Hills Software](https://www.ghs.com/news/20200602_RISC-V_tools_support.html), [IAR Systems](https://www.iar.com/about-us/newsroom/press/?releaseId=3702222), [Lauterbach](https://www.lauterbach.com/frames.html?home.html), [SEGGER](https://www.segger.com/news/segger-announces-comprehensive-support-for-sifive-insight-debugtrace-platform/), with [SiFive Freedom Studio](https://www.sifive.com/boards) free tools also available. 

## High-Performance, High-Efficiency Processor Cores 

There are several key enhancements to SiFive Core IP in the SiFive 20G1 release to improve power, performance, and area (PPA). Enhancements to the high-performance U7-Series application processor have reduced power consumption by more than 25%(2), while increasing load bandwidth up to 2.8x for streaming data applications such as those in AI Acceleration applications(1). 

![SiFive Core IP 20G1 Update PPA vs 19.08](https://images.prismic.io/sifive/fdd45650-2fa9-447d-ab1a-308b16eebf70_072220-SiFive-CoreIP-20G1-PPA-Blog.png?auto=compress,format)

The SiFive E3- and E7-Series are now available with the RISC-V “Embedded” extension, RV32E, delivering an area reduction of up to 11%(3) compared to RV32I to further improve PPA for these cores. Based on customer feedback, RV32E will be a very popular option for product designers who need area-constrained high-performance embedded CPUs. The SiFive 3-, 5-, and 7-Series cores have been refreshed with new, enhanced real-time capabilities, bringing deterministic performance for high-reliability designs to SiFive’s winning product portfolio. 

SiFive’s advanced platform engineering expertise enables our roadmap development to be quickly integrated and validated on FPGAs to rapidly test improvements and new features of our product line. SiFive includes FPGA bitstreams in customer packages to enable high-performance software-development platforms, now including the [VCU118](https://www.xilinx.com/products/boards-and-kits/vcu118.html) based on the Xilinx UltraScale+ family of FPGAs, offering a software development platform for the entire SiFive Core IP portfolio including large multi-core configurations. 

## Processor Optimization 

The [award-winning](https://www.elektraawards.co.uk/elektraawards2020/en/page/2019-winners) [SiFive Core Designer](https://www.sifive.com/core-designer) cloud-based development application for configuring your own processor core ties the SiFive 20G1 release together, making SiFive Core IP simple and easy to work with. In the SiFive 20G1 release, we adopt a new version scheme by moving from “year/month” naming to “year/release.” The SiFive 20G1 release is the first General Release of 2020, and encapsulates 9 months of hard work and progress at SiFive as we move to a new release schedule driven by our roadmaps and aligned to customer engineering cycles. SiFive Core Designer allows chip-designers to fine-tune a SiFive processor to meet their workload requirements, selecting which features and functionality are required. 

## Building Secure SoCs

SiFive Shield, an open, scalable platform architecture designed to enable whole SoC security for RISC-V, is pre-integrated into SiFive Core IP and configured via SiFive Core Designer. Freshly added in the SiFive 20G1 release is support for the SiFive Shield Hardware Cryptographic Accelerator (HCA) IP add-on option. 
SiFive HCA IP offers a configurable mix of AES, SHA, and TRNG functions to enable secure Root of Trust and hardware-accelerated cryptographic functions. SiFive Shield HCA is configured using SiFive Core Designer and is pre-integrated and verified along with SiFive Core IP deliverables, including accompanying documentation, software, and drivers. 

## Making Great Applications

In software discussions, one of the first questions we get asked is about the FreeRTOS™ real-time operating system. FreeRTOS support for RISC-V was integrated into the official FreeRTOS releases in early 2019, and the SiFive Freedom E SDK now includes FreeRTOS v.10, with source code and build scripts integrated into the SDK. Alongside the FreeRTOS kernel, the SiFive Freedom E SDK features several FreeRTOS-based examples, including using Physical Memory Protection (PMP) to enable secure runtime operations. 

The SiFive Freedom E SDK board support packages (BSP) have been upgraded to include System View Description (SVD) files, bringing tighter integration into debug environments. 

![SiFive Freedom Studio](https://images.prismic.io/sifive/407ea7f6-8469-4952-9a91-af5595089668_sifive-insight-traceview.png?auto=compress,format)

[SiFive Freedom Studio](https://www.sifive.com/boards) enables faster development of new products through enhanced support for SiFive Insight Advanced Trace and Debug including new views of trace flow to speed up debugging.

## SiFive’s Best Portfolio Is Here

The SiFive 20G1 release offers impressive PPA improvements combined with new pre-integrated SiFive Insight trace and debug to save time and effort with SiFive’s unique support for Arm® CoreSight™ to minimize workflow disruption, and broad tool ecosystem support. Defining and adopting a high-performance, high-efficiency, secure RISC-V processor using SiFive Shield security features and add-on options for your next application or real-time SoC has never been more attractive with SiFive. 

We can’t wait to engage with customers on the incredible new devices they’ll build using the substantial new capabilities of the faster, more efficient, more capable than ever SiFive Core IP portfolio. 

Please [contact us](https://www.sifive.com/contact-sales) if you would like to learn more about the SiFive 20G1 release directly from the team. 

**Footnotes 
(1) – 2.8x higher performance based on SiFive internal engineering measurement of improving performance in memory-intensive workloads running on a SiFive U7-Series processor core; when normalized the SiFive U7-Series processor (19.08) offers 36% of the performance of the SiFive U7-Series processor (20G1). 
(2) – 25% lower power based on SiFive internal engineering measurement of SiFive U74 processor (20G1) core power consumed while running Dhrystone benchmark as compared to SiFive U74 processor (19.08); when normalized the SiFive U74 (19.08) processor offers 133% of the power consumption of the SiFive U74 (20G1) processor. 
(3) – 11% area reduction based on SiFive internal engineering measurement of SiFive E3-Series area using RISC-V Embedded extension RV32E in 28nm process technology vs. RV32I; when normalized the SiFive E3-Series (19.08) measures 112% larger area of the SiFive E3-Series (20G1), using 28nm process technology. 
Arm and CoreSight are registered trademarks or trademarks of Arm Limited (or its subsidiaries) in the US and/or elsewhere.

072220-SiFive-CoreIP-20G1-PPA-LI.png

## A Message From The CEO

Innovation in SiFive’s product portfolio and business model differentiates our company, but the employee team is the heart of our success. SiFive employees enable our company to offer the full idea-to-silicon journey, from configurable processor cores with comprehensive pre-integrated security, trace and debug capabilities, and modern SoC IP, to scalable chip manufacturing development and management using a broad range of foundries and process technologies. 
 
To support the areas that SiFive employees live in, we will be making charitable donations to local communities around our design centers. We value our employee’s health and safety, and our commitment to keeping them and their families safe during this time is a top priority. 

Recently, SiFive announced our participation in the [COVID-19 pledge](https://opencovidpledge.org/), and we now offer the [SiFive E21](https://www.sifive.com/cores/e21) processor core IP [free](https://opencovidpledge.org/license/v1-0/)* to help those creating solutions to healthcare issues created by the pandemic. We encourage our partners and customers to continue to find ways to positively contribute to potential solutions for the challenges caused by COVID-19. For more information on using the SiFive E21 standard core IP in a design under the terms of the COVI-19 pledge, please contact our [sales team](https://www.sifive.com/contact-sales). 

SiFive’s mission is to make the idea-to-silicon journey easier, helping startups and established companies alike to solve the computing challenges they face. To achieve this goal, SiFive focuses on offering excellence, engineering, and expertise to enable customer domain-specific silicon. This focus was a key element in my decision to join SiFive, guiding and growing operations and programs to develop innovative solutions for computing challenges. 

A key element in this approach is SiFive’s innovative processor IP and scalable platform engineering methodology combined with a forward-thinking business model. SiFive was founded on the principle of using open standards to develop efficient, high-performance, SoCs with methodologies based on scalable reuse. To that end, SiFive offers a licensing and use model that does not require upfront IP licensing costs. Industry partners have joined in this model through SiFive’s [DesignShare](https://www.sifive.com/designshare) program. 

With flexible support and engineering engagement available to support customer core and silicon development, SiFive’s approach enabled scaling to a global presence quickly. SiFive’s sixteen design centers around the globe coupled with decentralized infrastructure and web-based products such as SiFive Core Designer continue to deliver on our customer commitments. 

Keep in touch with SiFive via our social media channels to follow the latest developments as we continue to support our local communities, create great technology, and free semiconductor roadmaps. 


* *The SiFive E21 Standard Core is offered under the [Open COVID license 1.0](https://opencovidpledge.org/license/v1-0/).

message-from-CEO.jpg

Published by [SemiWiki](https://semiwiki.com/ip/sifive/285092-sifives-approach-to-embedding-intelligence-everywhere/).


Before the advent of RISC-V, designers looking for embedded processors were effectively limited to a handful of proprietary processors using ISAs from decades ago. While the major ISAs are being updated and enhanced, they also are facing limitations from many decisions made over many years.  RISC-V was conceived with a clean well-thought-out architecture and designed for expansion that would not create inconsistencies. Because it is open source, there is a rich set of tools and products that support it.

SiFive is one of the leading exponents of RISC-V and has been producing IP based on the RISC-V ISA for years now. Their product offerings have expanded significantly, now addressing everything from edge/IoT to server applications. Their recent webinar titled “Embedding Intelligence Everywhere with SiFive 7 Series Core IP” talks about how intelligence is needed in each market.

![Embedding Intelligence Everywhere](https://images.prismic.io/sifive/11123394-15b6-406a-bad5-c6483df27170_embedding-intelligence-everywhere-blog.jpg?auto=compress,format)

The webinar is divided into two parts. The first, presented by Jack Kang, Senior Vice President of Customer Experience at SiFive, offers a look at how embedded intelligence is becoming prevalent everywhere from the cloud to the edge. He also offers an overview of SiFive’s embedded RISC processors and how they fit current market needs.

Jack first talks about how AI is moving from the cloud to the edge, creating the need for additional processing capabilities in a wide range of devices. At the edge AR, VR and sensor fusion are driving the need for expanded real time processing. Jack also points out that there is also a need for increased intelligence in storage. He touches on how intelligence is supporting caching schemes, cryptography, memory maps and even in-cluster application processors. Likewise, making networking smarter facilitates higher bandwidth and other activities such as the implementation of 5G stacks.

The cores offered by SiFive are grouped by their application areas. The E Cores are suitable for 32-bit embedded uses. For heavier workloads there are the S Cores, which add 64 bit capabilities. The most powerful processors are the U Cores, which are 64-bit application processors for high-end computing.

Their smallest and most efficient RISC-V processor IP is the 2 Series, the E2 and S2, which are 32 and 64 bit respectively. They are core and memory configurable to customer specific needs. They also feature ultra-low latency interrupts for servicing real world events.

The 3 and 5 Series are their most widely deployed products. The E3 offers 32 bit performance for mid-range embedded applications. The S5 adds 64 bit and the U5 is the top end offering higher performance. These cores can be used in multicore configurations and have Hard Real Time capabilities.

The 7 Series cores are the topic of the later second section of the webinar. Jack touches on them before talking about the U8, an extremely scalable high performance out-of-order core with their highest performance per watt. The U8 is also very area efficient. The combination of area and power efficiency make them very attractive for high end computing systems.

The second section, presented by Jahoor Vohra, Director of Field Application Engineering, is titled “SiFive 7 Series Core IP”. His presentation discusses the features of the three members of the Core IP 7 Series: E7, S7 and U7. This includes an overview of the 7 Series microarchitecture, focusing on performance, scalability and the detailed specifications of each.

The 7 Series are scalable up to 8+1 for each cluster. Like other RISC-V processors the instruction set is extensible through custom instructions. Their memory is configurable and tightly integrated for low latency. If called for, they support mixed precision arithmetic. They also feature enhanced determinism to better support demanding real time applications. There are also functional safety features provided by built-in fault tolerance mechanisms. These are just a few of the highlights that Jahoor brings up.

To gain a full appreciation and understanding of the SiFive offerings, across the board and about the 7 Series in particular, I highly suggest viewing the [informative webinar](https://www.sifive.com/resources/webinar/embedding-intelligence-everywhere-with-sifive-7-series). I have been following RISC-V and SiFive for a number of years now. The level of adoption and progress has been extraordinary. The entire effort is supported by some brilliant dedicated minds. The results speak for themselves.

SiFive is also giving a webinar soon on the topic of Rapid Embedded Prototyping with SiFive Software [see details](https://info.sifive.com/rapid-embedded-prototyping-with-sifive-software). These webinars are all part of the SiFive Connect webinar series, which aims to provide educational content in an interactive format. A full list of these webinars can be found [here](https://www.sifive.com/resources/webinars).


SiFive’s Approach to Embedding Intelligence Everywhere

A Platform Designed for Continued Engagement with the Global Hardware and Software Community Developing RISC-V Based Semiconductor Solutions.

After hosting the SiFive Tech Symposiums in a record 52 cities in 2019, it became amply evident that the RISC-V revolution has reached all corners of the globe and is here to stay. RISC-V cores are being designed into many SoCs and domain-specific custom silicon. To take our previous engagement with the global community to the next level, we’re launching the SiFive Connect Webinar Series as a highly educational and interactive platform for SoC developers to connect directly, on an ongoing basis, with industry experts. Targeted for engineers, architects, developers, researchers and students, attendees will learn about the RISC-V ecosystem and the latest RISC-V based cores and software, security solutions, SoC and system IP, various end market solutions and development platforms. 

These bimonthly webinars will be one hour in duration, and each will take place twice on the same day – once at 9 a.m. PDT and again at 6 p.m. PDT – enabling the global community to choose the time that works best for them.

Registration is now open for the first two SiFive Connect webinars of 2020!
- Thursday, April 16, 2020 
![Embedding Intelligence Everywhere](https://images.prismic.io/sifive/02667a10-9df0-478c-9099-7451cbe31b8d_embedding-intelligence-blog-photo.jpg?auto=compress,format)
Embedding Intelligence Everywhere with SiFive 7 Series Core IP 
[View Abstract & Register to Attend](https://info.sifive.com/embedding-intelligence-everywhere-with-sifive-7-series-core-ip)

- Thursday, April 30, 2020 
![Rapid Embedded Prototyping with SiFive Software](https://images.prismic.io/sifive/8ced59ef-f22b-4e4a-8aa4-66ee6260d127_rapid-embedded-prototyping-blog-photo.jpg?auto=compress,format)
Rapid Embedded Prototyping with SiFive Software 
[View Abstract & Register to Attend](https://info.sifive.com/rapid-embedded-prototyping-with-sifive-software)

To view an extended list of upcoming topics, please visit [www.sifive.com/resources/webinars](https://www.sifive.com/resources/webinars).

We look forward to engaging with you and sharing knowledge!

SiFive Connect : SiFive in Virtual World-Webinar Series

## The SiFive Mission

SiFive’s mission is to accelerate chip design, closing the time between the definition of a chip to silicon being available - we call this the ‘idea to silicon' journey. The solutions to modern computing challenges increasingly require domain-specific accelerators, silicon chips designed to solve a focused problem with built-in adaptability to provide flexibility for shifting workloads. 

![](https://images.prismic.io/sifive/09ae0aeb-c69f-4a46-871d-02ef15936a07_SiFiveIdeaToSiliconsm.png?auto=compress,format)
Today, [Synopsys announced](https://news.synopsys.com/2020-03-25-SiFive-Selects-Synopsys-Fusion-Design-Platform-and-Verification-Continuum-Platform-to-Enable-Rapid-SoC-Design) that SiFive has selected Synopsys Fusion Design Platform™ and Verification Continuum™ to further enable SiFive’s vision of rapid cloud-based design. SiFive will leverage Microsoft Azure to power our portfolio of design tools, enabling [SiFive platform engineering](https://www.sifive.com/blog/with-sifive-we-can-change-the-world) to continue to scale and deliver high-quality IP and solutions for customer challenges. 

With 16 design centers across the globe, SiFive leverages global collaboration tools to complete our work. And where those tools don’t exist, or need to be more efficient, [we build them](https://www.youtube.com/watch?v=L7L2r4Tp2J0). Scalable chip design can be abstracted to a compiler and language problem, once you have established the parameters for interfaces on your SoC IP building blocks. With pre-integrated IP, scalable building blocks, and the power of cloud-based tools, silicon at the speed of software becomes a reality. 

One popular example accelerator is machine learning inference; different inference processing models have different hardware design requirements. The market for deep learning accelerators is growing, as the global deep learning market is [expected to grow](https://www.globenewswire.com/en/news-release/2020/01/27/1975409/0/en/Deep-Learning-Market-Size-Worth-US-56-427-2-Mn-By-2026.html) at a CAGR of 51.1%, reaching a market value of over $56B US by 2026. Further [forecasts show IoT growth](https://www.gartner.com/en/newsroom/press-releases/2018-11-07-gartner-identifies-top-10-strategic-iot-technologies-and-trends) reaching 25 billion devices by 2021 from the 2019 level of 14.2 billion. To reduce anticipated network pressure, data can be processed and decisions made at the edge or endpoint device. 

On-device decisions drive new design requirements for the core, cache, memory, and processing offload accelerators used inside the silicon. An agile, scalable, programmatic approach to SoC design is required to create domain-specific accelerators and bring them to market quickly. 

SiFive Core IP enables processor cores to be generated, based on standard core definitions in our product range with configurable options. [SiFive Core Designer](https://www.sifive.com/core-designer) is an [award-winning](https://www.elektraawards.co.uk/elektraawards2019/en/page/2019-winners) web-based tool for silicon engineers to quickly configure SiFive RISC-V based cores, leveraging the broad SiFive Core IP portfolio. This is enabled through the use of programmatic techniques for integrating IP and creating core derivatives using generators. In 2018, we proved the efficacy of the solution by using these techniques and tools to create an SoC in just 6 months, from concept to booting Linux. 

Using a fully cloud-based methodology, SiFive [taped out](https://www.design-reuse.com/news/44851/tsmc-oip-ecosystem-enabled-in-the-cloud.html) the SiFive Freedom Unleashed FU540 64-bit RISC-V Linux chip and presented the results at the 2019 Design Automation Conference in Las Vegas. The SoC features a SiFive U54 multicore complex plus interconnects for accelerators, high-speed I/O, and DDR3/4 memory. 

The next level is the ability to rapidly enable new designs focused on domain-specific workloads. Shubu Mukherjee, SiFive Chief SoC Architect published a blog series on domain-specific accelerator (DSA) designs with SiFive RISC-V-based SoCs([1](https://www.sifive.com/blog/part-1-fast-access-to-accelerators-enabling-optimized-data-transfer-with-risc-v),[2](https://www.sifive.com/blog/part-2-high-bandwidth-core-access-to-accelerators-enabling-optimized-data-transfers-with-risc-v),[3](https://www.sifive.com/blog/part-3-high-bandwidth-accelerator-access-to-memory-enabling-optimized-data-transfers-with-risc-v),[4](https://www.sifive.com/blog/part-4-high-performance-interconnect-for-accelerators-enabling-optimized-data-transfers-with-risc-v)). Achieving rapid DSA enablement requires scaling the programmatic approach to core design to the whole SoC, leveraging high-quality cloud-based tools. 

SiFive’s mission is to reduce the time, complexity and cost of custom silicon for people trying to solve today’s computing challenges. Today, we continue to scale our enablement of the idea to silicon process that will drive silicon at the speed of software. With SiFive, you can unleash your roadmap and declare silicon independence.

SiFiveIdeaToSilicon.png

## Access, Observe, Control

The term ‘debug’ has a storied history. It’s [widely reported](https://www.computerworld.com/article/2515435/moth-in-the-machine--debugging-the-origins-of--bug-.html) as being coined by computing pioneer, US Navy Rear Admiral Grace Hopper, when she removed a moth from Harvard’s Mark II computer in 1945. Use of the word bug can also be traced to the great inventor, Thomas Edison, from a letter he wrote in 1878. Whatever the origin, we all agree that we don’t want bugs in our systems, our hardware, our code. 

With computer systems long past the size where physical inspection is feasible, and programming using wires or punch cards long gone, we need new methods. We need insight into the machine, the code, the operations happening millions of times per second right in front of us to create high-quality products, accurately and quickly. 

*An Industry Leading RISC-V Trace & Debug Portfolio* 

Today, SiFive are pleased to announce [SiFive Insight](https://www.sifive.com/technology/sifive-insight), a portfolio of trace and debug IP, software, and tools, to make the development of new SiFive RISC-V products efficient and simple. Observing product operation is critical for developing secure, efficient systems. These trace and debug features allow access to system state information, and even modification, to better understand the system’s operational flow. 

![SiFive Insight Trace Operation](https://images.prismic.io/sifive/407ea7f6-8469-4952-9a91-af5595089668_sifive-insight-traceview.png?auto=compress,format)

The capability to trace processor instruction execution step-by-step, and examine the contents of debug logs gives us the abilities we need to observe, access, and control system operation during development. 

SiFive Insight is the first RISC-V core with pre-integrated debug and trace offering. SiFive Insight reduces complexity by offering a single-vendor solution that is lightweight and simple to integrate into SoC designs based on SiFive RISC-V processor Core IP. Uniquely, SiFive Insight supports Arm® Coresight™ to enable simple adoption and ease of use in a heterogenous SoC development environment. 

SiFive Insight is pre-integrated and verified in a single deliverable, to offer a range of debug and trace functions as standard. From run-control to advanced multi-core trace in a heterogeneous core complex, SiFive Insight can be easily configured using the [award-winning](https://www.elektraawards.co.uk/elektraawards2019/en/page/2019-winners) SiFive Core Designer to suit your needs. 

![SiFive Insight Core Designer Integration](https://images.prismic.io/sifive/0894b85b-23f3-4d9e-8ac8-752627e2e3d5_sifive-core-designer-insight.png?auto=compress,format)

All SiFive cores include the ability to be configured with up to 16 hardware triggers. Hardware triggers can stop the processor on the execution of an instruction or the read or write of a memory location. Furthermore, hardware triggers can be used to control trace collection. These triggers can be combined to support arbitrary ranges. In addition to core triggers, SiFive Insight supports a configurable number of external triggers allowing for external events to trigger a debug halt. 

SiFive Insight is compatible with [Nexus 5001™ trace](https://nexus5001.org/nexus-5001-forum-standard/) specification standards, and is fully supported by the SiFive Freedom Studio integrated developer environment (IDE). Compatibility with Nexus 5001™ trace also ensures compatibility with leading developer tools. SiFive cores support the recently ratified [RISC-V Processor Trace standard](https://riscv.org/2020/03/risc-v-foundation-announces-ratification-of-the-processor-trace-specification/). The RISC-V Foundation trace and debug working group is evaluating Nexus 5001™ trace as an additional standard to be ratified. SiFive works closely with our ecosystem partners to enable them with the latest SiFive Insight technology, ensuring that they are well-positioned to support application developers and chip designers. 

*[IAR Systems](https://www.iar.com/iar-embedded-workbench/)* 
![](https://images.prismic.io/sifive/7b100e2c-c4f1-4a71-924c-d28f055cafe4_iar_probe%26adapter_kit_2.jpg?auto=compress,format)
*[Lauterbach](https://www.lauterbach.com/frames.html?home.html)* 
![](https://images.prismic.io/sifive/8f898c81-4aee-443d-a5f0-9411fc238c1d_RISC-V_Nexus_trace_Lauterbach.png?auto=compress,format)
*[SEGGER](https://segger.com)* 
"SEGGER J-Link offers full support for the new SiFive Insight debug and trace IP, including the Nexus based trace implementation. With SEGGER J-Link the trace data can be read from on-chip memory, yielding back trace, execution counts, code profiling and code coverage information" - SEGGER Microcontroller GmbH
![](https://images.prismic.io/sifive/18ebdd7e-6fdd-417a-b9d7-f7ec8b630e2f_SEGGER-Jlink-Ozone-Debugger.png?auto=compress,format)

**Market Momentum** 
Industry analysts forecast [62.4 billion RISC-V cores](https://riscv.org/2019/11/9679/) will be deployed in the next 5 years. SiFive’s portfolio of products, tools, and expertise will ensure the development of your new market-focused product is secure, efficient, and free of bugs.

sifive-insight-bullets.png

As part of our ongoing effort to spread knowledge about the RISC-V ISA around the globe, we hosted a two-day long RISC-V Symposium/Workshop in the ancient city of Ahmedabad, India. The event was co-hosted by Nirma University at their campus at Ahmedabad.
 
The first day of the event was the symposium portion, and it was attended by students of various universities, research scholars, and many prominent industrial experts from Ahmedabad. Anand Bariya, VP of engineering at SiFive, delivered a keynote presentation that outlined the importance of the RISC-V ISA and SiFive’s role in advancing the open-source ecosystem. Another keynote was presented by Professor Usha Mehta of Nirma University, Ahmedabad, who spoke on the research activities currently taking place at the university. Rajesh Varadharajan, the director of IP engineering at SiFive, presented on RISC-V core IP for target vertical markets and software ecosystems, and also provided a tutorial on SiFive’s Core Designer. Approximately 160 people participated in the symposium.

The second day of this two-day event was a hands-on workshop where attendees were given the opportunity to practice what they learned on the previous day. All the participants were very enthusiastic to implement the RISC-V ISA and boot their program on an FPGA board. Approximately 130 people participated in the workshop, as the seats were limited.
The experience in Ahmedabad was very rewarding. The enthusiasm of the participants from various backgrounds made it a great success! We’re very thankful to the management and staff of Nirma University for their gracious support and for co-hosting the event!

For more information on these and our many other tech symposiums and workshops, please visit [www.sifivetechsymposium.com](https://www.sifivetechsymposium.com).
 
## Glimpses: Day-1:
![Glimpses Day 1](https://images.prismic.io/sifive/d7343270-2b16-498f-a1cd-9a643192e516_glimpses-day-1.png?auto=compress,format)
![Glimpses Day 1](https://images.prismic.io/sifive/e82e6e85-2c01-4ffa-a430-70a79ae3c546_glimpses-day-1a.png?auto=compress,format)
![Glimpses Day 1](https://images.prismic.io/sifive/18a138f5-ebef-4aec-a9ac-2fbb093171eb_glimpses-day-1c.png?auto=compress,format)
![Glimpses Day 1](https://images.prismic.io/sifive/74733ec9-eaf7-434e-81e8-dfe4d6bfbee3_glimpses-day-1b.png?auto=compress,format) 

## Glimpses: Day-2:
![Glimpses Day 2](https://images.prismic.io/sifive/7208f507-9d99-453c-bf71-5708b614c4e2_glimpses-day-2.png?auto=compress,format)
![Glimpses Day 2](https://images.prismic.io/sifive/0339e334-23a0-4dd3-a282-7c19579bca77_glimpses-day-2b.png?auto=compress,format)
![Glimpses Day 2](https://images.prismic.io/sifive/c588b393-86ca-471d-8ef5-72db71a1db7c_glimpses-day-2c.png?auto=compress,format)

The RISC-V Revolution is Going Strong in Ahmedabad

Our SiFive Tech Symposiums in San José, Costa Rica and Mexico City, Mexico were well attended by not only those in industry, but in academia as well. There is a great deal of enthusiasm and engagement in RISC-V in both of these regions. Many new friendships were formed, and we look forward to the continued networking and idea sharing that open source brings to the hardware community.

Western Digital co-hosted the symposium in Costa Rica, which was co-located with LASCAS 2020, the flagship conference of the IEEE Circuits and Systems Society in Latin America. Those who attended the presentations and participated in the hands-on workshop included folks from Intel, HP and Wind River, as well as graduate students and professors from Central and Latin American countries. One of the highlights was the keynote presentation by Gerardo Bertero, senior director at Western Digital, who spoke about memory architecture and how RISC-V is being used within Western Digital.

With the Computer Research Center at National Polytechnic University (CIC-IPN) as our co-host, the symposium in Mexico City drew over 70 attendees. This symposium was predominantly geared toward academia and was heavily attended by students and professors from a variety of disciplines. One of the highlights was the presentation by Professor Marco Ramirez Salinas who outlined the magnitude of RISC-V research taking place at the university. It was very impressive to hear about the university’s accomplishments with RISC-V. 

We’d like to offer our gratitude to both Western Digital and CIC-IPN for co-hosting these symposiums with us.

For more information on these and our many other tech symposiums and workshops, please visit [sifivetechsymposium.com](https://sifivetechsymposium.com/) 

## Snapshots 
![Costa Rica John Min-Feb-25-2020](https://images.prismic.io/sifive/7fa5064a-28c1-4fa9-a89c-427c11592cc4_costa-rica-john-min-feb-25-20.jpg?auto=compress,format)
![Costa Rica David Connelly-Feb-25-2020](https://images.prismic.io/sifive/e78996ae-0c42-4e8f-8399-672fe6575d78_costa-rica-david-connelly-feb-25-20.jpg?auto=compress,format)
![Mexico Workshop-2020](https://images.prismic.io/sifive/7beada70-ba68-40e8-b4d7-a52a885e9625_mexico-workshop-2020.jpg?auto=compress,format)
![Mexico Workshop-2020 v2](https://images.prismic.io/sifive/1e419d40-1790-4fb7-81b5-102d1530f379_mexico-workshop-2020-v2.jpg?auto=compress,format)
![Mexico Workshop-2020 v3](https://images.prismic.io/sifive/1349bab7-3fc6-4f54-a118-47aef6543c98_mexico-workshop-2020-v3.jpg?auto=compress,format)

Our SiFive Tech Symposiums in Costa Rica and Mexico Underscore the Global Adoption of the RISC-V ISA in Industry and Academia



This is the fourth in a series of blogs about Domain-specific accelerators (DSAs), which are becoming increasingly common in systems-on-chip (SoCs). Parts 1, 2 and 3 addressed key challenges such as data transfers between DSAs and the core complex, point-to-point ordering between cores and DSA memory, and data transfers between DSA and memories. This fourth instalment in the series will focus on the frequent interaction with and amongst cores, which is required by DSAs, and how the TileLink specification can be utilized to build interconnection networks. 

To recap, a DSA provides higher performance per watt by optimizing the specialized function it implements.  Examples of DSAs include compression/decompression units, random number generators and network packet processors.  A DSA is typically connected to the core complex using a standard IO interconnect, such as an AXI bus (Figure 1). 

![AXI Bus](https://images.prismic.io/sifive/22db71b5-55c6-45cf-8365-9b7ae7855e36_axi-bus-figure1-2.jpg?auto=compress,format)

SOCs based on RISC-V offer a unique opportunity to optimize data transfers between cores and DSAs.  Many high-performance DSAs require frequent interaction with and amongst cores.  Standard memory interconnects often are limited by how fast they can transfer data.  Such an interconnection can be designed to the TileLink specification [1], which is a free and open standard to build interconnection networks. 
  
Designing one’s own memory interconnection network offers several advantages to a DSA (Figure 2): 
- The DSA can connect to the memory interconnect to reduce latency of interaction with cores by directly participating in the memory coherence protocol. 
- The interconnect channel width can be optimized to the data transfer rates required by the DSA.  For example, one could envision extremely wide 1024-bit wide channels.  The interconnection channels can also be run at a higher frequency than what a standard interconnect might allow.
- The Last-Level Cache (LLC) can have bigger cache block sizes than the core caches.  For example, core caches typically have 64-byte blocks, whereas the LLC could be designed for 128-byte or 256-byte cache blocks. The LLC can also support special prefetch mechanisms optimized for the DSA. 
- The LLC and interconnect can offer different levels of QoS (Quality of Service).  These QoS levels can be used, for example, by the LLC controller, to offer lower latency and higher bandwidth to DSAs in the presence of cross-traffic from different applications.

[1] SiFive TileLink Specification, [tilelink spec 1.8.1 PDF](https://sifive.cdn.prismic.io/sifive/7bef6f5c-ed3a-4712-866a-1a2e0c6b7b13_tilelink_spec_1.8.1.pdf)

See more details about SiFive’s standard cores, or to customize and build domain-specific RISC-V cores, please visit [sifive.com/risc-v-core-ip](https://www.sifive.com/risc-v-core-ip)




Part 4: High-Performance Interconnect for Accelerators: Enabling Optimized Data Transfers with RISC-V



This is the third in a series of blogs about Domain-specific accelerators (DSAs), which are becoming increasingly common in system-on-chip (SoC) designs. Part #1 addressed the challenges associated with data transfers between DSAs and the core complex, and showed how RISC-V offers a unique opportunity to optimize fine-grain communication between them and improve core-DSA interaction performance. Part #2 addressed the challenges associated with point-to-point ordering between cores and DSA memory, and how RISC-V offers a unique opportunity to optimize high-bandwidth communication between cores and DSAs. This third installment will focus on the challenges associated with data transfers between DSA and memories, such as DDR, LPDDR or HBM, and explain how SoCs based on RISC-V can use an alternate approach to write the data directly to memory.

To recap, a DSA provides higher performance per watt by optimizing the specialized function it implements.  Examples of DSAs include compression/decompression units, random number generators and network packet processors.  A DSA is typically connected to the core complex using a standard IO interconnect, such as an AXI bus (Figure 1).

![High Banswidth Accelerator](https://images.prismic.io/sifive/83e22f95-0216-42ac-951e-145f1ec99cc1_high-bandwidth-accelerator.jpg?auto=compress,format)

SoCs based on RISC-V offer a unique opportunity to optimize high-bandwidth data transfers between a DSA and memory.  DSAs often need to transfer their data to memory, such as DDR, LPDDR or HBM memories.  Often this is accomplished using a DMA (Direct Memory Access) engine.  
 
The difficulty in the traditional approach (Figure 1) is that such data transfers often involve allocating the data in the Last-Level Cache first.  This can significantly slow down accesses, particularly if the volume of transferred data is greater than the size of the Last-Level Cache. 

Figure 2 shows that SoCs based on RISC-V can use an alternate approach where they can write the data directly to memory, bypassing the Last-Level Cache.  This can be achieved by marking the data being written as uncached. Alternatively, the DMA engine can provide a hint to the Last-Level Cache to not allocate the data in the Last-Level Cache, but to write directly to memory.  In this scenario, the data is still marked as cacheable, so any other cached copy of the data must be invalidated within the processor complex. 

See more details about SiFive’s standard cores, or to customize and build domain-specific RISC-V cores, please visit [sifive.com/risc-v-core-ip](https://www.sifive.com/risc-v-core-ip)



Part 3: High-Bandwidth Accelerator Access to Memory: Enabling Optimized Data Transfers with RISC-V

*A Note from Chris Lattner, New SVP of Platform Engineering* 

My quest is to build beautiful things that help change the world, and I’ve been fortunate to spend the last 15 years in Silicon Valley, working with some of the major players shaping all sorts of technology. Today, I’m super excited to join SiFive - the company I believe is best positioned to transform the silicon industry, to lead the Platform Engineering team. With [experience](http://nondot.org/sabre/Resume.html) building and leading large-scale production systems that power our industry, I’m looking forward to making the dream of customized chips a reality with SiFive’s amazing team of engineers. 

The end of Moore’s Law is a profound time, leading to new accelerators, new demand for custom ASICs, and new opportunities - and I believe that it is time for the semiconductor industry to change its approach to innovation. This industry has been defined by proprietary technologies that are difficult to use, don’t inter-operate well, and have poor user experience. I believe that open tooling, world-class engineering, and a focus on end-to-end user experience can transform the industry. Similarly, the RISC-V architecture provides unique opportunities for SoC customization at every level. This is only possible with SiFive’s ambitious design methodology, which is unmatched in the industry. 

My background includes experience creating and leading a number of large-scale technologies, including compiler technologies like the LLVM Compiler Infrastructure project, the Clang C and C++ compiler, the MLIR machine learning infrastructure, and others. I also spearheaded the creation of Swift - a programming language that powers Apple’s ecosystem - and led a team at Tesla that applies a wide range of tech in the autonomous driving space. Most recently, I built and managed an array of AI-related compiler, runtime, and programming language teams for Google Brain and TensorFlow. 

I’m extremely thankful for the opportunities I’ve had in my career, but I’m even more excited to join the ambitious and world class team at SiFive, who are tackling an even bigger project: making custom silicon more accessible through SiFive’s design platform. SiFive's vertically integrated, idea-to-silicon team is an incredible one-stop-shop, making it possible to develop end-market hardware faster and more affordably than ever before. 

Faster, better, and cheaper custom SoC development will make it more accessible, and will allow people everywhere to accomplish technological breakthroughs that couldn’t happen anywhere else. Let’s change the world together! 

 - Chris

ChrisLattner-Blog.PNG



This is the second in a series of blogs about Domain-specific accelerators (DSAs), which are becoming increasingly common in SoCs. Part #1 addressed the challenges associated with data transfers between DSAs and the core complex, and showed how RISC-V offers a unique opportunity to optimize fine-grain communication between them and improve core-DSA interaction performance.

To recap, a DSA provides higher performance per watt by optimizing the specialized function it implements. Examples of DSAs include compression/decompression units, random number generators and network packet processors. A DSA is typically connected to the core complex using a standard IO interconnect, such as an AXI bus (Figure 1).

![AXI Bus](https://images.prismic.io/sifive/07e6b833-dfff-4803-a824-354b0d2405cc_axi-bus.jpg?auto=compress,format)

RISC-V offers a unique opportunity to optimize high-bandwidth communication between cores and DSAs. Cores often issue fine-grain load and store instructions in the IO space to access DSA memory. The problem, however, is that these loads and stores to DSA memory might have side effects. For example, a load to a specific DSA memory address might trigger a network message as a side effect of the load. Typically, because of such side effects, loads and stores from a core to an IO device are required to be observed by the IO device in order. This is also known as point-to-point ordering.

A naive way to implement such point-to-point ordering is to issue a load to a DSA and wait for the result to return to the core (Figure 2). This is highly inefficient because successive loads or stores to DSA memory cannot be issued back-to-back in a pipelined fashion. A RISC-V implementation would typically implement such IO loads in a pipelined fashion with help from the interconnect between the core and DSA (Figure 3). For example, if a mesh topology uses a fixed path (e.g., X-Y routing) from the core to the DSA (perhaps via the IO bridge), then the interconnect can guarantee the ordering and thereby allow very high bandwidth access to DSA memory

The RISC-V architecture itself offers two other modes of optional IO ordering. First, RISC-V offers a very conservative IO ordering mode, which can be selectively used to guarantee strong ordering when necessary. Second, RISC-V offers a high-bandwidth relaxed ordering mode where IO loads and stores can be reordered. This mode would typically be used for DSA memory that does not have side effects.

See more details about SiFive’s standard cores, or to customize and build domain-specific RISC-V cores, please visit [sifive.com/risc-v-core-ip](https://www.sifive.com/risc-v-core-ip)




Part 2: High-Bandwidth Core Access to Accelerators: Enabling Optimized Data Transfers with RISC-V



This is the first in a series of blogs about Domain-specific accelerators (DSAs), which are becoming increasingly common in systems-on-chip (SoCs). A DSA provides higher performance per watt than a general-purpose processor by optimizing the specialized function it implements. Examples of DSAs include compression/decompression units, random number generators and network packet processors. A DSA is typically connected to the core complex using a standard IO interconnect, such as an AXI bus. 

![IO Caching Slide](https://images.prismic.io/sifive/794e06be-0553-4c49-bc09-cc2736113b1d_IOCachingSlide.jpg?auto=compress,format)

Unfortunately, data transfers between DSAs and the core complex, which are often critical, can be inefficient in traditional SoCs.  Figure 1 shows that the datapath between a DSA and core complex in a traditional SoC traverses multiple interconnects 
and bridges.  This increases the latency between the cores and a DSA to 100s of cycles. Consequently, this makes it difficult to have fine-grain interaction between cores and a DSA.
 
RISC-V offers a unique opportunity to optimize such fine-grain communication between cores and DSAs. For example, as Figure 2 shows, a DSA can export a per-core DSA cache sitting next to a RISC-V core. The RISC-V core can poll status changes out of the DSA cache, thereby reducing the latency of interaction between the core and DSA to tens of cycles. The DSA can update 
status changes in the DSA cache through a sideband network. Others [1, 2] have argued for similar mechanisms.  
 
The DSA cache can further improve core-DSA interaction performance by prefetching data from the DSA and merging small IO writes into bigger chunks. A RISC-V core could even integrate some of these mechanisms within the core pipeline, if one were to design a custom RISC-V core.

[1] J. Mcalpin, "Notes on Cached Access to Memory-Mapped IO Regions", 
[https://sites.utexas.edu/jdm4372/2013/05/29/notes-on-cached-access-to-memory-mapped-io-regions](https://sites.utexas.edu/jdm4372/2013/05/29/notes-on-cached-access-to-memory-mapped-io-regions/)
 
[2] Mukherjee, et al., "Coherent Network Interfaces for Fine-Grain Communication," Proceedings of the 23rd Annual International Symposium on Computer Architecture, May 1996.
 
See more details about SiFive’s standard cores, or to customize and build domain-specific RISC-V cores, please visit [sifive.com/risc-v-core-ip](https://www.sifive.com/risc-v-core-ip)



Part 1: Fast Access to Accelerators: Enabling Optimized Data Transfer with RISC-V



The RISC-V ISA is rapidly becoming the new standard for compute, and has literally spawned a worldwide revolution in the semiconductor industry. At the beginning of 2019, SiFive set out to foster education about SiFive’s RISC-V based technologies and to advance deeper collaboration within the global hardware community. We succeeded! We completed 52 Tech Symposiums/Workshops reaching 26 countries and six continents – reaching all corners of the world. Over 10,000 people attended these events, demonstrating strong attraction to RISC-V in not only industry, but in academia as well.

![SiFive Tech Symposium](https://images.prismic.io/sifive/11502522-4461-4109-af6b-ba58e657f47f_sifive-tech-symposium-world-map.jpg?auto=compress,format)
![SiFive Tech Symposium Event Dates](https://images.prismic.io/sifive/8c325b66-f8de-4a39-a9de-336f6debc7e0_symposium-event-dates.jpg?auto=compress,format)

We’d like to express our gratitude to our co-hosts around the world who made all of this possible.
![Partner Logos](https://images.prismic.io/sifive/7a301b3c-ac7e-46ac-af0e-c2d895d4183a_partner-logos.jpg?auto=compress,format)

We’d also like to thank all of our partners around the world who sponsored and/or promoted the symposiums and workshops.
![Sponsors Logos](https://images.prismic.io/sifive/ed338905-6191-4d7e-a003-d331b327aca3_sponsors.png?auto=compress,format)

Last, but certainly not least, we’d like to thank all of the invited speakers who shared their knowledge, expertise and enthusiasm about RISC-V. Over 150 [speakers](https://sifivetechsymposium.com/speakers/) presented!

This tour has allowed us the opportunity to meet so many new people, who are now our friends. A lot of great memories were made. [See the glimpse of the highlights from each city](https://sifivetechsymposium.com/a-glimpse-of-past-events/).

We wish you happy holidays. We are looking forward to working with each and every one of you in 2020.



SiFive Completes its Global 52-City Tech Symposium/Workshop Tour



We completed our tour through South America, which included tech symposiums and workshops in São Paulo, Porto Alegre, Montevideo, Buenos Aires and Bucaramanga. We are proud to have co-hosted these events with South America’s most prestigious universities, including the Polytechnic School of the University of São Paulo (Poli-USP), the Federal University of Rio Grande do Sul (UFRGS), the Universidad Católica del Uruguay (UCU), the University of Bueno Aires (UBA), the Universidad Industrial de Santander (UIS), and the Integrated Systems Research Group Onchip at UIS. The combined attendance was 300+, which demonstrates the strong interest that South Americans have in RISC-V.

São Paulo, Brazil Symposium and Workshop (11/18):
![São Paulo, Brazil Symposium and Workshop (11/18)](https://images.prismic.io/sifive/b2cb58a8-b909-4077-ad88-1a55c578dabf_Sao-Paulo.jpg?auto=compress,format)

Porto Alegre, Brazil Symposium and Workshop (11/19):
![Porto Alegre, Brazil Symposium and Workshop (11/19)](https://images.prismic.io/sifive/ed902781-b426-4ebf-922c-e486ec0cc1ce_Porto-Alegre.jpg?auto=compress,format)

Montevideo, Uruguay Symposium and Workshop (11/21):
![Montevideo, Uruguay Symposium and Workshop (11/21)](https://images.prismic.io/sifive/3fc7b88e-da46-4b88-8358-5e566a41b79e_Montevideo.jpg?auto=compress,format)

Buenos Aires, Argentina Symposium and Workshop (11/22):
![Buenos Aires, Argentina Symposium and Workshop (11/22)](https://images.prismic.io/sifive/06db14c4-0873-41e5-9560-4134611c679c_Buenos-Aires.jpg?auto=compress,format)

Bucaramanga, Colombia Symposium and Workshop (11/25):
![Bucaramanga, Colombia Symposium and Workshop (11/25)](https://images.prismic.io/sifive/fb27f1c6-29e6-4e03-b394-3a6323200e22_Bucaramanga.jpg?auto=compress,format)

At all five symposiums, the main highlight was the hands-on workshop that offered attendees the unique opportunity to configure their own RISC-V core and bring up on an FPGA. Working professionals and students were enthusiastic about what they learned in the workshop and expressed their desire to continue using the RISC-V ISA for their current and future projects. We were humbled by the warm welcome we received by both academia and the local and regional electronics industry. In addition to our co-hosts, we’d like to express our gratitude to our South American partners, including Centro Interdisciplinar em Tecnologias Interativas (CITI-USP), the Department of Electronic Systems Engineering at the Polytechnic School of the University of São Paulo (PSI-EPUSP), the IEEE Uruguay Section and the IEEE Colombia Section. 

The RISC-V Revolution has reached South America!


SiFive’s Tech Symposiums and Workshops Throughout South America Included Participation by Both Academia and Industry



SiFive’s Tech Symposiums in Pakistan were a huge success, with the participation of more than 2,500 people from across the country. One of the symposiums was held at the NED University of Engineering and Technology in Karachi, and the other took place at the University of Engineering and Technology in Lahore. We are grateful to both of these universities for co-hosting these events with us, and to Lampro Mellon for partnering with us. All three were instrumental in making these symposiums world-class events. Attendees included students and professors, as well as delegations from federal and state governments of the Islamic Republic of Pakistan. The policy-making officials from the IT and education ministry also participated very actively in the symposiums. Everyone was extremely motivated and enthusiastic to learn more about the RISC-V ISA and the latest innovations. There were informative and engaging presentations by Naveed Sherwani (President & CEO), Krste Asanovic (Co-Founder & Chief Architect), Yunsup Lee (Co-Founder & CTO), Thomas Xu (CEO, SiFive China), Shafy Eltoukhy (SVP, Silicon BU), Anand Bariya (VP, Engineering), Muhammad Ahmed (Architect) and many others.

The symposium witnessed the first and formal adoption of RISC-V as the architecture of choice for all public universities in Pakistan’s Punjab Province. An MOU was signed in the presence of HE Sardar Usman Buzdar (Chief Minister of Punjab), Mr. Raja Humayun (Minister of Higher Education, Punjab Province), Krste Asanovic (SiFive), Naveed Sherwani (SiFive), Sabahat Rafiq (CEO, Lampro Mellon), Thomas Xu (SiFive China), Dr. Shafy Elthouky (SiFive), Chairman of Punjab Planning Division, Chairman of Punjab Higher Education Commission, Vice Chancellor of UET Lahore, Mr. Farooq Arshad (PTI Information Secretary), among other distinguished guests in Lahore.
## Glimpses of the Event:
![SiFive Tech Symposiums in Pakistan](https://prismic-io.s3.amazonaws.com/sifive/9e4cfaf3-71c6-4c31-b1c0-353b8e5ec799_pakistan-event.jpg)
![Yunsup Lee](https://prismic-io.s3.amazonaws.com/sifive/3d2b151a-6b6f-4a4c-a7ec-c8275dd87f69_yunsup-lee.jpg)
![Over 3,500 in attendance](https://prismic-io.s3.amazonaws.com/sifive/cb353cd3-9c6e-4313-9e25-0f83255df6f3_event-3-500.jpg)
![SiFive’s Tech Symposiums](https://prismic-io.s3.amazonaws.com/sifive/8d32a2f6-9878-47dc-9210-1b893bd0eb0a_symposiums-in-pakistan.jpg)

For more information on these and our many other tech symposiums and workshops taking place around the globe, please visit [www.sifivetechsymposium.com](https://www.sifivetechsymposium.com)




Our SiFive Tech Symposiums in Pakistan Drew Over 2,500 Attendees!



Our tour through the Middle East region included Istanbul, Amman, Cairo, Abu Dhabi and Dubai. This tour was dedicated to academia, and included presentations, tutorials and hands-on workshops. Attendees primarily consisted of PhD research scholars, professors and engineering students. It was humbling to see that the region’s universities have included the book, The RISC-V Reader: An Open Architecture Atlas, authored by SiFive Technical Adviser David Peterson and Co-Founder and Chief Engineer Andrew Waterman, in their curriculum. Besides presentations and tutorials, the attendees showed keen interest in the workshop. One could see the sense of achievement among the students on their successful completion of the workshop. It opened their minds to the infinite possibilities for exploring their unique ideas and realizing them into working products. The universities also showed desire to collaborate with SiFive on RISC-V research and development. Through these symposiums and workshops, SiFive has left its footprints in the Middle East region.

We would like to express our gratitude to our co-hosts – Mentor, TÜBİTAK BİLGEM, The University of Jordan, IEEE Jordan Section, EiTESAL, The American University in Cairo, the Artificial Intelligence and Intelligent Systems Institute (AIISI), Khalifa University, and BITS Pilani Dubai Campus. We’d also like to thank eFabless for their partnership.

For more information on these and our many other tech symposiums and workshops taking place around the globe, please visit [www.sifivetechsymposium.com](https://www.sifivetechsymposium.com)

![Istanbul,Turkey](https://prismic-io.s3.amazonaws.com/sifive/4a4bdd9f-4728-4dbd-b8de-fe35c71b8610_istanbul-symposium.png)
![Amman Workshop](https://prismic-io.s3.amazonaws.com/sifive/97257bd8-932c-4acb-ad90-c9f7c520875d_amman-workshop.png)
![Amman Workshop](https://prismic-io.s3.amazonaws.com/sifive/80639bb1-cc28-403e-ae15-d058d0de1ff4_amman-workshop-2.png)
![Cairo,Egypt](https://prismic-io.s3.amazonaws.com/sifive/f36fb4a3-e63e-43cc-8ec2-3a73bb5c6b9b_cairo-symposium.png)
![Cairo Workshop](https://prismic-io.s3.amazonaws.com/sifive/efd0cb98-f0a8-41ff-9244-6d7c95e4d411_cairo-workshop.png)
![Abu Dhabi](https://prismic-io.s3.amazonaws.com/sifive/c0aa7d94-87a5-46dd-a373-63fcc2a6f2a2_abu-dhabi.png)
![Dubai, UAE](https://prismic-io.s3.amazonaws.com/sifive/5c6d2cc0-0450-421c-9224-eda344869b67_dubai-workshop.png)

We Just Completed Five Energy-Filled Tech Symposiums and RISC-V Workshops Throughout the Middle East Region



Our SiFive Tech Symposiums in Portland and Seattle were a big success, thanks in large part to our co-host, Mentor, a Siemens business; and our partner, Lauterbach, a leader in microprocessor development tools. Many leading OEMs were in attendance, such as Amazon, Facebook, Intel, Microsoft and Google  There were presentations by the RISC-V Foundation, SiFive, Mentor and Lauterbach, as well as other ecosystem partners. We’d like to offer our thanks to the faculty and students at Portland State University for their participation at the symposium in Portland. We’d also like to thank the RISC-V Seattle Meetup Group who actively participated at the symposium in Seattle.

We’re now headed to South America for our next exciting round of symposiums and workshops. For more information on these and our many other tech symposiums taking place around the globe, please visit [www.sifivetechsymposium.com](https://www.sifivetechsymposium.com)

![The SiFive Tech Symposiums in Portland](https://prismic-io.s3.amazonaws.com/sifive/4531c1dc-7165-4ce8-bb8f-bd0416cb9a5c_SiFive-tech-symposiums-portland-1.jpg)

![The SiFive Tech Symposiums in Portland](https://prismic-io.s3.amazonaws.com/sifive/98b9705e-c532-4ea7-b2db-0a850bb75d65_SiFive-tech-symposiums-portland-2.jpg)

![The SiFive Tech Symposiums in Portland](https://prismic-io.s3.amazonaws.com/sifive/245e1370-8d0d-4e86-8f15-58ca73ead363_SiFive-tech-symposiums-portland-3.jpg)

![The SiFive Tech Symposiums in Seattle](https://prismic-io.s3.amazonaws.com/sifive/a908b542-2392-447f-ab1c-5308e93362c8_SiFive-tech-symposiums-seattle-1.jpg)

![The SiFive Tech Symposiums in Seattle](https://prismic-io.s3.amazonaws.com/sifive/ce4ccbf1-1993-4c31-8a9e-6390e356397b_SiFive-tech-symposiums-seattle-2.jpg)

The SiFive Tech Symposiums in Portland and Seattle are a Wrap

**Introducing the new SiFive U8-Series Core IP**

![SiFive U8-Series](https://prismic-io.s3.amazonaws.com/sifive%2F5880fe27-e76b-4136-a379-273141edda84_sifiveu8seriesresize.png)

SiFive is pleased to introduce the SiFive U8-Series Core IP, an incredibly scalable high-performance microarchitecture for modern SoC designs.  The SiFive U8-Series is the highest performance RISC-V ISA based Core IP available today, based on a superscalar out-of-order pipeline with configurable pipeline depth and issue queue width. SiFive U8-Series Core IP is designed for use in performance- and latency-sensitive markets, such as automotive, datacenter attach, and edge or end point deep learning SoCs.

The needs of the modern world to solve problems using deep learning and real-time low latency processing are increasing compute workloads in the enterprise, and migrating tasks into the edge and end point. Domain specific SoCs are being used to localize compute to reduce latency, improve workload performance, and increase efficiency. The requirements of modern SoCs include scalable processor cores that span current process technology, enabling configurable designs, and permit customization.

![SiFive U-Series Cores](https://prismic-io.s3.amazonaws.com/sifive%2Fcf9d84fb-392f-4bb7-ad11-00f4670be4df_fig1-u-core-series.png)

Based on the open, freely available RISC-V ISA, SiFive U8-Series Core IP is well-positioned to address these challenges. The SiFive 8-Series microarchitecture is fully parameterized to enable the generation of a vast array of configurations, allowing customers to explore the design space and fine-tune performance and features to the desired workload. 

**SiFive U8-Series Standard Cores**

SiFive will initially offer two standard cores in the SiFive U8-Series Core IP lineup. The standard core offerings will be the SiFive U84 core, optimized for power efficiency and area efficiency, and the SiFive U87 core with vector processing. The SiFive U84 design, focused on optimized efficiency, is the lead standard core, with more details on the SiFive U87 design to be released later.

![SiFive U84 & U87 Standard Core IP](https://prismic-io.s3.amazonaws.com/sifive%2F2477c5bd-c103-4a3d-b4de-e2ee24c74999_fig2-u84u87.png)

**Incredible, Efficient Performance**

Generationally, the SiFive U84 core offers a startling 3.1X higher performance than SiFive's popular U74 standard core. This is enabled by a 2.3X increase in IPC combined with a 1.4X increase in maximum frequency capability. Shown below, the SiFive U84 is 5.3X higher performance than the SiFive U54, isolated process. The SiFive U84 standard core in 7nm is 7.2X higher performance compared to a SiFive U54 standard core in 28nm. 

![SiFive U-Series Generational Performance](https://prismic-io.s3.amazonaws.com/sifive%2Fe015d8b5-a552-4f04-a2a0-da1e26c8375d_fig3-relativeperfu84.png)

**Winning Area Efficiency**

A quad-core SiFive U84 CPU, including 2MB of L2 cache, requires only 2.63mm2 in 7nm process technology while capable of operating at up to 2.6GHz clock speed. A single SiFive U8-Series CPU core, without L2 cache, can be laid out in as little as 0.28mm2. This massive area reduction without performance impact reduces overall solution cost, or allows the use of silicon area for new compute functions. 

![SiFive U84 Highlights](https://prismic-io.s3.amazonaws.com/sifive%2Ff24327ab-e4e6-429a-a0b9-9215824047ab_fig4-u84ppa.png)

The SiFive U84 standard core offers an incredible increase of 2X better area efficiency1 and 1.5X better performance/watt1, with very competitive performance when compared to an Arm® Cortex®-A72 processor. 

**Class-Leading Scalability**

SiFive U8-Series Core IP will be available on a variety of process nodes, from mass-market to leading-edge. The availability of verified IP with modern high-performance CPU features across such a broad array of foundry options defines the SiFive U8-Series as leading the market in scalability for design target and SoC design support. 

SiFive U8-Series scalability doesn’t end there, with the ability for SiFive customers to configure options inside the entire Out-Of-Order design space hyperplane. While the SiFive U84 standard core is configured with a 12-stage pipeline and triple-issue capability, the pipeline depth, issue queue count, and other options can be adjusted to perfectly suit the target market applications. 

SiFive U8-Series microarchitecture scalability options include the capability to cross-issue from the integer unit to the floating point unit, when the FP queue is empty. This flexibility when combined with design scalability of number of issue queues, and FP units in the design, can offer significant performance increases depending on the workload. 

SiFive U8-Series Core IP also features composable caches, enabling real-time operation support. For markets where low-latency, deterministic behavior is required, the ability to configure the high-performance OoO core to operate deterministically while maintaining the advantages of tiny area and superb efficiency makes SiFive U8-Series the obvious choice for automotive, enterprise, and edge or end point AI markets. 

**SiFive Mix+Match**

SiFive offers the ability to support heterogeneous core complexes, composed of different class cores. SiFive Mix+Match enables the design of core complexes with a mix of cores to enable the right level of processing capabilities for the target workload. On top of this, SiFive Custom Instruction Extensions permit any core to be enabled with new instructions to make workload acceleration simple and easy. Custom Accelerator IP from 3rd parties can be coherently included with SiFive’s TileLink coherent fabric for core-to-core communication, or SiFive ChipLink coherent fabric for chip-to-chip communications. 

![SiFive Mix+Match Example](https://prismic-io.s3.amazonaws.com/sifive%2Ff556a53c-f0d3-4886-b079-6077d80cf3ad_fig5-mix%2Bmatch.png)

SiFive also offers high-bandwidth memory interface IP, supporting SiFive TileLink and industry standard protocols, for SoC or chiplet style designs for memory intensive workloads that require the latest HBM2E+ memory capabilities. With validation in 7nm and 12nm process technology currently in progress, SiFive is extending high-performance DRAM capabilities from existing 16nm processes to leading-edge technologies. 

**Summary**

Today’s introduction of the new, high-performance SiFive U8-Series Core IP begins a new chapter for modern SoC design. Performance, area efficiency, and energy efficiency are key metrics for chip designers, and the SiFive U8-Series is compelling on all fronts. SiFive’s unique configurable methodology for fine-tuning IP to customer requirements unlocks the full potential of next-generation SoCs for markets that require high-performance application processor cores. 

SiFive now welcomes lead access to the new, high-performance SiFive U8-Series of application processor Core IP - please contact SiFive to find out more on how your next modern SoC design can benefit. 

**Footnote**

1 – Based on SiFive internal estimates of SPEC Int/GHz per Watt, and Power per MM2 of SiFive U84 Core with L2$ vs Arm® Cortex®-A72, of core implementation in 16nm process technology.
2 – Based on SiFive internal estimates compared to SiFive U7-Series using iso-process & iso-frequency methodology.

©2019 SiFive, Inc. All rights reserved. All trademarks referenced herein belong to their respective companies. PCI-SIG®, PCIE® and the PCI HOT PLUG design mark are registered trademarks and/or service marks of PCI-SIG. Arm and Cortex are registered trademarks of Arm Limited (or its subsidiaries) in the US and/or elsewhere. The Arm word and logo are trademarks of Arm Limited (or its subsidiaries) in the US and/or elsewhere. 

sifiveu8seriesresize.png

Incredibly Scalable High-Performance RISC-V Core IP

## Securing The RISC-V Revolution


![SiFive Shield](https://prismic-io.s3.amazonaws.com/sifive%2F0ebdcb30-26a9-4298-943d-8e31149556ba_sifiveshieldresize.png)

SiFive Shield is an open, scalable platform architecture designed to enable whole SoC security for RISC-V designs. The needs of modern SoC design dictate the need for a scalable solution for security, offering a low trusted computing base with clear root-of-trust and crucially, is auditable. Customization is also key, as a single offering fits all approach does not align to the needs of the next generation of domain specific processors now being designed.


Securing the RISC-V revolution requires a scalable architecture that offers per-memory protected memory regions and multi-core privilege modes. SiFive Shield and SiFive WorldGuard enable a scalable architecture with the ability to offer greater isolation. 

## SiFive WorldGuard

![SiFive WorldGuard](https://prismic-io.s3.amazonaws.com/sifive%2F7867de53-549f-4b13-995f-bdeceead7bcd_sifiveworldguard.png)

SiFive WorldGuard is a fine-grain security model for isolated code execution and data protection. SiFive Worldguard offers SoC level information control with advanced isolation control, based on multiple levels of privilege per world, and an unlimited amount of worlds. SiFive WorldGuard offers core-driven and process-id driven modes for multi-domain security, to offer data protection for core, cache, interconnect, peripheral, and memory. 

![Figure 1 - Core Driven Mode](https://prismic-io.s3.amazonaws.com/sifive%2F43aedfe6-dd30-4e11-aefc-a63e53f83558_fig1-worldguardcoremode.png)

In a multi-core processor, shown above, World ID markers are used to isolate processes from each other to ensure protected and isolated execution. Inside the SoC, the WID marker extends from core to cache, interconnect, peripherals, bus masters, DMA regions, and memories. Applications or OS environments can be isolated and protected, inside a high-performance multi-core system. For embedded systems where a single core is more common, the use of PID driven world ID's to protect and isolated execution between user and machine mode, for example. 

![Figure 2 - PID Driven Mode](https://prismic-io.s3.amazonaws.com/sifive%2F485845b3-6b68-41e7-9af1-b782ee722f05_fig2-worldguardprocessmode.png)

SiFive WorldGuard hardware accelerated multi-domain security moves the industry well beyond a single zone of trust. 

## Root of Trust

A clear root of trust is critical for enabling security. SiFive Shield offers secure on device storage of keys, with per device unique IDs. This enables flexible key management to support key and certificate provisioning at time of manufacture, critical to the beginning of secure lifecycle management. SiFive’s root of trust is based on open specifications and an open-source software platform for clear audibility.  

## Threat Prevention

Secure SoC design is enabled by accurate threat modelling. Inside of an SoC, the flow of information for processing requires an array of technologies. Fault detectors for the SoC ensure that operation continued as intended, to deter physical tamper attacks. Physical Memory Protection (PMP) and Physical Memory Attributes (PMA) are supported in 
the RISC-V ISA and leveraged by SiFive Shield to set limitations on memory ranges and memory mapped peripherals by privilege, enabling scalable domain security. 

Build upon the open and freely available RISC-V ISA enables a new approach to security. Building an open, secure platform architecture for security that can scale is the main goal of SiFive Shield.

## Verified Crypto-Engines

The SiFive Shield architecture includes a NIST SP 800-90A/B/C compliant true random number generator (TRNG) to enable cryptographic or entropy based secure features. The Cryptographic engines are protected against SPA/DPA/EMA attacks, and enable support for common use cases. The AES cryptographic engine offers block cipher and authenticated encryption support, while the secure hash crypto-engine support SHA-2 and SHA-3 standards. Public Key cryptographic RSA and ECDSA support is also offered. The cryptographic library is subject to external lab verification to ensure correct operation and validity. 

## Software

SiFive offers a single software platform based on open-source software. Figure n indicates the mix of community open-source software, including FreeRTOS and Linux OS support for SiFive RISC-V based SoCs. Further development is enabled via the SiFive Freedom Metal and Freedom SDK tool chains that offer a full development environment. 

## Summary

SiFive Shield is a new, transformative technology for securing RISC-V based SoCs. With an open, top-down security platform specification designed to provide a clear root of trust, low trusted codebase, effective lifecycle management, and a class-leading SiFive WorldGuard security model, the RISC-V revolution is secured by SiFive Shield. 

![Figure 3 - Competitive Comparison](https://prismic-io.s3.amazonaws.com/sifive%2Fa3fd17c8-840a-4d61-9be6-098d03e3b9e3_fig3-sifiveshieldcomparison.png)

SiFive_Shield_Metal_WordMark.png

SiFive Shield: An Open, Scalable Platform Architecture for Security



We’re confirming seats in Portland and Seattle for the Pacific Northwest leg of our worldwide 2019 SiFive Tech Symposiums. We are pleased to have Mentor, A Siemens Business as our co-host, and Lauterbach, a leader in microprocessor development tools, as our partner in both cities. 

The Portland symposium will take place Tuesday, October 22 at the Portland Community College. Our Seattle symposium will be on Wednesday, October 23 at thinkspace Seattle. All of the SiFive Tech Symposiums have been significantly instrumental in engaging the hardware community in the RISC-V ecosystem, and spearheading the emergence of new applications. We are constantly in awe of the brilliant minds that convene at these events. We thrive on watching intense conversations and the sharing of ideas between those already entrenched in RISC-V and others who are simply exploring design alternatives. 

The symposiums in Portland and Seattle will both feature presentations by the RISC-V Foundation, SiFive, Mentor and Lauterbach, as well as other ecosystem partners and academic luminaries. There will also be a tutorials, demos and presentations on RISC-V developments tools, platforms, core IP and SoC IP. As always, we have arranged for plenty of time for networking.

Attendance is free, but registration is required. 

- To view the agenda, and to confirm your seat in Portland, please click [here](https://sifivetechsymposium.com/agenda-portland/).
- To view the agenda, and to confirm your seat in Seattle, please click [here](https://sifivetechsymposium.com/agenda-seattle/).

We look forward to seeing you!


risc-vPort-Sea.png

The SiFive Tech Symposiums are Heading To Portland and Seattle This Month – See You There!



Today, SiFive is excited to announce the general availability of the Q3 2019 Engineering Update, packed with new features, tools, and improvements. In the first SiFive quarterly update, we discussed the transition from the “Information Age” to the “Experience Age.” In the Q3 Engineering Update, SiFive is delivering on our customer experience mantra: “Make It Easy” and “Get It Right.” - two principles at the heart of our Sales, FAE, and Engineering mindset for supporting and enabling our customers.

As the complexity of software continues to grow, the ability to quickly and efficiently write and debug software is critical to realize the fast time to markets necessary for IoT, Storage, Industrial, and Mission Critical markets as well as early silicon bring-up.

The focus of the Q3 2019 engineering update is adding [Nexus 5001™](https://nexus5001.org/nexus-5001-forum-standard/) Instruction Trace capabilities across the SiFive Core IP portfolio. Nexus 5001™ is a mature and open industry standard supporting trace of embedded processors. 

## Making It Easy

Configuring a SiFive Core IP project with advanced trace capabilities can now be performed in SiFive Core Designer. The core complex design is configured completely in SiFive’s cloud environment and delivered pre-integrated and verified in a single package saving you time, money, and engineering resources.

SiFive is also open-sourcing a cross-platform, C++ based, [Nexus 5001™ Trace decoder software for RISC-V](https://github.com/sifive/trace-decoder) in order to ease integration into existing debug and trace environments. The latest release of [Freedom Studio](https://www.sifive.com/blog/supporting-a-world-leading-risc-v-ip-portfolio) uses this software to display Instruction Trace streams intermixed with source code directly in the eclipse environment.

## Getting It Right

By using Nexus 5001™ trace, SiFive processors are supported by a number of industry supported tools, [including those provided by IAR, Lutenbach, and SEGGER](https://www.sifive.com/press/sifive-announces-key-enablement-of-trace-and-debug).

Trace can be sent to a dedicated trace SRAM buffer which can be read anytime by a debugger. Nexus 5001™ trace packets may be bridged to an AMBA® ATB interface to ease integration into existing designs, as well as off chip using the Serial Wire Trace protocol. 

The Nexus 5001™ trace encoders also support a configurable timestamp interface as well as the ability to both send and receive external triggers. In addition to the trace encoders, we are also adding an Instrumentation Trace Component (ITC). The ITC is a memory mapped peripheral which allows software to inject messages directly into the trace stream; printf for trace. This is especially useful for debugging large and complex software.

## SiFive Core Designer

In the Q3 release we are introducing 64-bit Linux capable U5 and U7 Core Series to SiFive Core Designer allowing for customization of all SiFive Core IP to be done from your browser.

SiFive E7-Series Core IP included in SiFive Core Designer now offers optional double-precision floating point (RV32D) capabilities. The following advanced debug features have been integrated into SiFive Core Designer for all SiFive Core IP:
- Instruction Trace Encoder with Crash Detection 
- Trace funnel for combining traces from multiple sources
- Debug Halt-On-Reset feature
- Instrumentation Trace with serial-wire output

![Trace Encoder](https://prismic-io.s3.amazonaws.com/sifive%2F812e30ff-a493-4497-a757-948349095ff9_te_scd.png)

Additionally, SRAM extraction options are available in SiFive Core Designer to help configure tailored cores to exacting specifications. 

These small but mighty improvements in SiFive Core Designer show SiFive’s commitment to continuous improvement to the development of modern SoC designs for all applications. 

## Summary

The SiFive Q3 2019 engineering update incorporates a broad and welcome set of new features and improvements. We know our Customers will appreciate the new capabilities and can’t wait to hear about the new designs and solutions our robust, scalable approach to modern SoC design enables. Best of all, the new improvements can be tested on your [Arty A7-100T](https://store.digilentinc.com/arty-a7-artix-7-fpga-development-board-for-makers-and-hobbyists/) FPGA test platform after configuring a core complex in SiFive Core Designer and using the latest version of [Freedom Studio](https://www.sifive.com/boards).




The second SiFive quarterly engineering release has arrived, and includes some great new Trace & Debug features. Static source code analysis may not offer a complete view of real world operation. Real time analysis enabled via tracing permits a deeper insight into the interactions of software and hardware to accelerate development, debug, validation of modern, configurable SoC designs.

A major focus of the [Q3 Engineer Update](https://www.sifive.com/blog/making-it-easy-to-get-it-right) was adding support for Nexus 5001™ compliant instruction trace. SiFive is pleased to contribute an open-sourced cross-platform, C++ based, [Nexus 5001™ Trace decoder software for RISC-V](https://github.com/sifive/trace-decoder). The latest release of Freedom Studio makes use of this software to display Instruction Trace streams intermixed with source code directly in the eclipse environment. 

![Freedom Studio Trace](https://prismic-io.s3.amazonaws.com/sifive%2F6707df9c-ba4b-47ba-a2ff-5fd69efa6e9d_freedom+studio+1908.png)

## Freedom Everywhere SDK

To enhance Freedom Studio further, the ability to more easily switch between Freedom E SDK environments has been updated. SiFive Core IP assets can be imported directly to generate Freedom E SDK projects, also greatly enhancing workflow. 

The Freedom E SDK bare-metal example program library has been expanded, including demonstrations of how to perform Cache Maintenance Operations as well as expanded CLIC and PLIC interrupt examples; and the SiFive HiFive Rev 1 B now includes a new simulate makefile target to automatically start up a QEMU simulation and QEMU BSP for the SiFive U54. 
To speed up test and integration processes, SiFive conveniently provides QEMU binaries to avoid the need to build from source. In keeping with our open-source values, the SiFive Freedom Tools repository contains the toolchains and utilities source for this release. 

## Freedom Unleashed SDK

Open-source contributions are a core value for SiFive, driving the contribution of an updated Freedom U SDK to an Open Embedded workflow, to enable community adoption of the SiFive HiFive Unleashed platform with an industry standard embedded linux workflow. 

The initial release includes a meta-sifive layer with support for the HiFive Unleashed and QEMU. The meta-sifive layer supports creating a demo image for the HiFive Unleashed board with the expansion board from Microsemi, a Microchip company, which supports a desktop environment and a few demonstration game titles. SD Card images can be easily created following standard Open Embedded workflows with complete instructions directly in the [Freedom U SDK](https://github.com/sifive/freedom-u-sdk) repository. We have also made HiFive Unleashed SD Card images available for download directly on our [website](https://www.sifive.com/boards) for those who just want to flash and go. 

SiFive will continue to improve Open Embedded support through future quarterly updates, while access to the previous buildroot based environment will continue to be available in Freedom U SDK under the [archive/buildroot](https://github.com/sifive/freedom-u-sdk/tree/archive/buildroot) tag.

## Summary

With these open-source contributions and key new feature support including in the SiFive Core IP portfolio, the time has never been better to engage for your next project. Reach out today and turn your next dream SoC into a reality with the world leader in RISC-V, SiFive. 


Supporting A World Leading RISC-V IP Portfolio



![Guest Speaker](https://prismic-io.s3.amazonaws.com/sifive%2F388206aa-aaf4-4eac-9bc9-b65c79e8ee45_speaker-9-13-2019.jpg)

Israel, and specifically the city of Tel Aviv, is said to have one of the highest densities of startups per capita in the world. At our SiFive Tech Symposium, we heard from some of the brightest minds residing at the epicenter of this high-tech hub. They shared their visions for the industry as well as their contributions to the semiconductor ecosystem via RISC-V based solutions.

This is the second year in a row that we’ve hosted the SiFive Tech Symposium is Israel. With our partners, Silicon Catalyst and CEVA, and participation from Western Digital and Technion, we saw a 25% increase in the number of attendees this year – 30% were repeat attendees, and 70% were first-time participants. Overall, 80% of the attendees came from industry, and 20% from academia. It is clear that there is a much deeper level of knowledge and a greater increase in engagement within the RISC-V ecosystem in Israel. The participants were eager to learn about the latest RISC-V based developments and solutions that are available to them. One of the highlights was the AI demo showing the power of RISC-V based high speed, multiprocessing applications. During the networking sessions, the speakers were heavily engaged in small-group discussions with the audience. This personal interaction, and the sharing of knowledge and ideas between industry veterans and the rest of the ecosystem, is always one of the greatest takeaways from the symposiums. The growing enthusiasm about RISC-V among those in the Israeli industry and tech community is very encouraging, and we are looking forward to our continued engagement with them as the ecosystem continues to grow.

![RISC V Demo](https://prismic-io.s3.amazonaws.com/sifive%2F76462190-828a-487a-ba60-4de78f2ff579_risc-v-demo.jpg)

![RISC V Conference](https://prismic-io.s3.amazonaws.com/sifive%2F2426b6f7-9488-458b-bfe0-41c1fdbb900c_rics-v-conference.jpg)

## What’s Next?
Over the next few weeks, we will be hosting hands-on workshops in Cairo, Istanbul and Dubai. For more information on these and other SiFive Tech Symposiums, please visit [www.sifivetechsymposium.com](https://sifivetechsymposium.com/)

We look forward to seeing you!


Israel is Evolving as a High-Tech Hub, and RISC-V is Playing a Vital Role

Designing new custom hardware accelerators for deep learning is clearly popular, but achieving state-of-the-art performance and efficiency with a new design is a complex and challenging problem.

Two years ago, NVIDIA opened the source for the hardware design of the NVIDIA Deep Learning Accelerator [(NVDLA)](http://nvdla.org/) to help advance the adoption of efficient AI inferencing in custom hardware designs. The same NVDLA is shipped in the [NVIDIA Jetson AGX Xavier Developer Kit](https://developer.nvidia.com/embedded/jetson-agx-xavier-developer-kit), where it provides best-in-class peak efficiency of 7.9 TOPS/W for AI. With the open-source release of NVDLA’s optimizing compiler on [GitHub](https://github.com/nvdla/sw/releases/tag/v1.2.0-OC), system architects and software teams now have a starting point with the complete source for the world’s first fully open software and hardware inference platform.

In this blog we’ll explain the role that a network graph compiler plays in the key goal of achieving power efficiency in a purpose-built hardware accelerator, and we’ll show you how to get started by building and running your own custom NVDLA software and hardware design in the cloud.
![Embedded NVDLA Diagram](https://prismic-io.s3.amazonaws.com/sifive%2Fade06deb-11bb-4154-adcf-642f273961fe_embedded_nvdla_diagram.png)
![NVDLA](https://prismic-io.s3.amazonaws.com/sifive%2Fbb35be64-252e-4835-871a-141dbad095ff_nvdla.png)
NVDLA Small Profile Modal

Compiler optimizations such as layer fusion and pipeline scheduling work well for larger NVDLA designs, providing up to a 3x performance benefit across a wide range of neural network architectures. This optimization flexibility is key to achieving power efficiency across both large network models like ResNet-50 and small network models like MobileNet.

The NVDLA core hardware has six specialized hardware units which can be scheduled either concurrently or in a pipelined configuration. It also has both small and large hardware profiles. The large profile includes advanced features such as an on-chip SRAM interface and the ability to attach a microcontroller. You can find further details about NVDLA’s profiles [here](http://nvdla.org/primer.html#accelerating-deep-learning-inference-using-nvdla). The hardware architecture is modular, and it is designed to be scalable from small embedded IoT designs to large data center class chips using arrays of NVDLA units. The compiler can be tuned based on various chosen factors: the NVDLA hardware configuration, the system’s CPU and memory controller configurations, and the application’s custom neural network use cases if desired.
![NVDLA primer](https://prismic-io.s3.amazonaws.com/sifive%2F67495333-9785-45e6-a6f6-e2a8742b9d94_nvdla-primer.png)
NVDLA Small Profile Modal

Compiler optimizations such as layer fusion and pipeline scheduling work well for larger NVDLA designs, providing up to a 3x performance benefit across a wide range of neural network architectures. This optimization flexibility is key to achieving power efficiency across both large network models like ResNet-50 and small network models like MobileNet.
![Chart 1](https://prismic-io.s3.amazonaws.com/sifive%2F1d84f61b-d843-43db-8b0a-5b5b30bbdb5d_chart-1.gif)

For smaller NVDLA designs, compiler optimizations such as memory tiling are critical for power efficiency. Memory tiling enables a design to balance on-chip buffer usage between weight and activation data, and so minimizes off-chip memory traffic and power consumption.

Furthermore, users are free to create fully customized layers tuned for their own specialized use cases or experiment with the latest cutting-edge algorithms published in research.

Users can gauge the expected performance of the default NVDLA large profile model based on the performance numbers below. Measurements were captured using one of the two NVDLA cores on a Jetson AGX Xavier Developer Kit.

![Performance Benchmarks](https://prismic-io.s3.amazonaws.com/sifive%2Fdfb49ee8-0bf1-4b43-9184-d32b414deb7b_chart-2.gif)

## Design in the Cloud with RISC-V and FireSim on AWS

With this compiler release, NVDLA users have full-access to the software and hardware source needed to integrate, grow, and explore the NVDLA platform. One of the best ways to get started is to dive right in with object detection using YOLOv3 on NVDLA with RISC-V and [FireSim](https://fires.im/) in the cloud.

To get hands on with [FireSim-NVDLA](https://github.com/CSL-KU/firesim-nvdla), follow the FireSim [directions](http://docs.fires.im/en/1.5.0/index.html) until you are able to run a single-node simulation. While following the step-by-step instructions, verify that you are using the firesim-nvdla repository during the “Setting up the FireSim Repo” section as shown below:

git clone https://github.com/CSL-KU/firesim-nvdla 
cd firesim-nvdla 
./build-setup.sh fast 

Once your single-node simulation is running with NVDLA, follow the steps in the [Running YOLOv3 on NVDLA](https://github.com/CSL-KU/firesim-nvdla#running-yolov3-on-nvdla) tutorial, and you should have YOLOv3 running in no time.

NVIDIA is excited to collaborate with innovative companies like [SiFive](https://www.sifive.com/) to provide open-source deep learning solutions.

![NVDLA-SiFive](https://prismic-io.s3.amazonaws.com/sifive%2F900a988b-5001-4a2c-9f2d-3001b48fcaa5_nvdla-sifive-625x481.png)
SiFive running Deep Learning Inference using NVDLA

*We are incredibly excited to see NVIDIA leading efforts developing the open-source Machine Learning ecosystem,” said Yunsup Lee, CTO/co-founder of SiFive and co-inventor of RISC-V. “SiFive first demonstrated NVDLA running on the SiFive Freedom Platform a year ago, and the new performance-optimized open-source NVDLA compiler further enables SiFive to create domain-specific optimized SoC designs ready for the modern compute needs of AI in the IoT Edge.”*

## Stay Plugged In
- Sign up on the [nvdla.org](http://nvdla.org/signup.html) website to receive NVDLA news and announcements
- Download the latest [open-source release of NVDLA](https://github.com/nvdla/sw/releases)
- Give NVDLA a try today with YOLOv3 on [FireSim-NVDLA](https://github.com/CSL-KU/firesim-nvdla)
- Get involved with the NVDLA community on GitHub
- Feel free to contact the NVIDIA NVDLA team through [e-mail](mailto:nvdla@nvidia.com)

NVDLA Deep Learning Inference Compiler is Now Open Source



![SiFive Speaker](https://prismic-io.s3.amazonaws.com/sifive%2Ff761f34b-65df-4ac3-9df4-d72729f8d263_sifive-speaker.jpg)

Our SiFive Tech Symposiums and Workshops in India and Bangladesh were a huge success, and an inspirational endeavor as well. We hosted events in six cities total, including symposiums in Noida/Delhi, Pune, Bangalore and Hyderabad, and workshops in Chennai and Bangladesh’s capital city of Dhaka. Attendance was at capacity in all locations, and was over capacity in Pune and Bangalore.

## Highlights From India 
Our co-hosts in India – Western Digital, Microchip and IIT Madras – delivered powerful keynote presentations that underscored both the momentum surrounding the RISC-V ISA, and the cores and IP blocks that are accelerating the ecosystem and unleashing innovation at the edge and beyond. 

One of the many highlights came from the Centre for Development of Advanced Computing (C-DAC) – one of our partners in Pune. They provided an update on their RISC-V based research and development program, and also expressed their eagerness to work with SiFive. We are equally eager! 

Another highlight came from IIT Madras – our co-host in Chennai. We received an update on the RISC-V Shakti Project, which is the academically renowned open-source initiative at IIT Madras that is spearheading the building of processors based on the RISC-V ISA, as well as reference SoCs and other associated components. The technological accomplishments by the SHAKTI team are world class.
 
Representative from both C-DAC and IIT Madras extended an invitation to Krste Asanovic, co-founder and chief architect at SiFive and chairman of the RISC-V Foundation, as well as others from the SiFive team, to tour their labs and see their RISC-V based projects in action. The team thoroughly enjoyed and greatly appreciated seeing the labs and all of the progress being made. We thank both C-DAC and IIT Madras for hosting us. 

The workshop in Chennai provided students and others with the unique opportunity to configure their own RISC-V core and bring up on an FPGA. Their excitement to learn, and to achieve the goal of their design in such a short amount of time was very evident. The participants felt encouraged to work more with the platform and to explore more possibilities. 

![Group Meeting](https://prismic-io.s3.amazonaws.com/sifive%2F7451ec8b-3ad2-4d73-b895-76578d3dfb0e_group-meeting-re.jpg)
![Collaboration](https://prismic-io.s3.amazonaws.com/sifive%2Fcca94723-db1c-4e94-8130-5c2a34e195d2_collaboration2.jpg)

## Highlights From Bangladesh
Our co-hosts, Ulkasemi and Bangladesh University of Engineering and Technology (BUET), were instrumental in making the workshop in Dhaka a world class event with the participation of industrial experts, professors, and the vibrant student community of Dhaka. One of the highlights was the presentation by a professor from BUET who elaborated on the University’s research activity, and showcased some of the recent work.
 
There was also a hands-on workshop where students, industrial experts, and senior professors actively participated to implement customizable RISC-V cores using SiFive’s IP Core Designer. By the end of the day, all the attendees were well-versed in the RISC-V revolution.
![Collaboration Talks](https://prismic-io.s3.amazonaws.com/sifive%2Fd4a5fd96-fbd6-4647-a59a-2ee7ccec8cb9_collaboration.jpg)


## Special Thanks
We are very grateful to Western Digital, Microchip, IIT Madras Ulkasemi and BUET, as well as our many ecosystem partners who helped immensely in making these events so successful. With each of these events, we are always humbled and inspired by the collective power of the minds that share in our endeavor to create and participate in a truly open source environment that fosters an unobstructed path to innovation.

![What’s Next?](https://prismic-io.s3.amazonaws.com/sifive%2F20a9744e-d02d-4aa9-b3c2-4dc720c4dc22_whatsnext.jpg)
 
## What’s Next?
The next SiFive Tech Symposium will take place in Middle East and Africa (MEA), followed shortly by symposiums in the Pacific Northwest, USA. For more information on these and other SiFive Tech Symposiums, please visit [www.sifivetechsymposium.com](https://www.sifivetechsymposium.com)


Collaboration, Inspiration and Progressive RISC-V Based Innovation in India and Bangladesh is Increasing at a Steady Pace 



Last year we hosted several SiFive Tech Symposiums in India to help promulgate the RISC-V ecosystem in the region. The enthusiastic reception from those in industry as well as students and faculty at India&#39;s most esteemed universities was inspiring. This July and August, we&#39;re bringing the SiFive Tech Symposium back to India, and also visiting Bangladesh. Our goal remains to foster the RISC-V ecosystem and to help prepare university students for entry into a workforce where RISC-V is heavily utilized. We have industry-centric symposiums planned in New Delhi/Noida, Pune, Bangalore and Hyderabad; and university-centric tutorials and workshops planned for Chennai, and Dhaka in Bangladesh. Attendance at all events is free, but registration is required. Here is a glimpse of what&#39;s happening in each city. You can also visit the [https://sifivetechsymposium.com](https://sifivetechsymposium.com) to learn more about these and other SiFive Tech Symposiums being held throughout the world.

**New Delhi/Noida Symposium – Monday, July 29**

With Western Digital as our co-host, this event will feature presentations by Krste Asanovic, chairman of the RISC-V Foundation and co-founder and chief architect at SiFive; Western Digital; Ministry of Electronics &amp; Information Technology, government of India; Silicon Catalyst; CircuitSutra Technologies;Computer Science and Engineering Department at IIT Delhi; and many more. There will also be a tutorial on SiFive&#39;s Core Designer, which will demonstrate the ease and speed at which a customized CPU core can be built. To view the full agenda and to register to attend, please visit [https://sifivetechsymposium.com/agenda-delhi-noida/](https://sifivetechsymposium.com/agenda-delhi-noida/)

**Pune Symposium – Wednesday, July 31**

With Western Digital as our co-host, this event will feature presentations by Krste Asanovic, chairman of the RISC-V Foundation and co-founder and chief architect at SiFive; Western Digital; Hardware Design Group at the Center for Development of Advanced Computing (C-DAC, India); Silicon Catalyst; IoTIoT.in; and many more. There will also be a tutorial on SiFive&#39;s Core Designer, which will demonstrate the ease and speed at which a customized CPU core can be built. To view the full agenda and to register to attend, please visit [https://sifivetechsymposium.com/agenda-pune/](https://sifivetechsymposium.com/agenda-pune/)

**Bangalore Symposium – Thursday, August 1**

With Microchip and Western Digital as our co-hosts, this event will feature presentations by Krste Asanovic, chairman of the RISC-V Foundation and co-founder and chief architect at SiFive; Microchip; Western Digital; QuickLogic; Silicon Catalyst; Morphing Machines; and many more. There will also be a tutorial on SiFive&#39;s Core Designer, which will demonstrate the ease and speed at which a customized CPU core can be built. To view the full agenda and to register to attend, please visit [https://sifivetechsymposium.c](https://sifivetechsymposium.com/agenda-bangalore/)[om/agenda-bangalore/](https://sifivetechsymposium.com/agenda-bangalore/)

**Chennai Tutorial/Workshop – Saturday, August 3**

With IIT Madras as our co-host, this academic-centric event will feature a presentation by Krste Asanovic, chairman of the board of the RISC-V Foundation and co-founder and chief architect at SiFive, and other industry veterans. There will be a tutorial on RISC-V cores and software, and a hands-on workshop where attendees will configure their own custom RISC-V core. This event presents a unique opportunity to network with RISC-V luminaries and solution providers. To view the full agenda and to register to attend, please visit [https://sifivetechsymposium.com/agenda-chennai/](https://sifivetechsymposium.com/agenda-chennai/)

**Hyderabad Symposium – Monday, August 5**

With Western Digital as our co-host, this event will feature presentations by Western Digital; SRiX; CircuitSutra Technologies; and many more. There will also be a tutorial on SiFive&#39;s Core Designer, which will demonstrate the ease and speed at which a customized CPU core can be built. To view the full agenda and to register to attend, please visit [https://sifivetechsymposium.com/agenda-hyderabad/](https://sifivetechsymposium.com/agenda-hyderabad/)

**Dhaka, Bangladesh Tutorial/Workshop – Aug 26**

With the University of Dhaka and Ulkasemi as our co-hosts, this academic-centric event will feature presentations by executives at SiFive, a talk by a faculty member at the University of Dhaka, a tutorial on RISC-V cores and software, and a hands-on workshop where attendees will configure their own custom RISC-V core. This event presents a unique opportunity to network with RISC-V luminaries and solution providers. To view the full agenda and to register to attend, please visit[https://sifivetechsymposium.com/agenda-dhaka/](https://sifivetechsymposium.com/agenda-dhaka/)

We look forward to seeing you!

SiFive Fosters RISC-V Collaboration and Education in India and Bangladesh Via Symposiums, Tutorials and Workshops

For consumers of low-end processors, the Dhrystone benchmark can be a valuable tool for estimating performance. Due to the nature of the Dhrystone benchmark, high-end Application Processor performance is incompletely represented by a Dhrystone score. For processor providers a Dhrystone score is a commonly used metric for instruction throughput comparison in early stage evaluation.

To fairly compare Dhrystone scores, the test conditions must be published. To that end SiFive offers two Dhrystone scores for our standard cores, Legal and Best Effort. The Legal score is achieved under the conditions of the Dhrystone benchmark, laid out in the Dhrystone Compilation model and measurement ["ground rules"](https://github.com/sifive/benchmark-dhrystone/blob/8ff0ab1db77b134b56815905bf694eb8a767285b/dhry.h#L173).

In this blog, I will show you how SiFive achieved Best Effort scores through the use of compiler techniques.

## Achieving Best Effort

Using a SiFive [E31 Standard Core](https://www.sifive.com/cores/e31), a single-issue in-order RV32IMAC core, as an example to demonstrate how a Dhrystone score can be improved dramatically. The following table a summary of the score. As expected, the E31 core reaches its peak performance of 1 IPC due to its single-issue architecture. However, the Dhrystone score varies by different compiler option sets and existence of library specific tuning. By using an aggressive compiler option set with a customized strcmp instruction, the Dhrystone score increases by 73% (1.61 to 2.78).

![SiFive E31 Dhrystone score](https://prismic-io.s3.amazonaws.com/sifive%2Fd8354ff3-1921-41a3-bec3-b1e6a581c279_table01.png)

## Dhrystone score and instruction count

Dhrystone scores are regularly represented as DMIPS/MHz using the following equation:

    DMIPS/MHz = iteration/cycle*1000000/1757

The Dhrystone score is higher if fewer cycles are spent per Dhrystone iteration. One can reduce the cycle number by improving the micro-architecture (e.g., branch prediction, load latency, cache hit rate), ultimately the minimal cycle number will be limited by the instruction count.

To estimate the best score by the instruction count we can assume a single-issue core maintaining peak performance (IPC=1) means that N cycles is equal to N instructions. The chart below plots the relationship of instruction number and score of a IPC-1 machine. When compiled using Legal compiler options the result is 338 instructions per iteration. This requires 338 cycles assuming peak performance, resulting in 1.68 DMIPS/MHz; 1.68 DMIPS/MHz is the best a single-issue machine can achieve for 338 instructions.

Running the Dhrystone benchmark using the Legal option, the SiFive E31 core will achieve a score of 1.61 DMIPS/Mhz, which is 96% of the maximum. Thus, a SiFive E31 core at peak performance offers IPC = 0.958.

![score of ground rule](https://prismic-io.s3.amazonaws.com/sifive%2Ff229e35c-dcdf-4144-8190-56aab7379c53_line_chart01.png)

## Function Inline & Link Time Compiler Optimizations

Function inlining and link time optimization (LTO) can reduce the number of instructions needed to perform the Dhrystone benchmark workload. 

The chart below shows the dynamic instruction count under the 3 compiler options:

-   Ground rule
-   Ground rule + inline
-   Ground rule + inline + LTO

Instruction count can be reduced by 21% through inline merges of functions, to reduce branches. With the application of link time optimization the instruction count can be reduced by an additional 19%. In total, the instruction are reduced by 36% purely by applying compiler optimizations.

![instruction count reduction](https://prismic-io.s3.amazonaws.com/sifive%2F5e2d0b7d-6f42-4b0a-ab97-8cf7590af51c_stack_chart01.png)

Instruction count reduction in the Dhrystone loop directly boosts the score without needing changes to the micro-architecture of the processor. In the chart below we mark the points of inline and inline + LTO. Assuming constant IPC (0.958), the score may theoretically increase 56% (1.68 to 2.63 DMIPS/Mhz). For the SiFive E31 at IPC = 0.958, the score increases 57%, from 1.61 to 2.53.

![all score](https://prismic-io.s3.amazonaws.com/sifive%2Ff37b60e4-7eaf-4b70-b947-4d62ff4746dd_line_chart02.png)

## Benchmark Specific Micro-architecture Changes 

The Dhrystone benchmark relies largely on standard C library functions. Analyzing the results of the previous optimizations I determined strcmp() occupies 16%, 21% and 26% of total instruction in the three compiler option sets, as represented by the below chart.

![strcmp portion](https://prismic-io.s3.amazonaws.com/sifive%2F0885c23f-45d8-4224-a035-8084bd371b77_stack_chart02.png)

In the circumstances described above, the Dhrystone score is more affected by the implementation of the strcmp() function than the processor micro-architecture as up to 26% of the code is a single function call. 

To further improve Dhrystone score, a custom instruction to improve strcmp() performance can be created to replace the strcmp() function, effectively eliminate around twenty instructions per Dhrystone iteration, based on the RISC-V newlib [strcmp implementation](https://github.com/riscv/riscv-newlib/blob/riscv-newlib-3.0.0/newlib/libc/machine/riscv/strcmp.S). As the chart below shows, this can improve the score by 7%, 8%, and 10% respectively for the three options. For the SiFive E31 core (IPC = 0.958) this increases the score to 1.70, 2.11 and 2.78, respectively.

![score change due to strcmp](https://prismic-io.s3.amazonaws.com/sifive%2F15ca3025-e587-42e4-8bf2-af3028955afa_line_chart03.png)

SiFive does not include a hardware implementation of strcmp, as it is unlikely to benefit many embedded processor applications. However, there may be workloads that a performance improvement based on customized instructions are worthwhile. [SiFive Core Designer](https://www.sifive.com/core-designer) can help you understand the options available for configuring a core to your needs, including adding the SiFive custom instruction extension, [SCIE](https://www.sifive.com/blog/when-hardware-roadmaps-look-like-software-roadmaps).

## Easily Reproducing SiFive Best Effort Scores

SiFive's [Freedom E SDK](https://github.com/sifive/freedom-e-sdk) includes the Dhrystone benchmark along with [preset optimizations](https://github.com/sifive/freedom-e-sdk/blob/v201905-branch/scripts/standalone.mk#L144-L156) for the 3 compiler optimizations outlined in this blog by setting the DHRY_OPTION parameter when executing the makefile:
-   Ground rule
-   Ground rule + inline (DHRY_OPTION=fast)
-   Ground rule + inline + LTO (DHRY_OPTION=best)

## Conclusion

With this understanding of Dhrystone performance, you can now see how the score may be influenced by compiler options, and micro-architecture changes. When comparing manufacturer provided scores, the conditions of the test are important to understand so that compiler optimizations are not confused with micro-architectural advantages. 



table01.png

Dhrystone Performance Tuning on the Freedom Platform

*Highlights From the SiFive Tech Symposiums*

In its endeavor to educate the tech world about the benefits of the RISC-V ISA, SiFive just completed its APAC and Australia series of tech symposiums. Throughout the month of June, symposiums were held in Tokyo, Daejeon, Pangyo, Hsinchu, Singapore and Sydney. The audience included academia, the business industry, and many RISC-V ecosystem partners. On average, in all seven cities, 60% of the audience came from the tech industry and 40% belonged to academia/universities. Pangyo, Hsinchu, Sydney and Tokyo witnessed a record number of turnouts. Hsinchu had over 460 registrations. Attendees said they were intrigued by the potential of the RISC-V architecture displayed through the AI demos by the SiFive team. Ecosystem partners&#39; demos also pulled the crowd and engaged them. During the breaks and networking hours, there was lively and enthusiastic interaction between speakers and inquisitive audiences. During the question and answer sessions after each presentation, the speakers were faced with both basic-level and high-level questions on both the technical and business front. In addition to the growing number of attendees in 2019, the SiFive Tech Symposiums have also attracted numerous partnerships from high profile ecosystem partners, including the following:

![Image Title](https://prismic-io.s3.amazonaws.com/sifive%2F36a64302-4764-45e0-93a8-edc0b86988ae_sponser.jpg)
![Image Title](https://prismic-io.s3.amazonaws.com/sifive%2Fd43fe9c5-8ba1-4a57-8fb7-583412d29017_sponser2.jpg)

The Highlights:

We are continually impressed and inspired by our ecosystem partners and the magnitude of the RISC-V revolution. All stakeholders are working in tandem with a common goal of the proliferation of RISC-V. All support the SiFive Tech Symposium as a key platform for meeting their RISC-V objectives.

One of the many highlights was a presentation by Mark Throndson, Sr. Director of Product Management at SiFive. He logged into SiFive&#39;s Core Designer to demonstrate how easy it is for anyone to build their own customized CPU core on the fly. This demonstration showed the audience the user-friendliness and the results delivered by the tool.

Another highlight was hearing about the RISC-V based research taking place at the National University of Singapore. Assistant Professor Trevor Carlson, spoke about the interesting work going on in the university&#39;s Department of Computing, and he expressed his interest in working with SiFive.

Another very interesting presentation was by Anand Bariya, VP of engineering at SiFive. He spoke about SiFive&#39;s new initiative, the &quot;SiFive Learn&quot; program at both the National University of Singapore and the University of Sydney. This program provides short and long-term (10+ years) education that spans K-12, higher education, professional/corporate learning, and even individuals, such as hobbyists. It focuses on democratizing access to computer architecture education and supports the next generation of innovators and dreamers through inspiring programs.

Last but not least, one attraction at all symposiums that always keeps the audience captive is the video: Design Your Own CPU!!

We&#39;d like to thank each of our co-hosts and partners for joining us in fostering education, innovation, networking and idea sharing within the global open-source community. We are grateful for their support and we are humbled to share in the collaborative success that open source brings to the hardware community.

After the success of the APAC and Sydney symposiums, we are heading to India and Bangladesh in August. To learn more, or to register for the event closest to you, please visit [www.sifivetechsymposium.com](http://www.sifivetechsymposium.com/).

A picture speaks a thousand words:

![Image Title](https://prismic-io.s3.amazonaws.com/sifive%2Fee24fecd-475c-46a9-95a4-3bac35b684e6_daejeon-2019.jpg)

![Image Title](https://prismic-io.s3.amazonaws.com/sifive%2F9f6a7dba-1f4a-467f-af83-bb99f5c7ee26_singapore-2019.jpg)
	
![Image Title](https://prismic-io.s3.amazonaws.com/sifive%2F8cf2f212-22b6-4cd4-a4fc-560f13d1f794_pan-gyo-2019.jpg)
	
![Image Title](https://prismic-io.s3.amazonaws.com/sifive%2F268f9fa3-4b02-444c-902d-d68350d2b5b0_hsinchu-2019.jpg)
	
![Image Title](https://prismic-io.s3.amazonaws.com/sifive%2Ffa8ecf65-1ba0-47dd-a38c-c73d4346aa47_japan-2019.jpg)
	
![Image Title](https://prismic-io.s3.amazonaws.com/sifive%2Fd27e8858-0d31-4c23-a559-bebed38d6bee_sydney-2019.jpg)

The Design Revolution in APAC and Australia

The Information age transformed the world, fueled by silicon chips that became more powerful and more cost-effective every 18 months. The thinking of silicon design was led by engineers in the pursuit of faster, smaller transistors. As the Experience Age transcends the Information Age, the law underneath the technology changes from what’s possible, to what’s needed. Now, the ability to create purpose-built processors – secure, fast, efficient, and cost-effective – is the defining characteristic inside products that change lives through improved experiences and abilities. 

Today, SiFive is proud to announce the SiFive quarterly update program, filled with the latest innovations and features. Based on RISC-V cores, SiFive offers a portfolio of RISC-V based domain specific acceleration SoCs and application processors, and cloud-based fully custom core design services. The Q2 2019 engineering update delivers new features and options across the breadth of the SiFive portfolio, and is available in Core IP products configured via Core Designer and the Freedom Tool suite products.
If this program sounds more like a software company roadmap than a hardware one, you’re right:  SiFive is extending the experience-first concept of the Experience Age to the process of silicon customization and design. The rapid integration of feature updates and improvements to processors is made possible by SiFive’s approach that creates fully synthesized SoC designs that can be quickly validated to accelerate time to market for domain specific tasks. 

Whether you’re working on inference processing, networking, creating a tiny embedded IoT chip with high density code, or simply need a secure, scalable application processor, you can rely on SiFive to deliver the IP, designs, services, validation, and experience you need to get it done. 

As the leader in RISC-V enablement, SiFive’s mission is to make specialized silicon design simple, fast, and efficient. SiFive will deliver Innovation updates on a quarterly basis to enable innovators needing new custom silicon designs. For IP companies looking for new opportunities to offer their world-class portfolio, SiFive becomes the marketplace to enable mass customization of silicon by offering easy-to-access, efficient pre-integrated solutions.

Read the companion blogs by SiFive experts to learn more about the specific changes included in the Q2 2019 SiFive engineering update for [SiFive Core IP](https://www.sifive.com/blog/when-hardware-roadmaps-look-like-software-roadmaps), [SiFive Core Designer](https://www.sifive.com/blog/sifive-core-designer-adds-three-new-core-series), and the [Freedom Tools](https://www.sifive.com/blog/freedom-in-software-and-in-the-metal) suite.
The ability to intelligently collect, process, and analyze data in the growing Internet of Things ecosystem will be the key to success in the new era of computing - partner with SiFive today and unlock your vision for the Experience Age!


With the move to a quarterly release program (see: [Silicon At Speed Of Software](https://www.sifive.com/blog/silicon-at-the-speed-of-software)), SiFive is innovating in the hardware space at an unprecedented pace. In the [SiFive Core Designer update](https://www.sifive.com/blog/sifive-core-designer-adds-three-new-core-series) and the [Core IP update](https://www.sifive.com/blog/when-hardware-roadmaps-look-like-software-roadmaps) we learned about new features being added to SiFive Core IP and the ability to quickly access those features via [SiFive Core Designer](https://scs.sifive.com/core-designer/), SiFive's Software-as-a Service (SaaS) application. We have also been hard at work making sure that our software enablement is just as configurable, and easy to access, as our hardware.

[Freedom Metal](https://github.com/sifive/freedom-metal) is a portable, bare-metal environment which exposes convenient software interfaces for controlling SiFive Core IP features and SiFive peripheral devices. We first released the beta of Freedom Metal in Q1 and have since been hard at work improving the interfaces and adding the necessary new feature support for the Q2 update. Some examples of the new features in Freedom Metal are: 

- **Multicore Boot** - Freedom Metal is now multi-core aware to support the new SiFive Core Designer ability to generate multi-core embedded devices.  
- **RV32E support** - Freedom Metal also supports the RV32E extension added to the E2 Series, extending SiFive core market reach to extremely area constrained design points requiring the use of reduced integer register count microarchitectures. 
- **User Mode and PMP API** - SiFive’s embedded devices can be configured to support RISC-V’s User Mode. Freedom Metal now supports the ability to create and enter a User Mode context via a Freedom Metal API calls along with driver support for programming PMP regions.

What makes Freedom Metal so special is that any software written against its API will work on any device which has a Freedom Metal Board Support Package (BSP). SiFive offers a tool which automatically generate BSPs based on [Device Tree Files](https://github.com/sifive/freedom-devicetree-tools). Using this tool, we are able to automatically generate Freedom Metal BSPs for all SiFive Core IP created with SiFive Core Designer. With the Q2 2019 update, we will be packaging Freedom Metal BSPs with all SiFive Core IP products ensuring software compatibility with Freedom Metal.

Building on top of Freedom Metal is **Freedom E SDK**, our command-line based software development kit. The Freedom E SDK is intended to make software development on SiFive devices as simple as possible by featuring a collection of Freedom Metal-based examples, Freedom Metal BSPs for SiFive development boards, scripts, utilities, and makefiles. In the Q2 2019 Freedom E SDK release we have updated the bundled Freedom Metal BSPs and added a number of new examples including:

- **Benchmarks** - Dhrystone and Coremark examples for easy replication of SiFive benchmark scores
- **Multicore Hello** - Demonstrates booting a multicore SiFive target
- **User Mode** - Demonstrates dropping down into user-mode via Freedom Metal API calls
- Many more

Freedom Metal BSPs included with SiFive Core IP deliverables feature Freedom E SDK examples tailored to a given design. For example, if a Core IP design doesn’t have User Mode, then the bundled Freedom E SDK will not include the User Mode example. Focusing SDK examples on the capabilities of the Core IP speeds understanding of capabilities and saves time.

**Freedom Studio** coherently encompasses the entire software experience together, building on top of Freedom Metal and Freedom E SDK. Freedom Studio provides an Eclipse based IDE along with all of the necessary toolchains and utilities pre-built for your OS of choice. As part of the Q2 2019 update SiFive has developed single-click access to the Freedom E SDK new project wizard. 

Getting starting writing code for SiFive devices is simple with the included QEMU based simulator with 32-bit and 64-bit target. Freedom Studio is your one-stop [download](https://www.sifive.com/boards) for software development for SiFive devices be it core IP, FPGA, and/or develop board targets. SiFive offers access to all toolchains and utilities from source in the [Freedom Tools](https://github.com/sifive/freedom-tools) repository on Github along with all of the necessary build scripts. 

For the Q2 2019 engineering update SiFive focused on the end-user and out-of-the-box experience which resulted in a strong focus on software for SiFive products. The Q2 2019 software update will result in a great user experience and allow for our partners to make some truly incredible products!


SiFive Core Designer (SCD) unlocks new possibilities by enabling engineers to explore the architectural design space of a CPU. With our [Software-as-a Service (SaaS) application](https://scs.sifive.com/core-designer/), customers can create and customize RISC-V core IP -- from their laptops.

Working within a Core Series (a “class” of Core paired with a specific microarchitecture) customers can rapidly create a range of cores at different design points, run software applications on FPGA bitstreams, simulate with RTL, and ultimately determine the best custom silicon for their product. [Explore SiFive Core Designer](https://scs.sifive.com/core-designer/).

## INTRODUCING QUARTERLY UPDATES
Today we are announcing the [SiFive Quarterly Update Program](silicon-at-the-speed-of-software), which is designed to “stream” SiFive’s latest innovations and features to customers. With today’s Q2 2019 engineering update, we’re expanding the available Core Series in SiFive Core Designer and adding a number of [compelling new core IP features](when-hardware-roadmaps-look-like-software-roadmaps).

## ADDING THREE NEW CORE SERIES TO SCD
With the addition of the **E7, S7, and S2 Core Series** to SiFive Core Designer, E and S cores (32-bit and 64-bit embedded cores, respectively) can be customized across all SiFive microarchitectures. *U cores (64-bit application cores) will be added to SCD in a subsequent quarterly update.* 

![Graphic](https://prismic-io.s3.amazonaws.com/sifive%2F9dcec28d-f08e-4da9-8485-3ea31cd654bf_sifive_blogimagefinal.png)

## 7 Series: E7, S7
With an 8-stage, dual-issue superscalar pipeline and a scalable throughput provided by 8 cores per cluster, the 7 Series is SiFive’s highest-performance microarchitecture. [Read more about the 7 Series](https://www.sifive.com/press/sifive-core-ip-7-series-creates-new-class-of-embedded).

The **E7 and S7 Core Series** offer 32-bit and 64-bit embedded processors targeting applications that require high performance while maintaining energy efficiency.

## 2 Series: S2
Edge SoCs (System on Chip) face the diverse requirements of real-time latency, deterministic capability, and stringent power constraints. The 2 Series enables SoCs to have an always-on, low power CPU that can be combined with high-performance CPUs that switch on only when applications demand performance, such as in voice-activated smart devices. The 2 Series can be configured to be as small as just 13,500 gates (in RV32E form).

The **S2 Core Series** brings a 64-bit architecture to SiFive’s smallest microcontrollers. An S2 core is just half the size of a similarly configured S5 core. [Read more about the S2 Core Series](https://www.sifive.com/press/sifive-launches-the-worlds-smallest-commercial-64-bit).

## NEW CORE IP FEATURES
This quarter, we’ve rolled in a new set of core IP features, which are available and configurable from SiFive Core Designer.

**New to all Core Series:**
* **SCIE (SiFive Custom Instruction Extension):** Add RISC-V-compatible custom instructions

**New to 2 Series:**
* **RV32E (RISC-V ISA Extension):** Create a minimal E2 core (as small as 13.5k gates)
* **μInstruction Cache:** More efficient performance in memory-constrained designs

**New to 3, 5 Series:**
* **Multicore:** Choose up to 8 cores
* **Floating Point:** Single-precision and double-precision FP
* **L2 Cache:** optional second-level cache

**New to 7 Series:**
* **Multicore:** Choose up to 8 cores
* **Fast IO:** Maximizes IO throughput
* **DLS (Data Local Store):** Quick memory access for the Data Bus
* **ITIM (Instruction Tightly-Integrated Memory):** Quick memory access for the Instruction Bus

[Read more about core IP features](when-hardware-roadmaps-look-like-software-roadmaps) included in the Q2 engineering update.

## ENHANCED CORE DESIGNER DEVELOPMENT KIT
We’ve included the [Freedom E SDK](https://github.com/sifive/freedom-e-sdk) (and [Freedom Metal](https://github.com/sifive/freedom-metal) software examples) in every custom core Development Kit built by the Core Designer. As part of the Q2 engineering update, we’ve added the following examples:

* **Benchmarks:** Dhrystone and Coremark examples permit replication of SiFive benchmark scores
* **Multicore Hello:** Demonstrates booting a multicore target
* **User Mode:** Demonstrates entering user-mode via Freedom Metal API calls

Now, along with [Freedom Studio](https://www.sifive.com/boards), our Eclipse-based IDE, it’s never been easier to develop software for cores built by SiFive Core Designer. Read more about our software toolchain in the [Q2 engineering update software blog](freedom-in-software-and-in-the-metal).

## SIFIVE SHIPS -- EVERY QUARTER
Rolling up SiFive’s products into a single update each quarter ensures that customers receive a complete end-to-end hardware/software development experience that regularly delivers innovation. We’re looking forward to shipping powerful new features in SiFive Core Designer as part of the Q3 2019 engineering update.




Three New Core Series Now Available in SiFive Core Designer

The traditional cadence for microarchitecture updates is usually tied to process technology nodes or ground-up redesigns. The SiFive Core IP portfolio offers scalable microarchitectures from efficient application multi-core processors capable of running Linux, to tiny, power-sipping cores suitable for the most area constrained design points. The SiFive quarterly update program delivers key improvements, new features, and more capabilities to SiFive Core IP in a measured, methodical way. Here’s all the information you need on the SiFive Core IP Series and the latest updates!

## 2 Series
Since launching the 2 Series in June of 2018 (see: [SiFive Unveils E2 Core IP Series for Smallest, Lowest Power RISC-V Designs](https://www.sifive.com/press/sifive-unveils-smallest-lowest-power-risc-v-designs)), it has quickly become our most popular Core Series. This quarter we have made a number of enhancements that will make the 2 Series even better! 

The biggest update being the introduction of the **S2 Series**, the world's smallest commercial 64-bit embedded core. The S2 greatly simplifies integration of small management cores into larger 64-bit SoCs with its ability to directly address a large address space.

Speaking of small, this quarter’s release also brings support for the **RV32E** RISC-V standard to the E2 Series. RV32E reduces the integer register-file of a RISC-V CPU from 32 integer registers to just 16 integer registers. The RV32E option can reduce area by up to 25% on the already small E2 series while only having a marginal impact on most benchmarks. Adopting the RV32E standard allows for area conscious E2 cores to be configured as small as 13.5k gates. 

We are also introducing an optional **μInstruction Cache** on the 2 Series allowing for higher and more efficient performance in memory-constrained designs, such as those with off-chip serial flash. This option is available on both the E2 and S2 Core Series.

## 7 Series
The 7 Series has been well-received since being launched in October of 2018 (see: [SiFive Core IP 7 Series Creates New Class of Embedded Intelligent Devices Powered by RISC-V](https://www.sifive.com/press/sifive-core-ip-7-series-creates-new-class-of-embedded)), when it set the bar for performance of in-order cores. Thanks to optimizations in both the hardware and the compiler, performance in the popular Coremark benchmark has been increased _from 4.9 Coremarks/MHz to 5.1 Coremarks/MHz_, further raising the bar.

In addition to benchmark improvements, we have also added a number of features to the E7 and S7 memory subsystems. **Fast IO** option enables better IO throughput by optimizing the 7 Series pipeline for memory mapped operations over max frequency and cached data operations. The **Data Local Store** (DLS) gives the 7 Series data bus quick access to local, but globally addressable, memory which can exist in addition to a data cache or DTIM. 

Lastly we brought an **ITIM**, directly and globally addressable Tightly Integrated Memory on the instruction bus, to the 7 Series which is instantly accessible by the core. The 7 Series ITIM can be paired with an L1 Instruction Cache, which now also has a special minimal configuration for applications mainly requiring directly-addressed memory such as that provided by the ITIM and DTIM.

## SiFive Custom Instruction Extension (SCIE)
At the heart of RISC-V is the ability to build customized, application-specific features on top of the well-defined base ISA in order to meet application-specific requirements, while still maintaining compatibility with the rapidly-expanding RISC-V software ecosystem. **SCIE** gives SiFive customers the ability to quickly and easily add custom instructions to all SiFive Core IP offerings using Verilog and familiar workflows. SCIE also takes care not to break compatibility with the RISC-V ecosystem by taking advantage of the custom-0 and custom-1 opcode space provided by the RISC-V ISA.

## Relentless Innovation
At SiFive we care about the entire user experience, from the performance of our offering to the ease of use. One of the things that makes SiFive’s design process unique is the Silicon as a Service offering SiFive Core Designer (SCD). Using SCD via the easy-to-use web interface, our customers can quickly explore the design space of our Core IP offerings and download designs ready for synthesis and software benchmarking on FPGAs. Learn more about what is new with the [SiFive Core Designer](https://www.sifive.com/blog/sifive-core-designer-adds-three-new-core-series) and the [Freedom Tools Suite](https://www.sifive.com/blog/freedom-in-software-and-in-the-metal) updates.

When Hardware Roadmaps Look Like Software Roadmaps

*Join SiFive Tech Symposiums in Tokyo, Daejeon, Pangyo, Hsinchu, Singapore and Sydney*


As we make our way around the world meeting and engaging with others in the semiconductor and hardware design community, we are seeing an increased interest in RISC-V based hardware innovation. This is due in large part to the emergence of  market-ready RISC-V core IP, development tools and silicon solutions based on cloud-based design platforms that facilitate the creation of custom SoC solutions for edge computing, AI, IoT, wearable, server and other target vertical markets.

Having just completed an exciting tour through Europe, we&#39;re gearing up for our visit to the APAC region and Australia, which will take place throughout the month of June. If you live in the region, or will be visiting, you won&#39;t want to miss this. Here is a glimpse of what&#39;s in store for attendees. For more details, and to register to attend any of our great symposiums, please visit [www.sifivetechsymposium.com](http://www.sifivetechsymposium.com)

**Tokyo Highlights**

Software Hardware Consulting Group, a company specializing  in FPGA and SoC microcontroller IP solutions, embedded security, voice, speech, wired and wireless connectivity, will be our co-host. This symposium will take place on Tuesday, June 11 and includes keynotes by Huzefa Cutlerywala, VP of sales (APAC) for SiFive, and Shumpei Kawasaki, CEOof Software Hardware Consulting Group. There will also be presentations by our customer, QuickLogic, and ecosystem partners, including DTS Insight, IAR Systems and Rambus. Attendees will also have an opportunity to see demonstrations and learn about the latest design platforms for RISC-V based SoCs, development boards, IP, software and more. For more information, and to register for the symposium in Tokyo, please visit: [https://sifivetechsymposium.com/agenda-tokyo/](https://sifivetechsymposium.com/agenda-tokyo/)

**Daejeon Highlights**

The Korea Advanced Institute of Science and Technology (KAIST) will be our co-host. This symposium will take place on Monday, June 17 and will include presentations from Yunsup Lee, alumni of KAIST and co-founder and CTO of SiFive, and Keith Witek, SVP corporate development and strategy at SiFive. There will be presentations by our partners, IAR Systems, UltraSoC and OpenEdges Technology, as well as other companies, including Samsung and FuriosaAI. Attendees will also have an opportunity to see demonstrations and learn about the latest design platforms for RISC-V based SoCs, development boards, IP, software and more. For more information, and to register for the symposium in Daejeon, please visit: [https://sifivetechsymposium.com/agenda-daejeon/](https://sifivetechsymposium.com/agenda-daejeon/)

**Pangyo Highlights**

The Korea Semiconductor Industry Association (KSIA) will be our co-host. This symposium will take place on Tuesday, June 18, and will include presentations from Yunsup Lee co-founder and CTO of SiFive, and Keith Witek, SVP corporate development and strategy at SiFive. There will also be presentations by many ecosystem partners, including UltraSoC, Rambus, OpenEdges Technology, Hancom MDS and IAR Systems, as well as other companies, including Samsung and FuriosaAI. Attendees will also have an opportunity to see demonstrations and learn about the latest design platforms for RISC-V based SoCs, development boards, IP, software and more. For more information, and to register to attend the symposium in Pangyo, please visit: [https://sifivetechsymposium.com/agenda-pangyo/](https://sifivetechsymposium.com/agenda-pangyo/)

**Hsinchu Highlights**

Microchip and ACTT are our co-hosts in Hsinchu. This event will take place on Tuesday, June 18, and features a great lineup of speakers. There will be keynotes by Thomas Xu, the CEO of SiFive China, Jianjun Xiang, CEO of ACTT, Vishakh Rayapeta, applications engineer at Microchip, Christopher Moezzi, VP and GM AI/ML Solutions BU of SiFive, and Jimmy Hu, VP of R&amp;D at SiFive China. There will also be presentations by Imagination Technologies, Industrial Technology Research Institute and Rambus. Attendees will also have an opportunity to see demonstrations and learn about the latest design platforms for RISC-V based SoCs, development boards, IP, software and more. For more information, and to register to attend the symposium in Hsinchu, please visit: [https://sifivetechsymposium.com/agenda-hsinchu/](https://sifivetechsymposium.com/agenda-hsinchu/)

**Singapore Highlights**

This symposium will take place on Wednesday, June 19, and will be hosted at the prestigious National University of Singapore. Some of the highlights include keynote presentation by Huzefa Cutlerywala, VP of sales APAC at SiFive, and presentations by Anand Bariya, VP of engineering at SiFive, and Trevor Carlson, assistant professor at the National University of Singapore. There will also be myriad presentations by industry veterans and luminaries. Attendees will also have an opportunity to see demonstrations and learn about the latest design platforms for RISC-V based SoCs, development boards, IP, software and more. For more information, and to register to attend the symposium in Singapore, please visit: [https://sifivetechsymposium.com/agenda-singapore/](https://sifivetechsymposium.com/agenda-singapore/)

**Sydney Highlights**

Morse Micro will be our co-host in Sydney. This symposium will take place on Friday, June 21. Some of the highlights include keynote presentations by Huzefa Cutlerywala, VP of sales APAC at SiFive, and Michael De Nil, co-founder of Morse Micro. There will also be a presentation by Anand Bariya, VP of engineering at SiFive and a member of the faculty at the research lab at the University of Sydney, as well as myriad presentations by industry veterans and luminaries. Attendees will also have an opportunity to see demonstrations and learn about the latest design platforms for RISC-V based SoCs, development boards, IP, software and more. For more information, and to register for the symposium in Sidney, please visit: [https://sifivetechsymposium.com/agenda-sydney/](https://sifivetechsymposium.com/agenda-sydney/)

The RISC-V Revolution is Sweeping Across the APAC Region and Australia

We just wrapped up our six-city tour in Europe, which included Cambridge, Grenoble, Stockholm, Moscow, Munich and Amsterdam. Together with our co-hosts, Qamcom, Syntacore, Imagination Technologies and Mentor; and ecosystem partners, Rambus, IAR Systems, UltraSoC, Antmicro, SecureRF, Credo and lowRISC, we engaged with over 500 responses/registrations throughout the tour. 

One of the highlights was having people from the audience come onto the stage and use SiFive&#39;s Core Designer to build their own customized CPU core on the fly. They were able to accomplish this task very quickly and easily and also walk away with a design that will deliver the precise results they wanted. 

Another highlight was hearing about the RISC-V based research taking place at Europe&#39;s premier academic institutions. We heard from lecturers, professors, researchers and students from many schools including the University of Cambridge Computer Laboratory, the LCIS Laboratory at the Grenoble Institute of Technology (Grenoble INP), KTH at The Royal Institute of Technology, Ivannikov Institute for System Programming of the Russian Academy of Sciences (ISP RAS), and Munich University of Applied Sciences. 

We were incredibly happy to share the stage with our co-hosts and ecosystem partners, and to have them share their ideas, innovations and solutions. The level of interactive engagement between the presenters and audience is always inspiring. As you can see in the photos, there was a lot of energy and collaboration, which of course is the cornerstone of the RISC-V ISA. These events have also proven to be an excellent opportunity for showcasing the SaaS-based approach that is democratizing access to the custom cores, design platforms and custom SoC solutions for emerging applications. 

We&#39;d like to thank each of our co-hosts and partners for joining us in fostering education, innovation, networking and idea sharing within the global open-source community. We are grateful for their support and to share in the collaborative success that open source brings to the hardware community. 

Throughout the month of June, we are hosting SiFive Tech Symposiums in the Asia-Pacific region and Australia. To learn more, or to register for the event closest to you, please visit [sifivetechsymposium.com](https://sifivetechsymposium.com/).

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The Design Revolution in Europe: Highlights From the SiFive Tech Symposiums

## Hello Cambridge, Grenoble, Stockholm, Moscow, Munich and Amsterdam
Our 2019 global symposiums and workshops have been hugely successful in promoting the RISC-V ISA and fostering expansive collaboration within the open-source community. It&#39;s invigorating to see how the worldwide semiconductor ecosystem is energized and mobilized by the open ISA. One of the areas receiving the most attention is embedded intelligence. The RISC-V ISA is enabling designers and innovators to actively pursue solutions that employ enhanced embedded intelligence at the edge. The real-world applications of this are awesome and we are inspired by what we see!

The next leg of our tour is taking us to six cities in Europe. We&#39;re so excited to meet the brilliant minds in and around Cambridge, Grenoble, Stockholm, Moscow, Munich and Amsterdam!

## Cambridge Highlights  
Imagination Technologies is our co-host in Cambridge. The symposium will take place on Monday, May 13, and includes a great lineup of speakers, tutorials and demonstrations. There will be keynotes by Naveed Sherwani, CEO of SiFive, and Andrew Grant, senior director of vision and AI at Imagination Technologies. There will also be presentations by Krste Asanovic, chairman of the board at the RISC-V Foundation, a member of the faculty from the computer laboratory at the University of Cambridge, IAR Systems, SecureRF and lowRISC. Attendees will also have an opportunity to see demonstrations and learn about the latest design platforms for RISC-V based SoCs, development boards, IP, software and more. For more information on the Cambridge event, please visit: [https://sifivetechsymposium.com/agenda-cambridge/](https://sifivetechsymposium.com/agenda-cambridge/)

## Grenoble Highlights  
This symposium will take place on Wednesday, May 15. There will be presentations by Krste Asanovic, chairman of the board at the RISC-V Foundation, a graduate student from the LCIS laboratory at Grenoble INP, and presentations by SecureRF and other ecosystem partners. Attendees will also have an opportunity to see demonstrations and learn about the latest design platforms for RISC-V based SoCs, development boards, IP, software and more. For more information on the Grenoble event, please visit: [https://sifivetechsymposium.com/agenda-grenoble/](https://sifivetechsymposium.com/agenda-grenoble/)

## Stockholm Highlights 
With Qamcom as our co-host, this event will take place on Friday, May 17, and will include a powerful lineup of speakers. There will be keynotes by Krste Asanovic, co-founder and chief architect at SiFive, and Olof Kindgren, senior digital design engineer at Qamcom. There will also be presentations by a professor at KTH, The Royal Institute of Technology, IAR Systems, Antmicro and other ecosystem partners. Attendees will also have an opportunity to see demonstrations and learn about the latest design platforms for RISC-V based SoCs, development boards, IP, software and more. For more information on the Stockholm event, please visit: [https://sifivetechsymposium.com/agenda-stockholm/](https://sifivetechsymposium.com/agenda-stockholm/)

## Moscow Highlights  
SiFive and Syntacore are jointly hosting the symposium in Moscow on Monday, May 20. It will feature several presentations by key industry veterans and luminaries. There will be keynote presentations by Alexander Redkin, CEO of Syntacore, and Krste Asanovic, co-founder and chief architect at SiFive. There will also be presentations by IAR Systems, UltraSoC and other ecosystem partners. A lead researcher from ISP RAS (Russian Academy of Sciences) will also be presenting. Attendees will also have an opportunity to see demonstrations and learn about the latest design platforms for RISC-V based SoCs, development boards, IP, software and more. For more information on the Moscow event, please visit: [https://sifivetechsymposium.com/agenda-moscow/](https://sifivetechsymposium.com/agenda-moscow/)

## Munich Highlights  
Mentor is our co-host in Munich. This event will take place on Thursday, May 23, and features a great lineup of speakers. There will be a presentation by Krste Asanovic, chairman of the board for the RISC-V Foundation, and keynote presentations by Sunil Shenoy, senior vice president and general manager of the RISC-V Business Unit at SiFive, and Petri Solanti, senior field applications engineer at Mentor. There will also be presentations by IAR Systems, Rambus and other ecosystem partners. Attendees will also have an opportunity to see demonstrations and learn about the latest design platforms for RISC-V based SoCs, development boards, IP, software and more. For more information on the Munich event, please visit: [https://sifivetechsymposium.com/agenda-munich/](https://sifivetechsymposium.com/agenda-munich/)

## Amsterdam Highlights 
This symposium will take place on Wednesday, May 29. Some of the highlights include a keynote presentation by Sunil Shenoy, senior vice president and general manager of the RISC-V Business Unit at SiFive. There will also be presentations by Imagination Technologies and other ecosystem partners. Attendees will also have an opportunity to see demonstrations and learn about the latest design platforms for RISC-V based SoCs, development boards, IP, software and more. For more information on the Amsterdam event, please visit: [https://sifivetechsymposium.com/agenda-amsterdam/](https://sifivetechsymposium.com/agenda-amsterdam/)

The SiFive Tech Symposiums are Heading to Six Cities in Europe in May!

![Freedom Studio](https://prismic-io.s3.amazonaws.com/sifive%2F18b2cbd9-97b8-4084-9a16-ae4193d6f6b7_splash.png)

Ever since we launched Freedom Studio in 2017, it has been a great way to quickly and easily get started writing code for SiFive platforms, whether those platforms are development boards such as the [HiFive1 Rev B](https://www.crowdsupply.com/sifive/hifive1-rev-b), [Digilent Arty FPGA](https://store.digilentinc.com/arty-a7-artix-7-fpga-development-board-for-makers-and-hobbyists/), or even our testbench, which ships along with SiFive IP deliverables.
Freedom Studio is based on the industry-standard Eclipse IDE and comes with several plugins and pre-built tools supporting Windows, macOS, and Linux, to help with embedded development for SiFive platforms.
While the tools included in Freedom Studio have always been open-source, we have also decided to open-source our build scripts as well, which can be found in the [Freedom Tools](https://github.com/sifive/freedom-tools) repository.

This release of Freedom Studio brings significant under-the-hood enhancements in addition to several new user-facing changes. 
In this blog, I will highlight several of these changes.

## Freedom-E-SDK Integration 

[Freedom-E-SDK](https://github.com/sifive/freedom-e-sdk) is a GitHub repository that contains a command-line driven workflow for targeting SiFive's embedded platforms.
One of the strengths of SiFive's RISC-V Core IP is the ability to customize a certain product to meet the requirements of a specific application.
A number of these configuration options can directly affect software development, such as the RISC-V ISA extensions implemented, memory map, included peripherals, and so on.
In order to accommodate bare-metal software development on such a wide variation of hardware targets, we have been busy developing a new API we call Freedom Metal.
Freedom-E-SDK has now been integrated with Freedom Metal and contains examples targeting the Freedom Metal API and Freedom Metal BSPs for all of our Standard Cores and development boards.
Look for a future blog specifically on Freedom Metal; until then, feel free to check out the Freedom Metal documentation [here](https://sifive.github.io/freedom-metal-docs/index.html).

How does this relate to Freedom Studio?
Until now, Freedom Studio has contained examples that were snapshots of certain projects in Freedom-E-SDK.
In the 2019.03 release of Freedom Studio, however, we now have much tighter integration between Freedom-E-SDK and Freedom Studio.
Freedom Studio is now, quite literally, an Eclipse front end to running Freedom-E-SDK projects and Makefiles.

The new project dialog now has an option for a *Freedom-E-SDK Project*.

![New Project Dialog](https://prismic-io.s3.amazonaws.com/sifive%2Fb4dc8150-65b6-4121-a18b-58ebdaa87e8a_new_proj.png)

This project type allows you to select any of the targets supported by Freedom-E-SDK as well as any of the examples in Freedom-E-SDK.
Note also that Freedom-E-SDK has BSPs for SiFive's RTL deliverables now allowing for Freedom-E-SDK examples to be run directly on our IP testbenches.

What is great about this integration between Freedom-E-SDK and Freedom Studio is that we have the ability to automatically generate Freedom Metal BSPs from SiFive Core Designer deliverables thereby allowing Freedom Studio (and Freedom-E-SDK) to target any IP delivered by SiFive.
Please see the Application Note [Custom Core Software Getting Started Guide](https://prismic-io.s3.amazonaws.com/sifive%2F7ed5fcaa-d390-4c9f-aa55-c79fcebf6ee7_custom-core-software-getting-started-guide-v1.0.pdf) for details on how to do this.
We will continue to streamline this process in the near future.

## Programming Arty Boards Directly from Freedom Studio

SiFive's Standard Cores and SiFive Core Designer deliverables include FPGA bitstreams which wrap our RISC-V Core IP deliverables with a peripheral sub-system, making it suitable for immediate software development. 
We currently target the [Digilent Arty](https://store.digilentinc.com/arty-a7-artix-7-fpga-development-board-for-makers-and-hobbyists/) line of FPGAs due to their low-cost, capacity, and availability.

In order to streamline the process of evaluating SiFive IP, we now have the ability to program the Arty A7-35T and A7-100T boards directly from Freedom Studio greatly simplifying the evaluation process.

![FPGA Flash Utility](https://prismic-io.s3.amazonaws.com/sifive%2Fd27cd26b-df01-4a39-9001-d14ddd1efde8_fpga_flasher.png)

## SEGGER JLINK Support Built In

SEGGER has been one of the earliest and strongest supporters of RISC-V in the tools ecosystem supporting SiFive devices as early as [September 2017](https://www.segger.com/news/segger-adds-support-for-sifives-coreplex-ip-to-its-industry-leading-j-link-debug-probe/).
When developing the newly launched [HiFive1 Rev B](https://www.crowdsupply.com/sifive/hifive1-rev-b) we were excited about the possibility of adding a [SEGGER JLINK](https://www.segger.com/products/debug-probes/j-link/) probe directly on the board.
This has several benefits including JLINK's legendary debug performance as well drag-and-drop programming capabilities.
Freedom Studio has had built-in support for JLINK probes for some time, however, in order to make development on the HiFive1 Rev B as easy as possible, we now include SEGGER's JLINK debug software directly in Freedom Studio.


## Available Today

Freedom Studio 2019.03 is available today for all 3 major Operating Systems at [https://www.sifive.com/boards](https://www.sifive.com/boards). Please visit our [Forums](https://forums.sifive.com/) and let us know what you think.

During the afternoon session of the Symposium, Jack Kang, SiFive VP sales then addressed the RISC-V Core IP for vertical markets from consumer/smart home/wearables to storage/networking/5G to ML/edge. Embedding intelligence from the edge to the cloud can occur with U Cores 64-bit Application Processors, S Cores 64-bit Embedded Processors, and E Cores 32-bit Embedded Processors. Embedded intelligence allows mixing of application cores with embedded cores, extensible custom instructions, configurable memory for application tuning and other heterogeneous combination of real time and application processors. Some recently announced products is Huami in Wearable AI, Fadu SSD controller in Enterprise, Microsemi/Microchip upcoming FPGA architecture. Customization comes in 2 forms, customization of cores by configuration changes and by custom instructions in a reserved space on top of the base instruction set and standard extensions, guaranteeing no instruction collision with existing or future extensions, and preserving software compatibility.

Palmer Dabbelt, SiFive Software lead manager, compared the complexity of x86 instructions to the simplicity of RISC-V. The current state of RISC-V specifications includes:

- User Mode ISA spec: M extension for multiplication, A extension for atomics, F and D for single and double precision floating point, C extension for compressed 16-bit
- Privileged Mode ISA spec: Supervisor, Hypervisor, Machine modes
- External Debug spec: Debug machine mode software over JTAG

Some resources are listed below 1.

Mohit Gupta, SiFive VP SoC IP, covered the SoC IP solutions for vertical markets. SoC/ASIC design is nowadays turning into an IP integration task for cost and design cycle time reasons. No single memory technology is applicable to all designs; power, bandwidth, latency tradeoffs are needed for each custom requirement; SerDes interfaces vary by application and selection is based on power and area optimization. The DesignShare partners provide their differentiated IP at no initial cost for verification and integration, built on top of RISC-V cores and foundational IP helping the development cost and reducing needed expertise.

Krste Asanovic, SiFive Co-Founder and Chief Architect, outlined the Customizable RISC-V AI SoC Platform.

![Image Title](https://prismic-io.s3.amazonaws.com/sifive%2F562a19eb-e58f-4880-b79d-022739bfc9c1_1-si5_12_n.jpg)
![Image Title](https://prismic-io.s3.amazonaws.com/sifive%2F80879cc0-2211-40d4-9478-5d80902a3f62_2-si5_13_n.jpg)

The AI accelerator design metrics for &#39;inference at the edge&#39; are cost/performance/power; for &#39;inference in the cloud&#39; latency, throughput/cost matter most. For &#39;training in the cloud&#39;, the only metric that matters is performance.

In order to lower cost, power and service latency, Unix Servers can be dropped and replaced by self-hosting accelerator engines along SiFive RISC-V Unix multi-cores.

SiFive&#39;s Freedom Revolution consists of:

- High-bandwidth AI and networking applications in TSMC 16nm/7nm
- SiFive 7-series RISC-V processors with vector units
- Accelerator bays for custom accelerators
- Cache-coherent TileLink interconnect
- 4-3.2 Gb/s HBM2 memory interface
- 28-56-112 GBs SerDes links
- Interlaken chip-to-chip protocol
- High speed 40+ Gb/s Ethernet

In development E7/S7/U7vector and custom extensions, accelerator bays, 3.2 Gb/s HBM2 in 7nm and higher performance RISC-V processors.

Jay Hu, CEO DinoplusAI, rounded out the presentations&#39; portion of the Symposium. He provided a market overview that showed Deep Learning ASIC having the highest growth

He emphasized that 5G Edge cloud computing and ADAS/Autonomous driving require predictable and consistent ultra-low latency (~0.2ms ResNet 50), high performance and high reliability high precision inference (the CLEAR diagram summarizes the technology platform and positioning).

DinoplusAI provided a latency comparison with NVIDIA Tesla V100 and Google TPU 2

![Image Title](https://prismic-io.s3.amazonaws.com/sifive%2Fb9ac2655-6db7-46c4-acab-d267fcf896ae_3-si5_14_n.jpg)
![Image Title](https://prismic-io.s3.amazonaws.com/sifive%2Fd0b6c3ec-0ad5-42bf-8df5-7e0efffb50d7_4-si5_15_n.jpg)
![Image Title](https://prismic-io.s3.amazonaws.com/sifive%2F44c8396b-358d-4554-9f12-bb871b85d2f4_5-si5_16_n.jpg)

\_\_\_
[1] Software Resources: [Fedora](https://fedoraproject.org/wiki/Architectures/RISC-V), [Debian](https://wiki.debian.org/RISC-V), [OpenEmbedded/Yocto](https://github.com/riscv/meta-riscv), [SiFive blog](/blog)

**Part II**

(Part I can be found [here](https://www.semiwiki.com/forum/content/8066-revolution-evolution-continues-sifive-risc-v-technology-symposium-part-i.html))

The Revolution Evolution Continues - SiFive RISC-V Technology Symposium - Part II

## HiFive1 Rev B: The Second Generation HiFive1 Dev Board and the Freedom Everywhere SoC, FE310

When SiFive launched the FE310 and HiFive1 in 2016, the product received a very warm and enthusiastic reception. The project received much more attention and traction than we could have ever hoped for. We were nominated for two ACE awards and the HiFive1 team won “Design Team of the Year”. 

In the short period of time since we launched the HiFive1, we have seen new RTOSes, software stacks, toolchains, debuggers, mechanical cases, and dev kits in different form factors. SiFive is proud to see the growth of the RISC-V Revolution alongside fellow RISC-V Foundation platinum members such as Western Digital, Microchip, Google, Samsung, and NVIDIA. We want to thank the community for openly embracing the FE310 and HiFive1 and helping us to drive the adoption of the free and open RISC-V ISA. 

Last week, we launched an upgraded Freedom Everywhere SoC and corresponding development kit, the HiFive1 Rev B, powered by SiFive’s E31 CPU, the FE310-G002. A small yet mighty 68 mm x 51 mm, the HiFive1 Rev B can connect to Arduino-compatible accessories and is a great platform for real-time embedded applications.

Here’s what’s new . . .

In the chip, the FE310-G002, we have added:

- One hardware I2C
- An additional UART for a total of 2 UARTs
- An upgrade to RISC-V Debug Specification 0.13
- Always-on domain at 3.3V
- The ability to power-off the core power (1.8V) during sleep mode.

On the board, the HiFive1 Rev B, we:

- Added a Wi-Fi/Bluetooth module to enable more connected applications for FE310
- Upgraded the USB debug to a Segger J-Link
- Enabled USB drag-and-drop flash programming
- Removed the bidirectional level shifters, enabling the FE310 to drive the I/O pins (3.3V only) directly
- Changed to a 4 MB QSPI NOR from ISSI

Optimization and power savings at the edge for IoT devices also necessitate that developers not be unnecessarily frustrated by walled-off gardens. Critically, The FE310 is the first open source, commercially available RISC-V SoC.

Since 2016, the most frequently requested feature for our next embedded dev board has been wireless networking connectivity. On the HiFive1 Rev B, we have added a Wi-Fi / Bluetooth module from Espressif to enable the community to use the FE310 as a truly connected IoT device. 

Another new feature that we have enabled in partnership with Segger is the drag-and-drop flash programming. When the HiFive1 Rev B is plugged into a PC, it appears as a mass storage device and you can copy your compiled binary (hex) directly to the board. This dramatically simplifies the re-programming of the HiFive1 Rev B.

We also have enabled Zephyr RTOS to run on the FE310 and HiFive1 Rev B. All HiFive1 Zephyr apps are forward-compatible. With Zephyr RTOS, you get a complete execution environment with portable peripheral drivers for all hardware on the board. Zephyr’s SDK removes the pain points of toolchain management, as all the tools needed for porting are provided. Everything that Zephyr has to offer is available on our platform thereby allowing us to ship silicon and boards that run a full-featured, well-supported, community-driven real time operating system. 

We are proud of our robust little MCU and we hope that you will like it, too. The support of the open-source community has helped us build the most open commercial hardware available. Our dream has always been to democratize access to custom silicon and hardware. We absolutely cannot wait to see what new applications the [HiFive1 Rev B](https://www.sifive.com/boards/hifive1) and [FE310](https://www.sifive.com/core-designer#fe310) will be used for. We are especially excited to see how people might make the best use of the ability to power-off the core power during sleep mode. Optimizing power usage is a key feature for any IoT or connected device. We are thrilled to be able to put upgraded hardware and capabilities into the hands of all the innovators and RISC-V revolutionaries out there. 

You can preorder your HiFive1 Rev B today [here](https://www.crowdsupply.com/sifive/hifive1-rev-b).

Let us know what you come up with on [Twitter](https://twitter.com/sifive) or [LinkedIn](https://www.linkedin.com/company/sifive)!

Freedom Everywhere — Back for Everyone!

SiFive held a RISC-V Technology Symposium on February 26 at the Computer History Museum in Mountain View. Keith Witek, SiFive SVP Corporate Development and Strategy kicked off the event and introduced the first keynote speaker Martin Fink, Western Digital CTO, at the time acting CEO of the RISC-V Foundation (as of this writing, Calista Redmond was just appointed the new CEO of the RISC-V Foundation). He shared a slide showing the growing RISC-V ecosystem from tools vendors, to IP/semi chip providers and design/foundry services. He stated that, moving forward, the areas of focus will include standards/specs, ecosystem growth, awareness and education.

![Keynote speech](https://prismic-io.s3.amazonaws.com/sifive%2F71887697-780a-4518-8010-24849e277894_sifive1.png)
![Keynote speech](https://prismic-io.s3.amazonaws.com/sifive%2F5c709ea4-b7c6-48aa-8c51-9f5aa001c6a8_sifive2.png)

Sunil Shenoy, SVP RISC-V IP BU, outlined the SiFive elements of leading the semiconductor design revolution with a global presence and reach including 12 offices, 320+ employees and 300+ tape outs so far and expertise in cloud chip design, RTL, physical design, silicon and design platforms on top of having the nucleus of the key RISC-V inventors, and a deep pool of technical and management talent.

The industry adoption for RISC-V is growing from Western Digital’s transitioning of 1 Billion+ cores per year to RISC-V, NVIDIA’s all future GPUs using RISC-V, India adopting RISC-V as national ISA, US DARPA mandating RISC-V in recent security proposals. Design wins are occurring in microcontrollers, wearables, networking, communications and storage.

The current challenges in hardware designing minimum viable products include cost, time and expertise. Currently, a leading-edge technology node chip development costs $500M+ for 7nm, takes 2 to 4 years to develop and requires numerous experts in at least 14 disciplines.

In order to accelerate the innovation cycle addressing slow development, increased cost and increasing dependency on many experts, SiFive is reshaping the Silicon business by enabling free and open instruction set architecture, simplifying custom silicon development with templates and providing easy access allowing design in the cloud.

![Keynote speech](https://prismic-io.s3.amazonaws.com/sifive%2Fcaadbff8-7273-4c1d-b299-24b1f8a53655_sifive3.png)
![Keynote speech](https://prismic-io.s3.amazonaws.com/sifive%2Ff60fb2bf-0e67-46fa-bebc-0fa8e27a7eff_sifive4.png)

SiFive offers Core IP product Series (E, S, 2/3/5/7 Series, and U 5/7 Series). With 32 and 64 embedded Cores (some multicore capable) and 64-bit high-performance or multi-core application cores. The graph above summarizes the features by application, performance, cost targets of the core portfolio of offerings. Embedded RISC-V development can occur on platform boards such as HiFive 2 and the higher performance Linux capable HiFive Unleashed with expansion board. 

Taking a page from the Software industry built on software stacks, SiFive is enabling the creation of a hardware stack where the customization is the focus with the lower stack levels mostly automated reducing cost and improving schedules while maintaining consistency of the design flow process.

![Keynote speech](https://prismic-io.s3.amazonaws.com/sifive%2Fbed82c1e-ac98-471e-b433-34a4e7f8bdfe_sifive5.png)
![Keynote speech](https://prismic-io.s3.amazonaws.com/sifive%2F34f97c54-8ded-498c-b18d-f7a3e55dae9b_sifive6.png)

SiFive also is enabling a DesignShare ecosystem where third party IP providers allow early integration and verification of their content in a safe cloud-based environment and where SiFive manages the NDA/contract and collects NRE/royalties at the appropriate time simplifying the customer-vendor interface and process. 
The figure below shows a sample of the growing list of the participating IP providers. SiFive had the world’s first cloud Tape-out with Microsoft (Freedom U540) and the world’s first RISC-V SSD controller (FADU).
![Keynote speech](https://prismic-io.s3.amazonaws.com/sifive%2F7b2c0f23-42e9-405b-ab4c-8732114d169b_sifive7.png)
![Keynote speech](https://prismic-io.s3.amazonaws.com/sifive%2Fb6c213c1-26df-4d97-8def-2e4e637a3d26_sifive8.png)
Simon Davidmann, Imperas CEO then followed, addressing getting the best approach from RISC-V with Application-targeted custom instructions. RISC-V adopters can be developing internal cores, are IP providers, creating open-source IP, enabling open source ecosystem as a business, or taking advantage of open-source RTL by incorporating in their products. Two types of adopters can either be creating new architectures with a ‘freedom to innovate’ key requirement or adopters where ‘free’ is the key requirement in order to support research, education, FPGA platforms and open-source communities. 

The innovators want to add their own custom extensions and need quality simulation models to debug and analyze the custom instructions and to do RTL design verification. Imperas provides the high-performance CPU models, modeling technology with instruction-accurate verification simulators, tools, debuggers for embedded software development, debug and test purposes. Imperas Fixed Platform Kits (FPK) allow delivery models to customers and partners for pre-sales evaluation and development.
![Keynote speech](https://prismic-io.s3.amazonaws.com/sifive%2F3b97e568-e06c-4df4-9c94-73efc944862c_sifive9.png)
Megan Wachs, SiFive VP of Engineering discussed HiFive Freedom RISC-V Development Platforms. Two SiFive chip platforms include Freedom Everywhere (TSMC 180nm) and Freedom Unleashed (TSMC 28nm) allow customers to customize their SOC by combining pre-integrated configurable SoC architectures, processors, interconnect, off-chip interfaces, on-chip IP from a catalog of SiFIve and DesignShare partner IP providers along with the customer’s own IP. The HiFive1 Arduino-compatible RISC-V Development Board is sold out but a refresh is coming soon. The HiFive Unleashed, the first multi-core RISC-V Linux development board can be ordered on crowdsupply.com for $999.

The Freedom SDK along with SiFive’s Platforms allow configurability of the number and type of cores, includes peripherals and memory map with per-peripheral configurability. SiFive’s Open Source repository allows building one’s own Linux-capable FPGA image.

Ravi Thummarukudy, Mobiveil CEO highlighted RISC-V based platforms for SSD and IoT applications. Mobiveil provides IP and services for high speed interfaces, switches, bridges, memory controllers. To address data center energy and I/O bottlenecks, Mobiveil has a computational storage solution with filtering, scanning, data compression and many other features such as reducing I/O contention and improved power (up to 70% power savings) resulting in improved network performance, lower cost and latency. Mobiveil presented their configurable NVMe SSD Controller platform and reference design and the IoT SoC development platform.

Shafy Eltoukhy, SiFive SVP/GM Custom SoC BU outlined the SSD custom SoC solution with CPU features for the Storage applications using 64-bit real-time addressability for Big Data and real-time applications for Fast Data. AI uses cases for SSD helping in failure prediction, storage tuning, adaptive caching are some examples of what RISC-V can help address.

The Physical Design Platform features a robust silicon engineering methodology with comprehensive checklists throughout the analysis, exploration, implementation and tape-out phases. Custom SoC metrics include 140+ million units shipped with an average 25 DPPM, 300+ tape-outs spanning 100 different end applications for 150 unique customers from tier-1 system companies to startups.

Darrin Jones, Sr Director Technology Development for Azure Cloud Services Infrastructure put in perspective the semiconductor market exceeding 1 trillion devices in 2018 with about 6% CAGR since 2000. Azure boasts 2 million miles of intra data-center fiber, 55 Azure regions, 100+ data centers with millions of servers deployed. The Azure silicon development allows the design execution and verification, place and route and physical verification for advanced nodes such as 7nm with faster product iterations. SiFive, Cadence Design Portal and EDA tools and TSMC VDE are all deployed on top of the Microsoft Azure cloud infrastructure. Performance, price and agility are combining to offer compelling solutions that are seeing adoption.

End Part I

The Revolution Evolution Continues - SiFive RISC-V Technology Symposium - Part I

We welcomed over 600 attendees to the SiFive Tech Symposiums in Austin, Mountain View and Boston. The feedback we received is flattering. We heard comments like, “You guys are going bold, and we love it!” and “SiFive has built a solid team with good breadth of business and technology expertise,” and “Very different take – and someone is addressing the pain point for hardware folks, finally!” There was a great deal of energy in the crowd, and people were thoroughly engaged all day long. Here’s a look back at some of the highlights:

One of the things that stood out as truly unique about the symposiums is that they were very interactive events with a lot of audience participation. SiFive’s SoC IP partners, many of whom were in the audience, were recognized for their contributions to DesignShare, which is SiFive’s platform that makes world-class IP from leading vendors accessible to designers, thus streamlining procurement and removing barriers to entry for SoC design. As a result of these events, three new IP partners signed on to DesignShare, further expanding and building the strength of the IP ecosystem. Another opportunity for participant engagement came when SiFive was presenting on its Core Designer product, which allows designers to use a cloud-based platform to configure customized RISC-V core IP. Volunteers from the audience came onto the stage and used the platform to design their own RISC-V core IP unique to their application, which they successfully and easily accomplished quickly. The demos and showcases at each event garnered a lot of attention as well, with a steady stream of people asking questions and engaging in the displays. 

People were definitely impressed by the quality of the speakers and their presentations, and how they represented the magnitude of the RISC-V core IP and its ecosystem. The speakers ranged from leaders in the RISC-V Foundation, to CEOs and senior-level executives who shared their successes in enabling RISC-V based innovation through custom SoC solutions, cores and IP, development platforms, processors, tools and more. There were also presentations by those in the trenches of RISC-V academic research who talked about the latest RISC-V research projects taking place at some of the country’s most renowned university laboratories. 
These symposiums were made possible by our many co-hosts, partners and customers. Each and every one of them was instrumental in escalating the caliber of the symposiums into the realm of a world-class event. They fostered education, networking and idea sharing, all of which make up the cornerstone of the open-source community. We are grateful for their support.
The next destinations on our global tour are China, Europe and the Asia-Pacific region. To learn more, or to register for the event closest to you, please visit [sifivetechsymposium.com](https://sifivetechsymposium.com/).

![Keynote speech](https://prismic-io.s3.amazonaws.com/sifive%2F2721f88a-76a4-4a88-90fa-a61f01a2681a__dsc0055.jpg)
![Keynote speech](https://prismic-io.s3.amazonaws.com/sifive%2F04ea04fb-73bd-456d-ba0e-37c1283f6b4a_martin+fink_keynote.jfif)
![Keynote speech](https://prismic-io.s3.amazonaws.com/sifive%2Fdf3e7c74-e98b-4889-8fa9-75f977dd9ace_meghan.jfif)
![Keynote speech](https://prismic-io.s3.amazonaws.com/sifive%2F98e87109-59a8-4157-b759-5495469eb427_sp1_0573-339.jpg)
![Keynote speech](https://prismic-io.s3.amazonaws.com/sifive%2F6d7ac4ed-c51c-4459-85d9-fd27e6359c91_sifive_boston_2-19_062.jpg)
![Keynote speech](https://prismic-io.s3.amazonaws.com/sifive%2F3e0e5449-b89e-490d-a986-d65e9860631e_dsc00216.jpg)
![Keynote speech](https://prismic-io.s3.amazonaws.com/sifive%2F264c9ef7-cc7b-4108-8ebe-d64fea18d521_lrg_dsc00187.jpg)



The First Leg of our Global Symposiums is a Wrap, and it was an Enormous Success!

In 2018, we hosted several RISC-V technology symposia in India, China and Israel. These events were very successful in fueling the growing momentum surrounding the RISC-V ISA in these countries. It turns out that these events were just the tip of the iceberg. In 2019, SiFive is greatly expanding its reach by hosting over 50 SiFive Tech Symposia in cities throughout the world. The first leg of the global tour begins in the USA. In collaboration with our co-hosts and partner companies, we aim to foster deeper education, collaboration and engagement within the open-source community. 

**What’s Happening in Austin?**

With Microchip as our co-host, we have created an exciting lineup of speakers, tutorials and demonstrations for the event in Austin, TX on February 21. Ted Speers, a member of the board of directors for the RISC-V Foundation, will present on the history and current state of the union of RISC-V. Naveed Sherwani, CEO of SiFive, will deliver a keynote presentation about the semiconductor industry and how RISC-V is leading a design revolution. Another keynote presentation will be given by Tim Morin, director of product line marketing for Microchip, who will present on RISC-V based SoC FPGAs. Esha Choukse, a PhD candidate in computer architecture at UT Austin, will present on compression in deep learning for AI applications. We will also have presentations by several other leaders in the RISC-V ecosystem, including NXP and Hex Five Security. Attendees will also have an opportunity to see demonstrations and learn about the latest design platforms for RISC-V based SoCs, development boards, IP, software and more. For more information on the Austin event, please visit [https://sifivetechsymposium.com/agenda-austin/](https://sifivetechsymposium.com/agenda-austin/)

**What’s Happening in Mountain View?**
 
This event will take place on February 26 and will feature several presentations by key industry veterans and luminaries. Martin Fink, CEO of the RISC-V Foundation and CTO at Western Digital, will deliver a keynote presentation on his vision for the RISC-V Foundation and his plans for the next several years. Naveed Sherwani, CEO of SiFive, will present on the semiconductor industry and how RISC-V is leading a design revolution. Another highlight at this event will be a keynote presentation by Darrin Jones, the senior director of technology development for cloud hardware infrastructure at Microsoft, who will present on SoC design in the cloud. Krste Asanovic, chairman of the RISC-V Foundation and co-founder and chief architect at SiFive, will also deliver a keynote presentation on customizable RISC-V AI SoC platforms. Other highlights include a presentation by Megan Wachs, VP of engineering at SiFive, who will talk about RISC-V development platforms. There will also be presentations by the CEOs of  Imperas, Mobiveil and DinolusAI. Attendees will also have an opportunity to see demonstrations and learn about the latest design platforms for RISC-V based SoCs, development boards, IP, software and more. For more information, please visit [https://sifivetechsymposium.com/agenda-mountain-view/](https://sifivetechsymposium.com/agenda-mountain-view/)

**What’s Happening in Boston?**

With Bluespec as our co-host, this event on February 28 will include a powerful lineup of speakers. Rishiyur Nikhil, ISA Formal Spec Task Group Chair at the RISC-V Foundation, will present on the history and current state of the union of the RISC-V ISA, and will also deliver a keynote about RISC-V verification and design from his perspective as CTO at Bluespec. Krste Asanovic, chairman of the RISC-V Foundation and co-founder and chief architect at SiFive, will deliver a keynote presentation on RISC-V and its role in leading a design revolution. Adam Chlipala, associate professor of computer science at MIT, will present on the state of RISC-V academic research at MIT CSAIL. There will also be a presentation by Greg Sullivan, co-founder and chief scientist at Dover Microsystems. Attendees will also have an opportunity to see demonstrations and learn about the latest design platforms for RISC-V based SoCs, development boards, IP, software and more. For more information, please visit [https://sifivetechsymposium.com/agenda-boston/](https://sifivetechsymposium.com/agenda-boston/)

We look forward to seeing you in Austin, Mountain View and Boston!


The RISC-V Revolution is Going Global

This Month, you can join SiFive in Austin, Mountain View, or Boston

In 2018, we saw the rapid proliferation of the RISC-V architecture, with commercial deployments of SiFive Core IP in a broad range of applications ranging from wearables and edge devices to the enterprise core. Modern compute workloads are evolving rapidly and require the ability to scale performance on demand and very often have real-time, deterministic requirements. This diversity of workloads poses computational challenges that can be resolved only by domain-specific architectures. With the advent of 5G, core networks are transforming from hierarchical models in which intelligence was concentrated at the core to a decentralized structure where intelligence is getting distributed to the edge. 

![Recently announced products](https://prismic-io.s3.amazonaws.com/sifive%2F640aa239-ee11-427c-b000-c72b1787e1c3_slide1.png)

SiFive’s Core IP series brings unprecedented scalability to the CPU IP market. Until now, CPU IP has generally been fixed with some limited configurability. With intelligence moving to the edge, new combinations of compute, storage and acceleration are required. SiFive Core IP is architected to enable heterogeneous computing and efficiency requirements of these distributed intelligent applications by providing a scalable portfolio of CPU IP which can be customized according to the domain-specific requirements. 

![SiFive Core IP 7 Series](https://prismic-io.s3.amazonaws.com/sifive%2Fd0485f94-1488-47db-bb3d-8a00eba2e29a_slide2.png)

Last fall at the Linley conference, we unveiled **Core IP 7 Series** which sports our first superscalar CPU microarchitecture. The Core IP 7 series is the highest performance commercially available RISC-V CPU IP with performance and efficiency ratings higher than comparable Arm products across the board. We also introduced the **Core IP S Series** of cores, which are 64-bit real-time cores and have no competitive counterpart from any incumbent CPU IP provider. Compared to SiFive Core IP 5 Series, the Core IP 7 series is ~40-60 percent  higher in performance at the same clock frequencies and has an additional 10 percent improvement in maximum frequency which translates to a higher total performance.

While performance and efficiency on benchmarks are important, the innovations that we are most excited about are our ability to do true heterogeneous computing where you can combine real-time processors with application processors in the same coherent domain, along with our ability to enable deterministic response from an application processor. Embedded applications (edge, AR, VR, intelligent machines, ADAS, AI, storage) are progressively becoming more intelligent and require real-time deterministic response as well as the capability to run high-level operating systems to interface with the real world and third-party applications. 

![SiFive Core IP 7 Series embedded intelligence](https://prismic-io.s3.amazonaws.com/sifive%2F11ebb2bb-e478-40bd-82d8-fe78eb711902_slide3.png)

RISC-V is the only architecture that enables a common software stack across the entire application space. This enables lower TCO, common software stacks, and scalability from the edge to the cloud. We are translating the architectural advantages of RISC-V into SiFive’s CoreIP portfolio of CPU IP, which can be efficiently combined, customized, and extended to meet your specific application requirements. The details of our latest innovations have been documented in a recent article by Bob Wheeler from the Linley Group and is available [here](https://sifive.cdn.prismic.io/sifive%2F5ec09861-351b-420c-b6e3-e2b76843044f_linley+report+-+sifive+raises+risc-v+performance.pdf).

In 2018, we saw multiple partners launch commercial products based on SiFive Core IP, and there is so much more to come in 2019. We have a diversity of exciting products in our R&D pipeline and will continue to develop market-defining innovations that will enable a hyper-connected world of a trillion connected devices.

Happy New Year, see you at CES2019!

Published by [SemiWiki](https://www.semiwiki.com/forum/content/7919-you-will-not-get-fired-choosing-risc-v.html).

These were the closing words Yunsup Lee, CTO, SiFive used at one of the December RISC-V Summit Keynotes entitled ‘Opportunities and Challenges of Building Silicon in the Cloud’. Fired up was more the mood among the 1000+ attendees of the RISC-V Summit held at the Santa Clara Convention Center and SiFive was among the companies showcasing their latest offerings, providing an update among the increasingly active and productive ecosystem blending open-source initiatives with commercial products and services.<a name="footnote-1-source" href="#footnote-1">[1]</a>

Among the stats presented by Lee was the number of industry RISC-V cores released which will soon reach (in less than five years) more than 70 cores. 5,000+ registered to attend the SiFive Global City Tours and 500+ fabless semiconductor companies have contacted SiFive.

SiFive’s Core IP comprises the 2, 3, 5, and 7 Series. Each numbered series is a product family and comprises 32 and 64-bit offerings in E, S, and U variants. E cores are 32 bit embedded cores, S cores are 64-bit high performance embedded cores, and U cores are Linux-capable. Each Core IP Series comprises standard cores as well as cores that can be fully customized with the features of each available Core IP Series.

SiFive’s Core IP portfolio has rapidly expanded of late. In February 2018, the E2 cores of the 2 Series Core IP were launched. These are SiFive’s most efficient cores optimized for power and area. At the recent Linley conference, six cores were announced (E7, S7, U7, and their multicore versions) including the highest performance S76 and E76 cores with real-time determinism, the S76-MC, and E76-MC coherent multicores, the U74 real-time + Linux, and the U74-MC Heterogenous Multicore (used by Bouffalo Lab). The S7/U7 Core benchmarks clock at 4.9 Coremark/MHz and 2.5 DMIPS/MHz

Announced standard cores to date include the E20, E21, E24, E31, E34, S51, S54, U54, and U54-MC. Recent customizable Core IP design wins include eSilicon, Bouffalo Labs and Western Digital. The E31 has been implemented by Huami. SiFive also announced floating point features in numerous cores including the S54 and E34. The Linux-capable, coherent multicore U54-MC is used by Microsemi, a Microchip company while FADU has selected S51-MC and E31-MC coherent multicores with FPUs.

![SiFive Core IP Roadmap](https://prismic-io.s3.amazonaws.com/sifive%2F4a793508-abf7-4cf7-a048-75980520e8e1_sifive-core-ip-development.png)

The SiFive Embedded Software Ecosystem is growing, complementing SiFive Freedom Studio with offerings and compatible services from SEGGER, Lauterbach, IAR, Ashling, Imperas, UltraSOC with Embedded OSes like Express Logic-ThreadX, FreeRTOS, Zephyr, Micrium uCOS, RIOT, RTEMS, NuttX.

SiFive is building products to allow customization at scale with their online design platform with a web interface, allowing for the generation of customized RTL with their Core Designer. Eventually, Core Designer designs will be able to put into the Subsystem Designer to build RTL ready subsystems which can then be integrated with the Chip Designer (currently in development stage) to generate a chip for prototyping and silicon production readiness. Currently, only a web preview of the Chip Designer is available; an SoC template incorporates DesignShare IP from 3rd part vendors (currently numbering 20), SiFive IP, and custom IP. All this is done through a cloud infrastructure (Microsoft Azure), in conjunction with an EDA tools company (Cadence) with SiFive offering the front-end Design Layer platform and managing the back-end Fab and OSAT packaging and test relationships. The proof of concept SoC was taped out in September (see below).

![SiFive Design Platform](https://prismic-io.s3.amazonaws.com/sifive%2Ff4ebaf03-f126-4143-88e3-0ad7b5129de0_sifive-design-platform.png)

A variant of the FU540 was taped out in 28nm to prove the methodology. The variant was the first to utilize the combined cloud environment of TSMC’s VDE (Virtual Design Environment, announced at TSMC’s last OIP event), with Cadence tools, hosted on Microsoft Azure, with a SiFive’s web-based design integration and aggregation.

When asked what the biggest impediment to faster RISC-V adoption was, Yunsup Lee cited FUD (Fear, Uncertainty, Doubt) concerns and questions on whether the ecosystem is mature enough. He stressed that RISC-V is here and with everyone’s help working on RISC-V, it will be even stronger.

Yunsup Lee earlier had another presentation with Frans Sijstermans of NVIDIA where he described SiFive’s Freedom Unleashed Platform running NVIDIA’s open-source Deep Learning Accelerator (NVDLA) targeted toward edge devices and IoT. I had a chance to chat with him about this and he described a demo using a RISC-V Linux processor talking to NVDLA and running YOLO (You Only Look Once) v3 open source network. All components to test that out are open sourced and the code can be downloaded by anyone. 

Summit announcements included Microsemi’s [PolarFire SoC architecture](https://investor.microsemi.com/2018-12-04-Industrys-First-RISC-V-SoC-FPGA-Architecture-Brings-Real-Time-to-Linux-Giving-Developers-the-Freedom-to-Innovate-in-Low-Power-Secure-and-Reliable-Designs) which brings real-time deterministic asymmetric multiprocessing (AMP) capability to Linux platforms in a multi-core coherent central processing unit (CPU) cluster. This architecture, developed in collaboration with SiFive, features a flexible 2 MB L2 memory subsystem that can be configured as a cache, scratchpad or direct access memory. A PolarFire SoC development kit is also available, consisting of the PolarFire FPGA-enabled HiFive Unleashed Expansion Board and SiFive's HiFive Unleashed Development Board with its RISC-V microprocessor subsystem and NVIDIA’s NVDLA was onboarded among a flurry of announcements.

Lee mentioned that SiFive’s strategy to build the HiFive Unleashed development board and getting the software stack going is helping the security aspects and all the software being ported is great to see and is helping the ecosystem. The next steps for SiFive are to increase adoption with some people who are still on the sidelines by highlighting the successes. For example, FADU in Korea announced that they used the S5 series as a real product reporting 1/3 of the area and 1/3 of the power required had they used standard cores. In addition, standard cores had features that they did not need. SiFive gave them a tailored implementation.

Software and hardware are important, and people want the easiest way to solve their problems. People are seeing the benefits of this approach since they cannot build only one chip due to the requirements being diverse. According to Lee, SiFive is building what customers want who are now asking for high- performance templates with HBM, Interlaken, high-speed Ethernet, high-speed SerDes. SiFive is getting a lot of pull on AI/ML and automotive safety requirements, edge compute, industrial solutions whose needs are not currently being satisfied. More custom solutions will be needed, and customers will see that standard products do not meet their needs and a customizable and configurable Design Platform will be the way to go. In summary, Yunsup Lee came to the Summit to deliver one message: RISC-V is here. RISC-V is safe. RISC-V is better. You will not get fired for choosing RISC-V.

[Sign up for the SiFive Core Designer Beta](https://scs.sifive.com/core-designer/beta-signup) to build a custom RISC-V Core.

---
<a name="footnote-1" href="#footnote-1-source">[1]</a> The RISC-V Foundation Summit had about 1,200 registrations, with 32 countries and 23 states represented at the Summit, 29 exhibitors, 9 keynotes, 4 panels, 53 presentations, and 1 hackathon

You Will Not Get Fired for Choosing RISC-V

We are really excited to see Wave Computing announce the open MIPS ISA and R6 processor core. SiFive would like to congratulate and welcome MIPS to the open-source community with its MIPS Open Initiative. The addition of the MIPS 32 and 64-bit open ISA will provide more options freely available to SoC designers. The open-source processor community, based on the RISC-V ISA, is thriving, and the addition of MIPS underscores the fact that the world is indeed becoming more open. Open ISA enables chip designers, innovators and academics to explore and expand their designs. The ability to add extensions to the base ISA makes it an attractive option for applications requiring special configurations. Chip designers no longer have to settle for an off-the-shelf processor. SiFive RISC-V cores have enabled a high degree of customization, which our customers have loved and used to create designs at 1/3 the power and area versus other solutions.

Modern SoCs have multiple ISAs. The issue is that proprietary ISAs come and go. The benefit of RISC-V is that it fosters a stable, free and open ISA for chip designers to rely on. The addition of MIPS has strengthened that same open-source community with choice, as SoC designers can now choose from a variety of open ISAs for their SoC designs. The open-source community, based on the RISC-V ISA, has gained tremendous momentum this year. For example, the recent RISC-V summit in Santa Clara, California, was attended by more than 1,100 registrants from 20 countries around the globe. In addition, SiFive’s recent 2018 global tour in 16 cities across India, China, Korea, Japan, Brazil and Israel included more than 5,000 registrants, and resulted in 500+ fabless semiconductor companies contacting SiFive. Clearly, the momentum is here. Want more evidence? A recent video on RISC-V attracted more than 2.5M views worldwide, and a second video is about to surpass that! 

When the engineering community bands together, the possibilities are endless. We want to make the call to other hardware innovators out there, from GPUs to DSPs to AI accelerators of all shapes and sizes. We believe that open-standard specifications and hardware is the key to translating dreams and ideas of innovators, inventors and entrepreneurs into true working silicon. We welcome MIPS to the open-source community and welcome them into the semiconductor revolution!

Hi everyone! I'm Nathaniel Graff, a software engineer here at SiFive, and I'm
excited to tell you about the most recent release of [Zephyr RTOS](https://www.zephyrproject.org/),
[version 1.13.0](https://github.com/zephyrproject-rtos/zephyr/releases/tag/zephyr-v1.13.0)! 
Zephyr RTOS is a real-time operating system hosted by The Linux Foundation,
featuring support for a myriad of different platforms, architectures, and
targets including SiFive's E-series CoreIP, and the HiFive 1 development board.

I'm particularly excited about this release because it incorporates recent work
making the RISC-V port of Zephyr compatible with [DeviceTree](https://www.devicetree.org/)
descriptions of SiFive platforms. DeviceTree is the standard markup language
used by the Linux Kernel to describe the hardware configuration of a target
device. In Zephyr, we use it to automatically configure the Zephyr kernel
and device drivers to build and run on your microcontroller of choice. The end
result is that it's never been easier to get a full-featured RTOS up and running
on your own custom SiFive core and spend more of your own time building your
end-user application!

## Why Zephyr RTOS?

Zephyr RTOS has a number of great features that make it a good choice for
developing embedded applications on RISC-V. First and foremost, it has a
welcoming and active development community coordinated by the Linux
Foundation, and enjoys major corporate backing from Intel, NXP, Nordic, Linaro,
and more. The operating system itself also has a number of powerful features,
including a device model, symmetric multiprocess support, and rich networking
and bluetooth stacks. This is all in addition to the standard constructs you
expect to see from a Real-Time Operating System like deterministic
multithreading and inter-thread communication.

Zephyr supports RV32IMAC cores like the SiFive E31, as well as a number of
peripherals built in to the FE310-G000 processor on the SiFive HiFive 1,
including the UART, GPIO, and the Platform-Level Interrupt Controller.

## Getting Started with Zephyr

### Installing the Zephyr SDK

The best way to get started with Zephyr is to use the Zephyr SDK, which
packages the toolchains needed for all of the build targets Zephyr supports,
including RISC-V boards. For Zephyr v1.13.0, install SDK version 0.9.3, not a
newer release like 0.9.4 or 0.9.5, to make sure that the `qemu_riscv32` target
is compatible with the version of QEMU in the SDK.

To install the Zephyr SDK, follow the instructions in Zephyr's Documentation
for your platform of choice
([Linux](https://docs.zephyrproject.org/latest/getting_started/installation_linux.html),
 [macOS](https://docs.zephyrproject.org/latest/getting_started/installation_mac.html),
 [Windows](https://docs.zephyrproject.org/latest/getting_started/installation_win.html))

### Getting the Zephyr Sources

Zephyr RTOS is developed [on GitHub](https://github.com/zephyrproject-rtos/zephyr).
You can get the sources easily by cloning the official repo:

 1. `$ git clone https://github.com/zephyrproject-rtos/zephyr.git`
 2. `$ cd zephyr`
 3. `$ git checkout v1.13.0`

### Building the Hello World Application

Zephyr comes with a number of sample applications which demonstrate different
features of Zephyr. The Hello World application is a good place to start to
make sure you can build Zephyr applications and run them in your target
environment.

Start in the Zephyr Sources you checked out earlier in this tutorial.

 1. `$ source zephyr-env.sh`
 2. `$ cd samples/hello_world`
 3. `$ mkdir build && cd build`
 4. `$ cmake -DBOARD=qemu_riscv32 ..`
 5. `$ make -j$(nproc)`

If your build environment is configured properly, the resulting application
should be located in `zephyr/zephyr.elf`.

### Running Zephyr in QEMU

To run the application we just built in the QEMU emulator, all we have to do is
call `$ make run`. The Zephyr SDK comes with QEMU for all of its supported targets.

### Running Zephyr on the SiFive HiFive 1

To run the Hello World application on the SiFive HiFive 1, we'll need to rebuild
the application to target the HiFive 1 board.

#### Rebuilding an Application for a New Target

If you built `samples/hello_world` for qemu\_riscv32, we'll need to clean the
build directory to make sure that Zephyr is properly configured for a new target.
Run the following command to clean your build directory

 - `$ make pristine`

You can then retarget and build the application for HiFive1:

 1. `$ cmake -DBOARD=hifive1 ..`
 2. `$ make -j$(nproc)`

#### If you skipped building for QEMU

 If you didn't build your application for QEMU simulation, we'll still need to
create a build directory and source the proper environment variables. You can
build for HiFive1 by running these commands:

 1. `$ source zephyr-env.sh`
 2. `$ cd samples/hello_world`
 3. `$ mkdir build && cd build`
 4. `$ cmake -DBOARD=hifive1 ..`
 5. `$ make -j$(nproc)`

#### Programming the HiFive 1 Board

We'll need some more tools to connect to the HiFive 1 board and flash
the Hello World application, namely GDB and OpenOCD. You can download those
tools [from our website](https://www.sifive.com/boards) for your desired platform.

Once you've installed the GNU embedded toolchain and OpenOCD, grab [a copy of
the OpenOCD configuration file for the HiFive1](https://docs.zephyrproject.org/latest/index.html).

Plug in the HiFive 1. Then open a terminal and run the following command:
 - `$ openocd -f openocd.cfg`
 
In a second terminal, navigate to `samples/hello_world/build/zephyr/`
Then run this command to load the program onto the HiFive 1:

 - `$ riscv64-unknown-elf-gdb zephyr.elf --batch -ex 'set remotetimeout 240'
   -ex 'target extended-remote localhost:3333'
   -ex 'monitor reset halt' -ex 'monitor flash protect 0 64 last off'
   -ex 'load' -ex 'monitor resume' -ex 'monitor shutdown' -ex 'quit'`

Using your favorite serial terminal monitor (GNU Screen, PuTTY, etc.) connect to
the virtual serial port presented by the HiFive 1 at 115200 baud. You should see
a zephyr boot message and the phrase "Hello, world!"

### Debugging Zephyr on the HiFive 1 from Freedom Studio

Zephyr also supports debug flows within your favorite Eclipse-based Integrated
Development Environments, like SiFive Freedom Studio!

Detailed instructions for setting up your Eclipse environment for Zephyr
can be found [in Zephyr's Documentation](https://docs.zephyrproject.org/latest/application/application.html#eclipse-debugging).

![Screenshot](https://prismic-io.s3.amazonaws.com/sifive%2F7ecf4dc5-0ad9-48ff-af97-b71d0057d10e_20181030-zephyr_rtos_freedomstudio_debug.png)

## Building Your Own Zephyr Application

Now that we've built and run a Zephyr application, it's time to get started
building your own! Zephyr has [thorough documentation on the process to set up
and start developing your own application here](https://docs.zephyrproject.org/latest/application/application.html).

## Porting Zephyr to Your SiFive SoC

As I mentioned before, Zephyr v1.13.0 features DeviceTree support for SiFive's
products. For example, using our [Core Designer](https://www.sifive.com/core-designer),
you can configure your core to have your desired quantity of GPIO channels.
Zephyr's SiFive GPIO driver automatically scales to the number of GPIO channels
specified by the DeviceTree model of your chip. The result is that porting
Zephyr to a new SiFive SoC is as simple as dropping in the DeviceTree for your chip
and setting Zephyr's configuration options to your choosing.

To make the process of creating a port for a new SiFive chip even easier, I've
created a template project called [zephyr-sifive-freedom-template](https://github.com/sifive/zephyr-sifive-freedom-template/).
Using the template, all you have to do is provide your DeviceTree, run the customization script,
and answer a few questions.


Getting Started with Zephyr RTOS v1.13.0 On RISC-V 

It's been another week, which means it's time to find another host for
"Last Week in RISC-V".  This week we're going to attempt a blog at
[riscv.org](https://riscv.org), which will hopefully be a good long-term
home for this series of articles.

As usual, you can find this week's entry on [GitHub](https://github.com/sifive/last-week-in-risc-v/blob/master/lwirv-2018-10-19.md).

## glibc Floating-Point Test Suite

As part of the RV32I glibc submission process, Zong from Andes has
submitted a [glibc patch
set](https://sourceware.org/ml/libc-alpha/2018-10/msg00236.html) to fix
a generic floating-point bug that crosses the boundary between GCC and
glibc.  There's been a bit of feedback that, quite honestly, I don't
understand -- the combination of floating-point and glibc macros pretty
much guarantees that I won't be able to read the diff.

Luckily, it appears some smart glibc maintainers have figured out what's
going on and have helped Zong work through some issues.  I look forward
to the v2 patch set!

## binutils-2.31.1 Backports

Kito from Andes has [backported a handful of
fixes RISC-V specific
fixes](https://github.com/riscv/riscv-binutils-gdb/pull/162) to
`binutils-2.31.1`.  The most important fix here is to avoid generating
incorrect executables with PC-relative relocations that have addends, as
was discussed in a previous post.  Like usual, anyone distributing
RISC-V toolchains should update.

## Floating-Point Support in `ptrace()`

Jim has [submitted a patch to add floating-point support to our `ptrace()`
implementation](http://lists.infradead.org/pipermail/linux-riscv/2018-October/001828.html).
There are some interface issues in this version, but I'm sure they'll
get ironed out in time for the 4.20 merge window.

## MUSL Support in `riscv-gnu-toolchain`

Nick Kossifidis has [opened a PR to add support for MUSL to
`riscv-gnu-toolchain'](https://github.com/riscv/riscv-gnu-toolchain/pull/386),
which should be useful for anyone working on our MUSL port.  We're not
upstream there yet, but reading the patches that Michael Clark sent
upstream is still on my TODO list!

## HiFive Unleashed Linux Drivers

Paul has posted a [driver for the `sifive,uart0` serial
controller](http://lists.infradead.org/pipermail/linux-riscv/2018-October/001834.html)
as well as the [associated device tree
binding](http://lists.infradead.org/pipermail/linux-riscv/2018-October/001833.html)
to the Linux mailing lists.  There are some issues, but hopefully
they'll get resolved soon.

Additionally, Atish has a [patch set containing drivers for our GPIO and PWM
controller](http://lists.infradead.org/pipermail/linux-riscv/2018-October/001702.html)
that was posted to the list last week.

## Events

* October 14: [FOSSi Fiesta San
  Jose](https://fossi-foundation.org/fossi-fiesta-2018-10-14) hosted by
  Western Digital in Milpitas.
* October 18: [RISC-V Day
  Tokyo](https://tmt.knect365.com/risc-v-day-tokyo/) hosted by Keio
  University in Tokyo, Japan.
* October 22: [RISC-V BoF at Embedded Linux Conference + IoT Summit
  Europe](https://events.linuxfoundation.org/events/elc-openiot-europe-2018/)
  hosted by The Linux Foundation in Edinburgh, UK.
* November 1: [RISC-V Bay Area Meetup](https://www.meetup.com/Bay-Area-RISC-V-Meetup/events/255433135/) hosted by Antmicro in Milpitas.
* November 13: [RISC-V Microconference at Linux Plumbers
  Conference](https://blog.linuxplumbersconf.org/2018/) in Vancouver,
  Canada.
* December 3: [RISC-V Summit](https://tmt.knect365.com/risc-v-summit/)
  in Santa Clara, CA.

This week's entry is fairly short, but it does come with one major
improvement: we now have a mailing list!  I've decided to create a
[Google Group at
SiFive](https://groups.google.com/a/sifive.com/forum/#!forum/last-week-in-risc-v),
and while I understand that's not ideal it's the best I can figure out
for now.  The Google Groups interface is quick clunky, so if you're
looking for archives it's probably still best to use
[GitHub](https://github.com/sifive/last-week-in-risc-v).  Hopefully this
makes it easier for people to find the mailing list.

I've copied this message to various RISC-V mailing lists, but won't be
doing so in the future.

## HiFive Unleashed SD Card Bootrom Bug

Paul recently found a bug in the HiFive Unleashed's bootrom that
manifests when booting directly from the SD card.  The bug manifests
when the Unleashed is hot reset while the SD card is in the middle of a
block transaction.  We'll publish a concrete fix for the issue in our
open source bootloader repo, but since there's no way to fix the mask
ROM in the chip it isn't that useful in the short term.  The bug also
manifests in the FSBL (which is usually in SPI flash) during the
standard boot flow, and assuming the bug is what we think it is the FSBL
fix should be the same as the ZSBL fix.

To work around the bug you simply need to do a second hot reset -- just
try to time that one such that you're not in the middle of another block
transaction :)

## Signaling NaNs in the RISC-V glibc Port

The biggest outstanding issue in the RISC-V glibc port is our handling
of signaling NaNs.  Jim has been working through the [implementation of
`-fsignaling-nans` in our GCC
port](https://gcc.gnu.org/ml/gcc-patches/2018-10/msg00356.html) in order
to fix these test suite failures, which should aid the RV32I port
submission as well.

## GCC 8.2.0 Backports

Kito from Andes has [backported a handful of GCC commits to our release
branch](https://github.com/riscv/riscv-gcc/pull/139).  If you're
distribution RISC-V compilers then I recommend pulling these as well.

## QEMU 3.1 Soft Freeze

QEMU will have their soft freeze for the 3.1 release at the end of
October.  Thanks to Alistair from WD for [collecting a small patch
set](https://lists.gnu.org/archive/html/qemu-devel/2018-10/msg01429.html)
and pushing on it so we can get it upstream.  There are still a lot of
patches in the queue, but it's great to have someone helping out!

## Events

* October 14: [FOSSi Fiesta San
  Jose](https://fossi-foundation.org/fossi-fiesta-2018-10-14) hosted by
  Western Digital in Milpitas.
* October 18: [RISC-V Day
  Tokyo](https://tmt.knect365.com/risc-v-day-tokyo/) hosted by Keio
  University in Tokyo, Japan.
* October 22: [RISC-V BoF at Embedded Linux Conference + IoT Summit
  Europe](https://events.linuxfoundation.org/events/elc-openiot-europe-2018/)
  hosted by The Linux Foundation in Edinburgh, UK.
* November 13: [RISC-V Microconference at Linux Plumbers
  Conference](https://blog.linuxplumbersconf.org/2018/) in Vancouver,
  Canada.
* December 3: [RISC-V Summit](https://tmt.knect365.com/risc-v-summit/)
  in Santa Clara, CA.

## Contributing to "Last Week in RISC-V"

Like everything else in the RISC-V ecosystem, this won't be possible as
just a one-man effort.  I'm hosting the sources at
[github.com/sifive/last-week-in-risc-v](https://github.com/sifive/last-week-in-risc-v),
so if you're comfortable editing them feel free to open a pull request.
If you don't want to get involved in GitHub then you're also welcome to
just mail me patches or blurbs for inclusion and I can merge them
together.

I don't really have any specific criteria as to what will or won't be
included.  Part of the reason I'm doing this is that the RISC-V
ecosystem has started to get big enough that there are huge sections of
it that I know nothing about, so I think the starting criteria will be
"anything I'm interested enough in to want to read" and we'll just go
from there!

I spent too much time writing my single entry this week so it's all I
have. The issue itself is somewhat complex, so I thought it warranted a
deep dive.

### Relaxing `R_RISCV_PCREL_*` in the Presence of Addends

Jim recently found an issue with our ELF relocation scheme. While
technically it's a somewhat wide-ranging ABI bug, the actual set of
cases in which the issue will manifest is somewhat restricted -- in
other words: while I'm sure the proper long-term fix for this will be
quite involved, it probably isn't biting too many people in practice
right now. If you're unsure about how ELF relocations and linker
relaxation work on RISC-V systems, some of the [early entries in my "All
Aboard"
series](/blog/all-aboard-part-2-relocations)
go into greater detail. For this week's summary, I'll restrict myself
to the specific issues at hand.

The vast majority of RISC-V relocations follow the pattern of having one
relocation to fill out the high 20 bits of a 32-bit address (relocations
that follow the naming pattern `R_RISCV_*HI20`), and a second relocation
to fill out the low 12 bits of a 32-bit address (relocations that follow
the naming pattern `R_RISCV_*LO12*`). This
`R_RISCV*_HI20`/`R_RISCV*_LO12_*` pattern is baked into RISC-V's
instruction encodings, with the U format providing the high 20 bits and
the I or S formats proving the low 12 bits (hence the names `*_LO12_S`
and `*_LO12_I`). While the issue at hand applies to all relocations
that follow this pattern, the toolchain can handle this extra complexity
for the vast majority of these relocations -- that's why it took us so
long to notice! It turns out that there is one specific case where the
ABI we've chosen where this is difficult to do: the case where multiple
LO12 relocations share the same HI20 relocation but have different
addends.

Unfortunately this toolchain bug manifests as incorrect code generation
from the linker, which is pretty much the worst sort of bug -- nobody
understands the linker, so it's a long exercise for users to track down
the bug and then a lot of work to fix it. In practice this bug it is
somewhat unlikely to actually manifest in real code, but since it's a
linker bug it's probably best to understand what is going on with an
example before we dig into exactly why this bug is unlikely to manifest.

#### A Concrete Manifestation of this Bug

Like most of the examples I write it's somewhat contrived, I'll discuss
how this applies to more likely user code later. The following assembly
program is nonsensical but legal:

 .text
 .global _start
 _start:
 .balign 4096
 .fill 2048, 1, 0
 1: auipc t0, %pcrel_hi(global)
 addi t1, t0, %pcrel_lo(1b)+0
 addi t0, t0, %pcrel_lo(1b)+8
 
 .data
 .balign 4096
 global:
 .fill 2, 8, 0

it's a fairly simple program: it takes the address of a global symbol
and an offset into that global symbol. When assembled it generates a
single `R_RISCV_PCREL_HI20` relocation to fill out the top 20 bits of
the `auipc`, and then a pair of `R_RISCV_PCREL_LO12_I` relocations to
fill out each `addi`. This program assembles and links correctly,
resulting in the pre-linked object file you'd expect

 17fe:	00000297 	auipc	t0,0x0
 			17fe: R_RISCV_PCREL_HI20	global
 			17fe: R_RISCV_RELAX	*ABS*
 1802:	00028313 	mv	t1,t0
 			1802: R_RISCV_PCREL_LO12_I	.L11
 			1802: R_RISCV_RELAX	*ABS*
 1806:	00028293 	mv	t0,t0
 			1806: R_RISCV_PCREL_LO12_I	.L11+0x8
 			1806: R_RISCV_RELAX	*ABS*+0x8

and a sensible executable

 11800:	00003297 	auipc	t0,0x3
 11804:	80028313 	addi	t1,t0,-2048 # 14000 <global>
 11808:	80828293 	addi	t0,t0,-2040

Things start to get interesting when we slightly perturb this program.
In this case, let's look at what happens when we change the alignment of
the `auipc`. At the assembly source level this is a straight-forward
change (because I carefully constructed the example that way):

 .global _start
 _start:
 .balign 4096
 .fill 2050, 1, 0
 1: auipc t0, %pcrel_hi(global)
 addi t1, t0, %pcrel_lo(1b)+0
 addi t0, t0, %pcrel_lo(1b)+8
 
 .data
 .balign 4096
 global:
 .fill 2, 8, 0

In this case we generate a pre-linked object file that looks like you'd
expect, essentially the same as what's above but with different
alignment

 1800:	00000297 	auipc	t0,0x0
 			1800: R_RISCV_PCREL_HI20	global
 			1800: R_RISCV_RELAX	*ABS*
 1804:	00028313 	mv	t1,t0
 			1804: R_RISCV_PCREL_LO12_I	.L11
 			1804: R_RISCV_RELAX	*ABS*
 1808:	00028293 	mv	t0,t0
 			1808: R_RISCV_PCREL_LO12_I	.L11+0x8
 			1808: R_RISCV_RELAX	*ABS*+0x8

The interesting thing here is that this slight input perturbation results
in an incorrect binary after linking

 11802:	00002297 	auipc	t0,0x2
 11806:	7fe28313 	addi	t1,t0,2046 # 14000 <global>
 1180a:	80628293 	addi	t0,t0,-2042

Essentially what's going on here is that our relocations are capable of
providing 2^32 distinct bit patterns, but in the presence of pair
relocations with distinct addends we need to be capable of generating
2^32+1 bit patterns. Like many bugs of this sort, it's quite obvious
once it's been described but fairly difficult to find in practice.

#### Why this Probably isn't Manifesting in Your Program

If you've managed to make it this far you're probably getting pretty
worried: a linker bug that manifests as silent incorrect code generation
is a pretty hairy thing to deal with. While I agree, it turns out this
bug has lurked for so long because it's somewhat unlikely to manifest in
real application code under the set of compiler options that are
actually sensible to use. We are of course working on fixing the bug
(and there's already patches to at least cause it to manifest as an
explicit failure to link), but a fully performant fix is somewhat
tricky.

This bug can only manifest under a very specific set of conditions:

* There must be multiple `LO12` relocations that share a `HI20`
 relocation but have different addends.
* The result of the `HI20` relocation must be misaligned WRT to final
 target of the `LO12` relocations.

As long as you're writing C code and haven't written your own GCC
optimization passes, these conditions are mutually exclusive:

* GCC doesn't know how to share a single `auipc` between multiple
 accesses, so the only way to end up with a shared relocation for the
 top 20 bits of an address is via `lui`.
* GCC always aligns the intermediate results of the `lui`-based
 relocations. This alignment is implicit: GCC aligns the target
 symbol, which for `lui-`based addressing results in an intermediate
 result that is always aligned.

Importantly, the second case is not true for our `auipc`-based
relocations. Since `auipc` includes the current PC as part of the
intermediate result, aligning the target symbol is not sufficient to
align the intermediate result.

#### What's the Takeaway for a User of the Toolchain?

This article has been somewhat involved. I wrote it because I think
it's an interesting dive into a toolchain bug, but most people reading
this probably aren't interested in that level of detail and just want to
know what to do. My official recommendation is simple: don't use
`-mcmodel=medany` on an RV32I target. That's actually exactly the same
recommendation as I would have provided before we found this bug. The
key point here is that `-mcmodel=medany` doesn't actually provide any
benefit on RV32I targets: `-mcmodel=medlow` can already generate every
possible 32-bit address, so all `-mcmodel=medany` does is add a bit of
complexity to the address generation. I used to think that all that did
was generate slightly worse code, but now that we've found a correctness
bug my recommendation is simply a bit stronger.

The only users who are likely to need `-mcmodel=medany` are those on
64-bit systems. While you're unlikely to find a bug in `-mcmodel=medany
-mexplicit-relocs` because GCC can't perform constant subexpression
elimination on `auipc`, I'd still recommend avoiding `-mcmodel=medany
-mexplicit-relocs`. While `-mcmodel=medany -mexplicit-relocs` is
necessary to squeeze the last fer percent out of Dhrystone, we've found
it actually generates worse code for real programs which is why it's not
the toolchain default. If you're really that worried about a few
percent performance in Dhrystone then I'd recommend finding a better
benchmark.

I also explicitly recommend that users do not try to backport the
various patches to fix this bug themselves and instead wait for us to
completely verify these bug fixes and add them to our backport branches.
The workarounds above are really the right thing to do even without the
bug, and due to the subtlety of what's going on here, you're more likely to
end up introducing a bug than fixing one.

### Events

* October 18: [RISC-V Day
 Tokyo](https://tmt.knect365.com/risc-v-day-tokyo/) hosted by Keio
 University in Tokyo, Japan.
* October 22: [RISC-V BoF at Embedded Linux Conference + IoT Summit
 Europe](https://events.linuxfoundation.org/events/elc-openiot-europe-2018/)
 hosted by The Linux Foundation in Edinburgh, UK.
* November 13: [RISC-V Microconference at Linux Plumbers
 Conference](https://blog.linuxplumbersconf.org/2018/) in Vancouver,
 Canada.
* December 3: [RISC-V Summit](https://tmt.knect365.com/risc-v-summit/)
 in Santa Clara, CA.

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