If you missed the press release, SiFive is pleased to be working with Cycuity and BAE Systems.

The advent of generative AI has brought an increased focus on datacenter design and optimization. Datacenter chips need to be high performance with low latency to power the latest AI workloads. At the same time, sustainability is a growing concern for datacenters, so datacenter chips need to be extremely efficient. Additionally, chips need to be designed with flexibility in mind so companies can scale the number of clusters as needed.

As RISC-V technology broadens its reach from broad adoption in embedded use cases to growing deployments across a set of additional markets, one of the main questions I am asked relates to the readiness of software optimized for this processor architecture. Over the recent holiday period, I reflected on the significant progress on this front during 2024. The intent of this blog is to tie together a number of the important RISC-V software milestones and provide some hints as to the vector of travel for the year ahead.

This was my first time attending CES in (significantly) more than a decade. 141,000 attendees visited 4,500 exhibitors in the too-close-to-the-New-Year event in Las Vegas. As with most tradeshows, there were two levels to my conversations with customers and partners:

• Reviewing the products in the booths that showcased technology available now and available soon.
• The conversations behind the scenes focused on the challenges faced with those products and the desire to solve those issues in next-generation products.

With strong initial reviews, the HiFive Premier P550 Development Boards with pre-installed Ubuntu are in stock and available for purchase at Arrow.com. First launched in October, the Yocto-based Early Access edition of the HiFive Premier P550 sold out rapidly as developers eagerly embraced it to test their RISC-V designs on real silicon. Today, we’re excited to announce the general availability of the Premier P550 in both 16GB and 32GB configurations. This release offers even more flexibility and power, featuring pre-installed Ubuntu 24.04 to help developers make the most of their RISC-V projects.

In this blog, we’ll begin by introducing XNNPACK and exploring its current status on RISC-V platforms. Next, to bridge the technical gap for contributors, we will provide a step-by-step guide on integrating RVV-optimized microkernels into XNNPACK, using F32-GEMM (single-precision floating-point general matrix multiplication) as a practical example. Finally, we will highlight the performance improvements achieved through these optimizations.

In June 2024, SiFive announced the 4th generation of its Essential Product line. Products from the Essential family are already deployed in billions of consumer and IoT products including smartphones, sensors, SSDs, FPGA platforms, surveillance cameras, smartwatches and more. This new release contains a wide range of iterations on the previous generations and numerous new features. The inspiration for the majority of these enhancements came from customer feedback. One specific example is the support for AMBA ACE, a protocol for bidirectional data coherency that enables customers to create systems with multiple clusters of Essential processors.

At the RISC-V Summit in North America this week, RISC-V International announced that the RVA23 Profile has been ratified. The fundamental objective behind RVA Profiles is to ensure software portability across hardware implementations.. This announcement reminded me of an important question that Krste Asanović, Co-founder and Chief Architect at SiFive and Chief Architect of RISC-V International, brought up during his 2024 presentations at the RISC-V Summit Europe in Munich and (more recently) at the RISC-V Summit China in Hangzhou. During these sessions, Krste tackled the (much asked) question: is RISC-V flexible or rigid? The answer is “Yes!”

Reflecting on how far we’ve come since SiFive launched the world’s first RISC-V development boards back in 2016, it’s clear we’ve been on an incredible journey together with the RISC-V software community. Those early boards, like the HiFive1, were game-changers—true ignitors for the entire RISC-V revolution. Since then, SiFive has continued to innovate, releasing new boards every 2 years, adding more performance and features, pushing the ecosystem forward.

SiFive’s mission is to create the best computing solutions in the world so our customers can deliver differentiated, best-in-class products. We do this not only by building great intellectual property (IP), but also by driving the RISC-V ecosystem forward. The open standard RISC-V architecture is the last instruction set architecture (ISA) that will ever matter. It’s not often that you can be part of a computing revolution; especially one that is revolutionizing systems as we know them. SiFive helps spur innovation across a broad community while ensuring our customers benefit from the evolution of our high-performance IP, ecosystem, extensions, and tools.

Large language models (LLMs) have become essential to numerous applications, thanks to their powerful capabilities in natural language understanding and text generation. However, their large model sizes and high computational demands present significant challenges for efficient deployment and real-time performance.

In case you missed it at the 2024 Samsung Developer Conference today, our partners at Samsung Visual Display discussed the work they have been doing to port the Tizen operating system to RISC-V. Tizen is an open-source operating system (OS) that is used in many Samsung smart T.V.s and it makes sense that they would look to the fast growing, global open-standard RISC-V to develop future systems. The presentation showed the results of efforts at both companies to expand the capabilities of the already robust Tizen approach. At the event they also demonstrated a T.V. running on RISC-V and using a SiFive Performance P470 based core.

At our recent SiFive Day event, SiFive’s CEO Patrick Little explained that “AI and RISC-V were made for each other.” The open RISC-V standard frees developers from the restrictions of proprietary compute, giving them more flexibility to innovate. RISC-V efficiently supports specialized computing engines including mixed-precision operations, and developers can further customize solutions with vector instructions and specialized AI extensions. Additionally, RISC-V has a widely supported software ecosystem.

I was fortunate enough to attend the RISC-V China Summit in Hangzhou in August. As a premium sponsor, SiFive had a large presence at the show with a booth in the exhibition hall and several executive presentations. The inspiration for writing this blog was when a great friend of mine asked me to compare and contrast this event with other recent RISC-V events held in North America and Europe. My high-level response was;

One of the primary motivations behind my decision to join SiFive was the opportunity to define, articulate and execute our go-to-market initiatives for a range of high value market segments. Several analysts have created their estimates of market share growth into these segments including Omdia (see chart below). SiFive has strong momentum, but, to me, the infrastructure/datacenter segments are particularly exciting.

SiFive has a global footprint, working with the world's largest semiconductor manufacturers, automakers, global hyperscale data centers, and consumer device companies. It’s no surprise then that we’re frequently at industry shows and events around the globe. We recently participated in shows across Asia, Europe, and the U.S., and we’re off to RISC-V Summit China next. Read on to learn more about our latest activities and what’s ahead.

The automotive market requires high levels of quality and safety. With the rapid increase in the number of chips and electronic systems in vehicles—there are as many as 3000 or more chips in some cars—the need for safety and the ability to test and certify these systems has become more challenging and more critical. Recognizing the importance of quality and safety early on, SiFive formed a team of world leading experts in automotive functional safety (FuSa) to empower our customers to swiftly deliver safe, secure and certified products for connected vehicles. These functional safety products are also beneficial for many other markets, including aerospace and defense. In this blog we’ll share more information about functional safety and will talk about how SiFive is integrating it into our broad portfolio.

In the era of software-defined vehicles (SDVs), cybersecurity isn't just a buzzword; it's a critical necessity. SDVs are increasingly vulnerable to cyberattacks thanks to their interconnected systems, huge size of software and vast amounts of data being generated and processed. These attacks could compromise safety, privacy, and even a vehicle's functionality and have huge implications to brand reputation. To help mitigate these risks, SiFive is laser focused on cybersecurity and recently achieved ISO/SAE 21434:2021 product certification.

We are proud to celebrate SiFive’s Priyanka Viswanathan, director of functional safety and cybersecurity, and Monia Chiavacci, senior principal architect of functional safety, for their recognition in Electronics Weekly’s 2024 Women Leaders in Electronics Awards. The program honors women who have made significant technical achievements and have had a positive impact on the electronics industry. Priyanka brought home an award in the Safety and Compliance category, and was recognized as a finalist in the Unsung Hero in Leadership Role category. Monia was a finalist in the Innovator of the Year category.

SiFive was busy in Washington, D.C. this week, participating in a number of exciting meetings surrounding the historic visit of Japanese Prime Minister Kishida to the United States. The visit highlights the strength of cooperation between the two countries and the importance that the semiconductor industry holds in this alliance. SiFive was honored to occupy a seat at the table alongside industry powerhouses and key government officials from both nations.

Jonathan Gentin of SiFive joined a U.S.-Japan Semiconductor Suppliers roundtable and explained to participants how RISC-V and SiFive’s collaborative ecosystem is well poised to enhance innovation and cooperation between the U.S. and Japan. RISC-V, of course, is an open standard that allows for collaboration in all emerging areas of compute ranging from AI to automotive to datacenter and to consumer devices. As the leader in RISC-V, SiFive is working with lead partners to continue to grow RISC-V in Japan.

In the first of what we expect will be a number of webinars this year, Krste Asanovic, SiFive co-Founder, Chief Architect and RISC-V innovator, sat down to talk about how SiFive is solving real-world AI challenges and some of the applications where RISC-V is gaining rapid momentum. He also discussed how our latest innovations in high performance RISC-V computing are bringing exciting open standard solutions to AI and ML workloads.

You can watch the webinar here:

Securing your vehicle used to mean remembering to lock your doors at night and hiding your belongings under the seat when parked in public lots. Now that today’s smart cars are running hundreds of millions of lines of code, vehicle security has become much more complicated. To protect private data and sensitive information in vehicles, it’s critical that automotive processors support the latest functional safety and cybersecurity standards.

SiFive has always been at the cutting-edge of vehicle safety, and we recently hit a new milestone by achieving ISO/SAE 21434 compliance. ISO/SAE 21434 is the first automotive-focused standard specifying a cybersecurity framework for next-generation software defined vehicles (SDVs). Our RISC-V automotive products already offer unparalleled design freedom and flexibility for the automotive market, and now our customers can design vehicle components with the confidence that our solutions meet the most demanding security requirements.

Let’s dive in further to explain why ISO/SAE 21434 is so important. The standard provides specific requirements for cybersecurity processes and establishes a common language for communicating and managing cybersecurity risk across the supply chain—protecting original equipment manufacturers (OEMs) and end users from cybersecurity threats. ISO/SAE 21434 certification is seen as a prerequisite for OEMs in selecting their suppliers, as this certification allows OEMs to meet the requirements for UN R155, a regulatory framework designed to ensure that vehicles are secure.

Many of the processes required by the ISO/SAE 21434 are not new for SiFive. SiFive expanded on its existing processes to meet additional requirements specified by ISO/SAE 21434, including providing its customers with a security package that includes a security manual, and a cybersecurity capability and interface report. Now all of SiFive’s automotive products include this package to streamline the standardization process at every level of the supply chain.

With SiFive’s deep commitment to quality, security, and safety, our efforts don’t stop here. SiFive will be implementing the security practices and guidelines outlined by ISO/SAE 21434 as appropriate across the other products in our portfolio. This will make it easier for our customers across different verticals to take advantage of the latest security capabilities, even if certain segments do not have as strict security requirements as the automotive market.

To learn more about SiFive Automotive™ solutions, please visit.

In stock today!

We’d like to thank our moms, the Academy and …well ok, maybe it’s not the Oscars but the 2023 RISC-V Summit was filled with innovation, collaboration, and a SiFive award for one of our most popular products! The SiFive Performance P470 RISC-V processor was awarded Embedded Computing Design’s Best in Show Award at this year’s event. Winning in the microelectronics, microprocessors and IP category, the SiFive Performance P470 brings unparalleled compute performance and efficiency to small size, high volume applications such as wearables, smart home devices, and consumer devices. At the Summit Samsung representatives spoke about their experience working with the P470 in silicon and also provided some great overall advice to the RISC-V ecosystem.

The SiFive Performance P470 is the company’s first efficiency-focused, Out-of-Order, area-optimized vector processor. It is significantly smaller than competing solutions and is optimized to have best-in-class performance efficiency and area density. The P470 delivers significant upgrade opportunities over legacy processors, offering impressive compute density, power efficiency, and robust feature sets to handle the most demanding workloads and bring significant cost savings to customers. Plus, the processor offers greater design flexibility to meet specific application needs, power budgets, and cost envelopes.

The progress RISC-V has made in the past few years is amazing. The leap from being an ISA deployed for basic embedded cores to powering high performance applications in consumer products, datacenters, autonomous vehicles, and next generation wearables, has come faster and stronger than anyone anticipated. The RISC-V community has grown from a few dozen contributors to more than 3,900 members – spanning markets, applications, and geographies. The ISA has become foundational technology for the entire semiconductor industry, and we are now witnessing the beginning of a profound shift toward RISC-V. Some of the world’s largest and most influential technology companies have joined our ranks and further strengthened our ecosystem, a community which, over time, will rival all others. Qualcomm and Google’s recent announcement of their collaboration on a RISC-V based wearables platform that will power next generation Wear OS solutions is a groundbreaking milestone that will pave the way for more RISC-V products within the ecosystem. This further highlights the relevance and momentum of RISC-V’s unstoppable march.

SiFive congratulates Arm on its IPO, which represents a momentous step forward for the entire semiconductor ecosystem. This IPO has brought more awareness to the public about the critical role of computing architectures, specifically the instruction set architecture (ISA), and the need for high-quality, high-performance processor IP to drive our industry forward. Competition is essential for a healthy semiconductor industry, and we continue to hear from companies about the importance of having choice in the processor market, especially after the chip supply challenges of the last few years. Arm has helped focus a spotlight on the ISA and CPU IP, and is highlighting its criticality to the fastest growing areas of semiconductors, areas like datacenter and AI, automotive, consumer, and mobile.

Part of the excitement has been a new recognition of how big the market opportunities are, and there is room for all of us. These markets need rapid innovation and customization, which are consistent themes in our conversations with customers. It’s no secret that SiFive’s founders developed RISC-V as a response to the limited customization options of closed, proprietary architectures. We work with global technology leaders and SiFive’s high-performance IP is being designed into everything from aerospace applications to automotive, the datacenter, wearables, and beyond. While the semiconductor landscape has evolved considerably since then, what hasn’t changed is that companies want design flexibility and freedom: SiFive and RISC-V make that possible. After all, there are no limits with RISC-V.

SiFive recently received its official ASIL-B Ready Functional Safety Certificate from the SGS-TUV organization, and to understand the implications, I discussed this achievement with SiFive’s industry recognized Automotive Functional Safety experts, Priyanka Thachakuzhiyil Viswanathan, Director Functional Safety and Cybersecurity, and Monia Chiavacci, Sr. Principal Architect, Functional Safety. This is a great step forward for our customers. Here’s what I learned.

I recently had a great conversation with Bill Lamie, President/CEO of PX5, and Rafael Taubinger, Sr. Product Marketing Manager at IAR, regarding the recent port of the industrial-grade PX5 RTOS to the SiFive HiFive Rev B RISC-V development board (powered by a 32-bit SiFive RISC-V embedded microcontroller), using the IAR Embedded Workbench tools suite. I wanted to understand why Bill, who has been a serial innovator in embedded for decades, chose SiFive and IAR as the platform and development solutions, respectively, for his most recent venture. And, since I wasn’t yet familiar with the PX5 RTOS, I wanted to gain some insights into this latest technology. As a veteran of the RTOS market myself, I was super impressed that PX5 can be configured for minimal size, requiring less than 1KB of Flash and 1KB of RAM on 32-bit microcontrollers. The kernel features native POSIX threads API, making it portable and familiar to developers across the spectrum. The PX5 team has a particular focus on extensive validation and verification to enable use in safety-critical applications that require documented safety practices.

You are invited to attend an upcoming webinar where Ansys will talking with SiFive's Phil Dworsky to discuss the pursuit of maximum compute density in our RISC-V processor cores.

In March, SiFive announced the opening of its new office in the greater Boston area. 2022 was a monumental year for SiFive and 2023 is shaping up to be another strong year. Marlborough was an ideal location for the new office as the company continues to expand its footprint and serve our growing customer base located in Massachusetts and the surrounding Northeast region.

The office will be led by Shubu Mukherjee, vice president of architecture at SiFive, with plans to grow its headcount in the next 12-to-24 months. The greater Boston area is rich in talent in all areas of semiconductor development, including architecture, RTL, digital verification, and physical design, as well as sales, marketing, and business development. Having a physical presence in the area will help reach both experienced professionals as well as tap into the strong University programs in the region.

SiFive is always seeking talented designers and engineers ready to make an impact on the world and help accelerate the adoption of RISC-V. You can always check our website for open roles. Careers

As the inventors of RISC-V and performance density leaders, SiFive is committed to spreading the word about how this groundbreaking open architecture is reshaping the computing industry and ushering in new possibilities. Last week, we hosted the SiFive Tech Forum in Hsinchu, the technology heart of Taiwan, to bring together hardware engineers, developers, and other technology leaders to talk about the incredible momentum of RISC-V to-date and how SiFive is leading the RISC-V revolution. The event was well over subscribed, which highlighted the eagerness with which the attendees were keen to learn about the latest SiFive solutions. Read on to find out more about what we covered during the SiFive Tech Forum. And you can view the presentations here

SiFive is in attending 2023’s embedded world from March 14-16, and we’d love to see you there! Meet us in Nürnberg to learn about some of our recent announcements, including our new processors for wearables. These new processors, the P670 and P470, offer unrivaled choice and flexibility with the perfect balance of performance and efficiency. The P670 is ideal for applications like premium wearables, networking, robotics, and mobile. Meanwhile, the P470 – SiFive’s first efficiency-focused Out-of-Order, area optimized, vector processor – is designed for applications like wearables, consumer, and smart home devices.

In case you missed it, we also recently introduced new automotive processors. SiFive’s Automotive X280-A, E6-A, and S7-A solutions address critical needs for current and future automotive applications like infotainment, cockpit, connectivity, ADAS, and electrification. The X280-A (the automotive version of SiFive’s X280 vector processor) has industry-leading performance to meet the complex computing requirements of sensor fusion and ML intensive workloads. The E6-A series is designed for real-time, 32-bit applications including system control, hardware security modules (HSMs), and safety islands, and also serves as a standalone solution for microcontrollers. Additionally, the S7-A is a 64-bit, high-performance real-time core optimized for the needs of modern SoCs with performant safety islands.

Let us know if you’d like to set up a meeting to learn more about these new products and how the open era of computing is transforming the semiconductor industry. SiFive saw record growth in 2022 driven by global demand for RISC-V and a growing awareness of it's compute density and power efficiency advantages. We work closely with more than 100 leading customers in applications including automotive, AR/VR, client computing, datacenter, and the intelligent edge. To set up a meeting, please contact sifive@racepointglobal.com.

At the 2022 RISC-V Summit, SiFive highlighted collaborations with some of the world’s biggest companies in our 10+ talks on stage and with our demos. SiFive also gave an exclusive first look at an upcoming product, and three of our employees won awards.

One highlight was the keynote from SiFive’s CEO, Patrick Little: “RISC-V Spotlight: RISC-V Everyone Wins”. Patrick highlighted how the momentum and excitement for RISC-V is growing and how today it is in billions of cores on the market and is being designed into a huge range of applications. Patrick covered the early vision for RISC-V and emphasized the importance of collaborating to build a strong community and ecosystem for RISC-V.

As part of our efforts to build out the RISC-V ecosystem, SiFive has partnered with Intel to develop the HiFive Pro P550 Development System (previously code-named Horse Creek). During his keynote, Patrick was joined on stage by Intel Foundry Services’ Bob Brennan to share a first look at this high performance platform that features a quad-core SiFive Performance™ P550 processor and is implemented in the Intel 4 technology platform. The board will enable a new generation of RISC-V software, continuing the tradition of SiFive HiFive boards that have helped drive the growth of the RISC-V ecosystem. The board will be commercially available in the summer of 2023.

SiFive ecosystem partners and customers, including Ashling, AWS, Canonical Ubuntu, Codeplay, Google, Imperas, Intel, Lauterbach, Microchip, Qualcomm, Rice University, Solid Sands, Synopsys, and Tenstorrent, were featured throughout the event and in a panel session entitled “It takes a village… to build an ecosystem,” which reviewed the strong state of the RISC-V ecosystem as well as the next steps that key contributors are leading.

SiFive’s additional presentations throughout the event focused on our collaborations and partnerships to bring our high-performance RISC-V portfolio to automotive, aerospace, and beyond. For example, through our partnership with Microchip, SiFive is a part of NASA’s next generation High-Performance Spaceflight Computing (HPSC) processor, which delivers a 100x increase in computational capability to help propel next-generation planetary and surface missions. Jack Kang, SVP, Biz Dev, CX, Corp Marketing at SiFive, summed up why so many companies are choosing RISC-V and SiFive: “RISC-V products are just better. Better power, better performance, and more.”

Jack also took some time to chat with RISC-V International’s CEO Calista Redmond about our momentum to-date and what’s ahead.

SiFive continues to invest strongly in the RISC-V community, with many of our employees actively participating in RISC-V International’s technical committees. In recognition of these efforts, three of SiFive’s employees won awards from RISC-V International. Yunsup Lee, SiFive’s Co-Founder & Chief Technology Officer, received a Technical Contributor Award for his work as Chair of the Technical Steering Committee (TSC). Craig Topper, Principal Compiler Engineer, and Kito Cheng, Compiler Engineer, received Software Contributor Awards for their hard work on RISC-V technical committees. Check out the full list of winners here.

You can read more about SiFive’s latest activities and momentum in 2022 here. To watch SiFive’s presentations at the RISC-V Summit, visit here.

SiFive has seen tremendous growth over the past few years with strong year-over-year revenue growth and is in the top 10% of the Inc. 5000 list of private companies. With more than 550 employees around the world, we’re continuing to grow our team and expand our footprint across different regions to meet the strong customer demand for SiFive’s innovative RISC-V IP.

India is one region in particular where we’re focused on building out our team. This month SiFive opened a new design center in Bangalore, India. We have around 90 employees working there currently, and the space has room for around 150 employees as we continue to grow. The Bangalore team is focused on leading edge CPU and platform design, verification, physical implementation and software.

In the fast moving Semiconductor Industry, predictions and papers become obsolete fast and so it’s worth recognizing when a paper has a significant impact on our industry that also has a bit of a timeless nature. The paper, A systematic methodology to compute the architectural vulnerability factors for a high-performance microprocessor (you can read it here was recognized during the award ceremony at MICRO 22 in Chicago October 4th, and we’re proud to share that our very own VP of Architecture, Shubu Mukherjee, (who was at Intel at the time it was written) was there to accept the award on behalf of his fellow authors, Christopher Weaver, Joel Emer, Steve Reinhardt and Todd Austin.

At the AI Hardware Summit in Santa Clara, September 14th, Krste Asanovic, SiFive Co-Founder and Chief Architect, took to the stage with Cliff Young, Google TPU Architect and MLPerf Co-Founder, to reveal how the latest SiFive Intelligence™ X280 processor with the new SiFive Vector Coprocessor Interface Extension (VCIX) is being used as the AI Compute Host to provide flexible programming combined with the Google MXU (systolic matrix multiplier) accelerator in the datacenter. They also talked about why this type of architecture is becoming popular for AI/ML workloads, and how, with this configuration, SiFive provides essential compute capabilities so Google can focus on deep learning SOC development. A video of the talk is expected to be available in early October.

The Next SiFive Revolution

As SiFive announces its long-term plans to meet the rapidly changing needs of the automotive markets, this blog explores the many advantages the SiFive Automotive™ portfolio brings across a wide range of current and future applications, including; electrification, cockpit, ADAS, safety, and others. Our power efficient, flexible and high-performance cores are ideally suited for the most critical applications, and are of course, supported by the global RISC-V ecosystem.

In June 2022, SiFive released an enhanced version of the market-leading SiFive® Intelligence™ X280 processor to take a further leap in performance for AI inference, image processing, and datacenter applications.

With the 2021 launch of the SiFive® Intelligence™ X280, SiFive was the first company to release a RISC-V Vector 1.0 product, and it took the market by storm. The X280 has quickly achieved market-leading success, with design wins across a number of high performance applications including AI inference, Image Processing, and Datacenter applications. Customers include a U.S. government agency working on next generation aerospace/defense standards, a tier #1 global mobile image processor supplier, and a tier #1 global hyperscaler for AI, and the list grows daily..

If you haven’t seen it, SiFive is ranked in the top 10 percent of Inc.’s annual list Here of the fast-growing private companies in America which includes a wide range of industries. This ranking is a direct reflection of our impressive revenue growth the past three years and our momentum, forward trajectory, and leadership in the processor IP market. By the numbers, SiFive is ranked No. 413 overall, and we are excited to rank an impressive second (No. 2) in computer hardware.

Cambridge, with a long history of innovation and invention and a thriving tech ecosystem, is an obvious choice as a location for SiFive to continue its global expansion. We’re all about attracting the best talent, anywhere, and part of our mission and values is to also give back to, and be an active participant in the communities where we do business. As we expand in Cambridge we found a great partner with Cambridge United Football Club and this week announced our sponsorship as part of a week-long celebration. See the promotional video Here

SiFive is the market leader in RISC-V Vector processors with the flagship SiFive vector processor, the SiFive Intelligence X280, leading the charge as a clear favorite with customers, with solutions being designed into a broad range of applications ranging from computer vision, mobile ISP, Edge AI, to datacenter AI.

After describing the current 2022 broad SiFive Performance, Intelligence, and Essential Processor Product portfolio, this webinar introduction to the SiFive vector processors begins by identifying some of the challenges that exist for system designers and subsequent evolving application trends.

A great way to get to know more about popular SiFive vector processors, which are compatible with the RISC-V Vector (RVV) version 1.0 specification

SiFive is the market leader in RISC-V Vector processors and has gained significant market traction, with solutions being designed into a broad range of applications ranging from computer vision, mobile ISP, Edge AI, to datacenter AI.

The RISC-V revolution continues to advance as the technology industry embraces open computing to address semiconductor design and business challenges

SiFive joins the Intel Foundry Services IP Alliance program to broadly enable innovative new computing platforms

SiFive is aiming high with bold new technology for performance-driven applications

The RISC-V Summit 2021 highlighted to the world that the future of RISC-V has no limits!

The freedom of RISC-V enables a bright future for SiFive

In just a few short years, RISC-V has become a category of utmost importance in tech; but, things are just getting started.

Scalable High-Performance Computing SoC Design with RISC-V

Leading the RISC-V uprising drives SiFive, home of the inventors of RISC-V, to continue to push forward with developing our product families and technologies.

Introducing the new era of SiFive Performance for RISC-V

This week has been an exciting one for our team at SiFive, with a number of key announcements that are beginning to allow us to publicly share our strategy for the exponentially growing AI/ML market. While we are only scratching the surface of the impact AI/ML will have on our industry and our lives, it’s clear that the workloads, algorithms, and requirements are going to be constantly evolving and improving for the foreseeable future.

These changing requirements make it exceedingly difficult to align workloads with purpose-built silicon. Hardwired accelerators may work well for matrix multiplication and convolution layers today but simply aren’t efficient or adaptable enough for more modern models, such as transformer-based models like BERT or recommendation models. What’s needed are adaptable AI and ML solutions with a flexible, future-proof approach enabled by efficient, programmable building blocks of hardware IP designed with a software-first ideology.

This leads us to our biggest announcement this week, SiFive Intelligence. Today at the Linley Spring Processor Conference, Dr. Chris Lattner, President of Engineering and Product at SiFive, introduced the SiFive Intelligence X280. The SiFive Intelligence X280 extends RISC-V with SiFive Intelligence Extensions, integrating dedicated AI acceleration technology and extended data type support. SiFive Intelligence includes turnkey software solutions that utilize the X280's features to provide great AI inference performance and support for the full capability of TensorFlow Lite. The result is a programmable, scalable, and configurable platform to meet modern AI/ML processing requirements from the edge to the cloud, providing out-of-the-box compatibility with a wide range of popular machine learning models.

We’re pleased to debut SiFive Intelligence and to be able to tell you that one of the first customers of the SiFive Intelligence X280 is AI developer Tenstorrent, an innovator in AI training and inference processors led by industry leaders Ljubisa Bajic and Jim Keller. The heterogeneous combination of Tenstorrent’s Tensix processing cores alongside the SiFive Intelligence X280 will bring efficiency and programmability to stay ahead of the requirements of next-generation AI workloads. Read more about SiFive's collaboration with Tenstorrent.

This week also saw the announcement of a new partnership for SiFive, with Renesas licensing the SiFive RISC-V Core IP portfolio and collaborating with us on next-generation RISC-V solutions for the automotive markets. Our product portfolio includes 32 and 64-bit embedded real-time cores; advanced, high-performance RISC-V processor cores; and SiFive Intelligence. We’re excited to see what the future will bring as we collaborate to meet the automotive application requirements and the new AI workloads that will come from it. Read more details on the Renesas blog post, Renesas and SiFive Partner to Jointly-Develop Next-Generation High-End RISC-V Solutions for Automotive Applications.

The future of AI processing requires a software-first mindset built on a robust and open ecosystem like RISC-V. We combine RISC-V vectors and SiFive Intelligence Extensions to offer highly power- and memory-efficient compute without sacrificing programmability. RISC-V was invented by the founders of SiFive to build an instruction set architecture for the new golden era of computing. The new SiFive Intelligence line, which is available now, combines all these elements to deliver the flexibility and performance needed by modern AI platforms.

OpenFive Tapes Out SoC for Advanced AI/HPC Solutions on TSMC 5nm Technology

Tremendous progress has been made in the last year bringing RISC-V vector (RVV) extensions to market in both hardware implementations and supporting compiler technologies.

The best just got better--SiFive’s latest Processor Core IP Portfolio release

Enabling more choice for Next-Generation Heterogeneous Compute Platforms

SiFive RISC-V processors are powering flash drives in production as well as addressing emerging In-Storage Computing (ISC) needs

Creating a RISC-V PC Ecosystem for Linux application development

Faster, More Efficient SiFive 7-Series Core IP

A note from SiFive President & CEO, Patrick Little

Building a secure foundation using the concept of randomness seems, on the surface, counter-intuitive.

The RISC-V Vector extension (RVV) enables processor cores based on the RISC-V instruction set architecture to process data arrays, alongside traditional scalar operations to accelerate the computation of single instruction streams on large data sets.

OpenFive is a solution-centric and processor agnostic custom silicon business unit dedicated to building optimized domain-specific SoCs

SiFive's Best Processor Portfolio Is Here

A Message From The CEO

Published by SemiWiki.

The SiFive Mission

Access, Observe, Control

This is the third in a series of blogs about Domain-specific accelerators (DSAs), which are becoming increasingly common in system-on-chip (SoC) designs. Part #1 addressed the challenges associated with data transfers between DSAs and the core complex, and showed how RISC-V offers a unique opportunity to optimize fine-grain communication between them and improve core-DSA interaction performance. Part #2 addressed the challenges associated with point-to-point ordering between cores and DSA memory, and how RISC-V offers a unique opportunity to optimize high-bandwidth communication between cores and DSAs. This third installment will focus on the challenges associated with data transfers between DSA and memories, such as DDR, LPDDR or HBM, and explain how SoCs based on RISC-V can use an alternate approach to write the data directly to memory.

Domain-specific accelerators (DSAs) are becoming increasingly common in system-on-chip (SoC) designs. A DSA provides higher performance per watt by optimizing the specialized function it implements. Examples of DSAs include compression/decompression units, random number generators and network packet processors. A DSA is typically connected to the core complex using a standard IO interconnect, such as an AXI bus (Figure 1).

A Note from Chris Lattner, New SVP of Platform Engineering

This is the second in a series of blogs about Domain-specific accelerators (DSAs), which are becoming increasingly common in SoCs. Part #1 addressed the challenges associated with data transfers between DSAs and the core complex, and showed how RISC-V offers a unique opportunity to optimize fine-grain communication between them and improve core-DSA interaction performance.

The RISC-V ISA is rapidly becoming the new standard for compute, and has literally spawned a worldwide revolution in the semiconductor industry. At the beginning of 2019, SiFive set out to foster education about SiFive’s RISC-V based technologies and to advance deeper collaboration within the global hardware community. We succeeded! We completed 52 Tech Symposiums/Workshops reaching 26 countries and six continents – reaching all corners of the world. Over 10,000 people attended these events, demonstrating strong attraction to RISC-V in not only industry, but in academia as well.

Introducing the new SiFive U8-Series Core IP

Securing The RISC-V Revolution

We’re confirming seats in Portland and Seattle for the Pacific Northwest leg of our worldwide 2019 SiFive Tech Symposiums. We are pleased to have Mentor, A Siemens Business as our co-host, and Lauterbach, a leader in microprocessor development tools, as our partner in both cities.

Today, SiFive is excited to announce the general availability of the Q3 2019 Engineering Update, packed with new features, tools, and improvements. In the first SiFive quarterly update, we discussed the transition from the “Information Age” to the “Experience Age.” In the Q3 Engineering Update, SiFive is delivering on our customer experience mantra: “Make It Easy” and “Get It Right.” - two principles at the heart of our Sales, FAE, and Engineering mindset for supporting and enabling our customers.

The second SiFive quarterly engineering release has arrived, and includes some great new Trace & Debug features. Static source code analysis may not offer a complete view of real world operation. Real time analysis enabled via tracing permits a deeper insight into the interactions of software and hardware to accelerate development, debug, validation of modern, configurable SoC designs.

For consumers of low-end processors, the Dhrystone benchmark can be a valuable tool for estimating performance. Due to the nature of the Dhrystone benchmark, high-end Application Processor performance is incompletely represented by a Dhrystone score. For processor providers a Dhrystone score is a commonly used metric for instruction throughput comparison in early stage evaluation.

Highlights From the SiFive Tech Symposiums

The Information age transformed the world, fueled by silicon chips that became more powerful and more cost-effective every 18 months. The thinking of silicon design was led by engineers in the pursuit of faster, smaller transistors. As the Experience Age transcends the Information Age, the law underneath the technology changes from what’s possible, to what’s needed. Now, the ability to create purpose-built processors – secure, fast, efficient, and cost-effective – is the defining characteristic inside products that change lives through improved experiences and abilities.

With the move to a quarterly release program (see: Silicon At Speed Of Software), SiFive is innovating in the hardware space at an unprecedented pace. In the SiFive Core Designer update and the Core IP update we learned about new features being added to SiFive Core IP and the ability to quickly access those features via SiFive Core Designer, SiFive's Software-as-a Service (SaaS) application. We have also been hard at work making sure that our software enablement is just as configurable, and easy to access, as our hardware.

SiFive Core Designer (SCD) unlocks new possibilities by enabling engineers to explore the architectural design space of a CPU. With our Software-as-a Service (SaaS) application, customers can create and customize RISC-V core IP -- from their laptops.

The traditional cadence for microarchitecture updates is usually tied to process technology nodes or ground-up redesigns. The SiFive Core IP portfolio offers scalable microarchitectures from efficient application multi-core processors capable of running Linux, to tiny, power-sipping cores suitable for the most area constrained design points. The SiFive quarterly update program delivers key improvements, new features, and more capabilities to SiFive Core IP in a measured, methodical way. Here’s all the information you need on the SiFive Core IP Series and the latest updates!

As we make our way around the world meeting and engaging with others in the semiconductor and hardware design community, we are seeing an increased interest in RISC-V based hardware innovation. This is due in large part to the emergence of market-ready RISC-V core IP, development tools and silicon solutions based on cloud-based design platforms that facilitate the creation of custom SoC solutions for edge computing, AI, IoT, wearable, server and other target vertical markets.

We just wrapped up our six-city tour in Europe, which included Cambridge, Grenoble, Stockholm, Moscow, Munich and Amsterdam. Together with our co-hosts, Qamcom, Syntacore, Imagination Technologies and Mentor; and ecosystem partners, Rambus, IAR Systems, UltraSoC, Antmicro, SecureRF, Credo and lowRISC, we engaged with over 500 responses/registrations throughout the tour.

Hello Cambridge, Grenoble, Stockholm, Moscow, Munich and Amsterdam

Our 2019 global symposiums and workshops have been hugely successful in promoting the RISC-V ISA and fostering expansive collaboration within the open-source community. It's invigorating to see how the worldwide semiconductor ecosystem is energized and mobilized by the open ISA. One of the areas receiving the most attention is embedded intelligence. The RISC-V ISA is enabling designers and innovators to actively pursue solutions that employ enhanced embedded intelligence at the edge. The real-world applications of this are awesome and we are inspired by what we see!

During the afternoon session of the Symposium, Jack Kang, SiFive VP sales then addressed the RISC-V Core IP for vertical markets from consumer/smart home/wearables to storage/networking/5G to ML/edge. Embedding intelligence from the edge to the cloud can occur with U Cores 64-bit Application Processors, S Cores 64-bit Embedded Processors, and E Cores 32-bit Embedded Processors. Embedded intelligence allows mixing of application cores with embedded cores, extensible custom instructions, configurable memory for application tuning and other heterogeneous combination of real time and application processors. Some recently announced products is Huami in Wearable AI, Fadu SSD controller in Enterprise, Microsemi/Microchip upcoming FPGA architecture. Customization comes in 2 forms, customization of cores by configuration changes and by custom instructions in a reserved space on top of the base instruction set and standard extensions, guaranteeing no instruction collision with existing or future extensions, and preserving software compatibility.

HiFive1 Rev B: The Second Generation HiFive1 Dev Board and the Freedom Everywhere SoC, FE310

SiFive held a RISC-V Technology Symposium on February 26 at the Computer History Museum in Mountain View. Keith Witek, SiFive SVP Corporate Development and Strategy kicked off the event and introduced the first keynote speaker Martin Fink, Western Digital CTO, at the time acting CEO of the RISC-V Foundation (as of this writing, Calista Redmond was just appointed the new CEO of the RISC-V Foundation). He shared a slide showing the growing RISC-V ecosystem from tools vendors, to IP/semi chip providers and design/foundry services. He stated that, moving forward, the areas of focus will include standards/specs, ecosystem growth, awareness and education.

We welcomed over 600 attendees to the SiFive Tech Symposiums in Austin, Mountain View and Boston. The feedback we received is flattering. We heard comments like, “You guys are going bold, and we love it!” and “SiFive has built a solid team with good breadth of business and technology expertise,” and “Very different take – and someone is addressing the pain point for hardware folks, finally!” There was a great deal of energy in the crowd, and people were thoroughly engaged all day long. Here’s a look back at some of the highlights:

In 2018, we hosted several RISC-V technology symposia in India, China and Israel. These events were very successful in fueling the growing momentum surrounding the RISC-V ISA in these countries. It turns out that these events were just the tip of the iceberg. In 2019, SiFive is greatly expanding its reach by hosting over 50 SiFive Tech Symposia in cities throughout the world. The first leg of the global tour begins in the USA. In collaboration with our co-hosts and partner companies, we aim to foster deeper education, collaboration and engagement within the open-source community.

In 2018, we saw the rapid proliferation of the RISC-V architecture, with commercial deployments of SiFive Core IP in a broad range of applications ranging from wearables and edge devices to the enterprise core. Modern compute workloads are evolving rapidly and require the ability to scale performance on demand and very often have real-time, deterministic requirements. This diversity of workloads poses computational challenges that can be resolved only by domain-specific architectures. With the advent of 5G, core networks are transforming from hierarchical models in which intelligence was concentrated at the core to a decentralized structure where intelligence is getting distributed to the edge.

Published by SemiWiki.

We are really excited to see Wave Computing announce the open MIPS ISA and R6 processor core. SiFive would like to congratulate and welcome MIPS to the open-source community with its MIPS Open Initiative. The addition of the MIPS 32 and 64-bit open ISA will provide more options freely available to SoC designers. The open-source processor community, based on the RISC-V ISA, is thriving, and the addition of MIPS underscores the fact that the world is indeed becoming more open. Open ISA enables chip designers, innovators and academics to explore and expand their designs. The ability to add extensions to the base ISA makes it an attractive option for applications requiring special configurations. Chip designers no longer have to settle for an off-the-shelf processor. SiFive RISC-V cores have enabled a high degree of customization, which our customers have loved and used to create designs at 1/3 the power and area versus other solutions.

Hi everyone! I'm Nathaniel Graff, a software engineer here at SiFive, and I'm excited to tell you about the most recent release of Zephyr RTOS, version 1.13.0! Zephyr RTOS is a real-time operating system hosted by The Linux Foundation, featuring support for a myriad of different platforms, architectures, and targets including SiFive's E-series CoreIP, and the HiFive 1 development board.

It's been another week, which means it's time to find another host for "Last Week in RISC-V". This week we're going to attempt a blog at riscv.org, which will hopefully be a good long-term home for this series of articles.

This week's entry is fairly short, but it does come with one major improvement: we now have a mailing list! I've decided to create a Google Group at SiFive, and while I understand that's not ideal it's the best I can figure out for now. The Google Groups interface is quick clunky, so if you're looking for archives it's probably still best to use GitHub. Hopefully this makes it easier for people to find the mailing list.

Introduction to Linux Kernel Development

GNU Tools Cauldron Trip Report, Part 2

This is the last version of "Last Week in RISC-V" that I plan on sending to the various mailing lists, as we'll be posting the rest of them on SiFive's Blog. I didn't get any contributions, but I also haven't gotten through my email yet -- sorry if I missed anything that's been sent it, but I'm not too far behind so I should have everything read from this week by the end of next week.

The FU540-C000, which is available on the HiFive Unleashed development board, is a Linux capable board based on the open source Freedom platform. We built this chip to drive RISC-V Linux development, and it's been incredibly successful. In the three months since we started shipping the board the RISC-V Linux distribution porting effort, with Debian and Fedora leading the charge, has come farther that it had come in the previous 5 years. It's been incredible watching the open source community get behind the RISC-V ISA, and the level of progress has exceeded anything we could have predicted at the beginning of this year.

Welcome to the first issue of "Last Week in RISC-V", a weekly newsletter tracking the RISC-V community. This newsletter was born out of a discussion in SiFive's internal RISC-V software team and I'm compiling it so it'll have a somewhat heavy focus on the open source software community for now as that's where I spend most of my time. The general idea behind "Last Week in RISC-V" is that the RISC-V ecosystem is getting big enough that it's impossible for any single person to track everything going on. For a while we had the patches mailing list, but we've outgrown a single mailing list for all development -- plus, this mailing list is just for patches to core RISC-V software components so it isn't wide enough in scope to cover everything going on it the RISC-V ecosystem.

On Wednesday, July 25th, SiFive had the pleasure of hosting Girl Geek X at our offices in San Mateo. Girl Geek X is a brilliant organization with the aim of connecting women across companies large and small for the purposes of networking and sharing career advice in the fast-paced tech industry. Over the past 10 years, Girl Geek X has grown from a 400-person dinner hosted by Google to a well-known Bay Area group with a membership base of more than 15,000.

Last week SiFive launched the new E2 Series RISC-V Core IP. The E2 Series represents SiFive’s smallest, most efficient Core IP Series and is targeted specifically for embedded microcontroller designs. One of the reasons it is great for microcontroller applications is because of its extremely small area footprint, just 0.023mm² in 28nm for the entire E20 Standard Core! Another reason it's great for the embedded market is its configurability. The E2 Series can be configured even smaller than the E20 Standard Core by removing things like the Interrupt Controller and support for the M extension. Another major reason the E2 Series is great for microcontroller applications is its support for the new RISC-V Core Local Interrupt Controller (CLIC) which allows for extremely low latency interrupt operation, hardware preemption, and hardware prioritization of all interrupts. The CLIC specification is a result of collaboration between RISC-V members in the RISC-V Foundation’s Fast Interrupts Technical Group and the draft specification can be found here.

Good news, HiFive fans! A limited supply of HiFive Unleashed Development Kits are now available on CrowdSupply for purchase.

We recently announced that Intel Capital participated in our Series C funding round! Our CEO, Naveed Sherwani, revealed the investment earlier this month at the Intel Capital Global Summit.

We’re very happy to announce that Intel Capital participated in our recent Series C funding round. The investment was revealed at the Intel Capital Global Summit earlier today.

QEMU 2.12.0 was released on April 24th 2018 and this version is the first official QEMU version to contain the RISC-V port. This is yet another milestone towards the development of the Open Source RISC-V tools on top of the recent acceptance of RISC-V in Linux kernel 4.15 in December last year and GLIBC 2.27 this past February.

Boy have we been busy. Over the last few months, our DesignShare ecosystem has continued to expand, and, this week, we were excited to welcome Dover Microsystems into the program.

First, we are thrilled to have recently announced that we raised $50.6 million in our Series C funding round! We wanted to thank our existing and new investors - including Chengwei Capital, Huami, SK Telecom and Western Digital - for the continued support and new engagement, so we held a party to celebrate!

We’re heading to the Embedded Linux Conference next week, March 12-14, to hold our first hackathon. Developers will be among the first to run code on the HiFive Unleashed board with a chance to take home a board of their own and win a $1,000 cash prize.

Date: Monday, March 12 – Wednesday, March 14
Time: 10:30am Monday – 1:00pm Wednesday
Location: Embedded Linux Conference, Hilton Portland Downtown, Skyline II, Floor 23

As our business continues to grow, the people we hire continue to impact and shape our business more and more.

We recently announced the HiFive Unleashed, a development board for Freedom U540-C000, the world's first Linux-capable RISC-V ASIC. The announcement of this board roughly lined up with the first upstream releases of Linux and glibc that contain RISC-V support. As a result, our news has driven a lot of interest from the open source software community -- that was really the whole point of announcing the board in the first place, so in that sense it's working out very well.

Before we dive into our newsletter, we want to take a moment to talk about the vulnerabilities around Meltdown and Spectre. First off -- and most fortunately -- SiFive’s RISC-V Core IP offerings are not affected by Meltdown and Spectre. Secondly, as the RISC-V Foundation’s statement on these vulnerabilities notes, now is the time for open architecture and open hardware designs to shine.

The recently disclosed speculation-based timing attacks Meltdown and Spectre have received much attention this week—and rightly so. The vulnerabilities these attacks exploit are not limited to a particular instruction-set architecture, nor are they restricted to a single vendor’s implementations. Many processors that rely upon speculation to improve performance are affected, even some that do not use out-of-order execution.

A new year brings new opportunities. Before we dive into 2018, we wanted to take some time to reflect on some of the excitement we experienced over the last couple of months.