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The Blog
SiFive — Nov 20, 2020
SiFive Strengthens Foothold in Storage Applications for Data-Centric AI Computing
SiFive RISC-V processors are powering flash drives in production as well as addressing emerging In-Storage Computing (ISC) needs
SiFive — Oct 29, 2020
The Heart of RISC-V Development is Unmatched
Creating a RISC-V PC Ecosystem for Linux application development
SiFive — Oct 15, 2020
The SiFive 20G1 Update for 7-Series Core IP
Faster, More Efficient SiFive 7-Series Core IP
SiFive — Sep 17, 2020
The Incredible Opportunity For SiFive
A note from SiFive President & CEO, Patrick Little
SiFive — Sep 3, 2020
Randomness is Secure with SiFive Shield HCA
Building a secure foundation using the concept of randomness seems, on the surface, counter-intuitive.
SiFive — Sep 3, 2020
RISC-V Vector Extension Intrinsic Support
The RISC-V Vector extension (RVV) enables processor cores based on the RISC-V instruction set architecture to process data arrays, alongside traditional scalar operations to accelerate the computation of single instruction streams on large data sets.
SiFive — Aug 17, 2020
OpenFive's Customizable Silicon-Focused Solutions
OpenFive is a solution-centric and processor agnostic custom silicon business unit dedicated to building optimized domain-specific SoCs
SiFive — Apr 27, 2020
SiFive’s Approach to Embedding Intelligence Everywhere
Published by SemiWiki.
SiFive — Jan 27, 2020
With SiFive, We Can Change the World
A Note from Chris Lattner, New SVP of Platform Engineering
SiFive — Oct 24, 2019
Incredibly Scalable High-Performance RISC-V Core IP
Introducing the new SiFive U8-Series Core IP
SiFive — Oct 23, 2019
SiFive Shield: An Open, Scalable Platform Architecture for Security
Securing The RISC-V Revolution
SiFive — Sep 13, 2019
Israel is Evolving as a High-Tech Hub, and RISC-V is Playing a Vital Role
SiFive — Jul 22, 2019
Dhrystone Performance Tuning on the Freedom Platform
For consumers of low-end processors, the Dhrystone benchmark can be a valuable tool for estimating performance. Due to the nature of the Dhrystone benchmark, high-end Application Processor performance is incompletely represented by a Dhrystone score. For processor providers a Dhrystone score is a commonly used metric for instruction throughput comparison in early stage evaluation.
SiFive — Jul 17, 2019
The Design Revolution in APAC and Australia
Highlights From the SiFive Tech Symposiums
SiFive — Jun 25, 2019
Silicon At The Speed of Software
The Information age transformed the world, fueled by silicon chips that became more powerful and more cost-effective every 18 months. The thinking of silicon design was led by engineers in the pursuit of faster, smaller transistors. As the Experience Age transcends the Information Age, the law underneath the technology changes from what’s possible, to what’s needed. Now, the ability to create purpose-built processors – secure, fast, efficient, and cost-effective – is the defining characteristic inside products that change lives through improved experiences and abilities.
SiFive — Jun 25, 2019
Freedom in Software and in the Metal
With the move to a quarterly release program (see: Silicon At Speed Of Software), SiFive is innovating in the hardware space at an unprecedented pace. In the SiFive Core Designer update and the Core IP update we learned about new features being added to SiFive Core IP and the ability to quickly access those features via SiFive Core Designer, SiFive's Software-as-a Service (SaaS) application. We have also been hard at work making sure that our software enablement is just as configurable, and easy to access, as our hardware.
SiFive — Jun 25, 2019
When Hardware Roadmaps Look Like Software Roadmaps
The traditional cadence for microarchitecture updates is usually tied to process technology nodes or ground-up redesigns. The SiFive Core IP portfolio offers scalable microarchitectures from efficient application multi-core processors capable of running Linux, to tiny, power-sipping cores suitable for the most area constrained design points. The SiFive quarterly update program delivers key improvements, new features, and more capabilities to SiFive Core IP in a measured, methodical way. Here’s all the information you need on the SiFive Core IP Series and the latest updates!
SiFive — Jun 25, 2019
Three New Core Series Now Available in SiFive Core Designer
SiFive Core Designer (SCD) unlocks new possibilities by enabling engineers to explore the architectural design space of a CPU. With our Software-as-a Service (SaaS) application, customers can create and customize RISC-V core IP -- from their laptops.
SiFive — Jun 10, 2019
The RISC-V Revolution is Sweeping Across the APAC Region and Australia
Join SiFive Tech Symposiums in Tokyo, Daejeon, Pangyo, Hsinchu, Singapore and Sydney
SiFive — May 30, 2019
The Design Revolution in Europe: Highlights From the SiFive Tech Symposiums
We just wrapped up our six-city tour in Europe, which included Cambridge, Grenoble, Stockholm, Moscow, Munich and Amsterdam. Together with our co-hosts, Qamcom, Syntacore, Imagination Technologies and Mentor; and ecosystem partners, Rambus, IAR Systems, UltraSoC, Antmicro, SecureRF, Credo and lowRISC, we engaged with over 500 responses/registrations throughout the tour.
SiFive — May 13, 2019
The SiFive Tech Symposiums are Heading to Six Cities in Europe in May!
Hello Cambridge, Grenoble, Stockholm, Moscow, Munich and Amsterdam
Our 2019 global symposiums and workshops have been hugely successful in promoting the RISC-V ISA and fostering expansive collaboration within the open-source community. It's invigorating to see how the worldwide semiconductor ecosystem is energized and mobilized by the open ISA. One of the areas receiving the most attention is embedded intelligence. The RISC-V ISA is enabling designers and innovators to actively pursue solutions that employ enhanced embedded intelligence at the edge. The real-world applications of this are awesome and we are inspired by what we see!
SiFive — Mar 19, 2019
The Revolution Evolution Continues - SiFive RISC-V Technology Symposium - Part II
During the afternoon session of the Symposium, Jack Kang, SiFive VP sales then addressed the RISC-V Core IP for vertical markets from consumer/smart home/wearables to storage/networking/5G to ML/edge. Embedding intelligence from the edge to the cloud can occur with U Cores 64-bit Application Processors, S Cores 64-bit Embedded Processors, and E Cores 32-bit Embedded Processors. Embedded intelligence allows mixing of application cores with embedded cores, extensible custom instructions, configurable memory for application tuning and other heterogeneous combination of real time and application processors. Some recently announced products is Huami in Wearable AI, Fadu SSD controller in Enterprise, Microsemi/Microchip upcoming FPGA architecture. Customization comes in 2 forms, customization of cores by configuration changes and by custom instructions in a reserved space on top of the base instruction set and standard extensions, guaranteeing no instruction collision with existing or future extensions, and preserving software compatibility.
SiFive — Mar 19, 2019
Freedom Everywhere — Back for Everyone!
HiFive1 Rev B: The Second Generation HiFive1 Dev Board and the Freedom Everywhere SoC, FE310
SiFive — Mar 18, 2019
The Revolution Evolution Continues - SiFive RISC-V Technology Symposium - Part I
SiFive held a RISC-V Technology Symposium on February 26 at the Computer History Museum in Mountain View. Keith Witek, SiFive SVP Corporate Development and Strategy kicked off the event and introduced the first keynote speaker Martin Fink, Western Digital CTO, at the time acting CEO of the RISC-V Foundation (as of this writing, Calista Redmond was just appointed the new CEO of the RISC-V Foundation). He shared a slide showing the growing RISC-V ecosystem from tools vendors, to IP/semi chip providers and design/foundry services. He stated that, moving forward, the areas of focus will include standards/specs, ecosystem growth, awareness and education.
SiFive — Mar 13, 2019
The First Leg of our Global Symposiums is a Wrap, and it was an Enormous Success!
We welcomed over 600 attendees to the SiFive Tech Symposiums in Austin, Mountain View and Boston. The feedback we received is flattering. We heard comments like, “You guys are going bold, and we love it!” and “SiFive has built a solid team with good breadth of business and technology expertise,” and “Very different take – and someone is addressing the pain point for hardware folks, finally!” There was a great deal of energy in the crowd, and people were thoroughly engaged all day long. Here’s a look back at some of the highlights:
SiFive — Feb 21, 2019
The RISC-V Revolution is Going Global This Month, you can join SiFive in Austin, Mountain View, or Boston
In 2018, we hosted several RISC-V technology symposia in India, China and Israel. These events were very successful in fueling the growing momentum surrounding the RISC-V ISA in these countries. It turns out that these events were just the tip of the iceberg. In 2019, SiFive is greatly expanding its reach by hosting over 50 SiFive Tech Symposia in cities throughout the world. The first leg of the global tour begins in the USA. In collaboration with our co-hosts and partner companies, we aim to foster deeper education, collaboration and engagement within the open-source community.
SiFive — Jan 4, 2019
Embedded Intelligence Everywhere
In 2018, we saw the rapid proliferation of the RISC-V architecture, with commercial deployments of SiFive Core IP in a broad range of applications ranging from wearables and edge devices to the enterprise core. Modern compute workloads are evolving rapidly and require the ability to scale performance on demand and very often have real-time, deterministic requirements. This diversity of workloads poses computational challenges that can be resolved only by domain-specific architectures. With the advent of 5G, core networks are transforming from hierarchical models in which intelligence was concentrated at the core to a decentralized structure where intelligence is getting distributed to the edge.
SiFive — Dec 18, 2018
Open Standards Work!
We are really excited to see Wave Computing announce the open MIPS ISA and R6 processor core. SiFive would like to congratulate and welcome MIPS to the open-source community with its MIPS Open Initiative. The addition of the MIPS 32 and 64-bit open ISA will provide more options freely available to SoC designers. The open-source processor community, based on the RISC-V ISA, is thriving, and the addition of MIPS underscores the fact that the world is indeed becoming more open. Open ISA enables chip designers, innovators and academics to explore and expand their designs. The ability to add extensions to the base ISA makes it an attractive option for applications requiring special configurations. Chip designers no longer have to settle for an off-the-shelf processor. SiFive RISC-V cores have enabled a high degree of customization, which our customers have loved and used to create designs at 1/3 the power and area versus other solutions.
SiFive — Oct 30, 2018
Getting Started with Zephyr RTOS v1.13.0 On RISC-V
Hi everyone! I'm Nathaniel Graff, a software engineer here at SiFive, and I'm excited to tell you about the most recent release of Zephyr RTOS, version 1.13.0! Zephyr RTOS is a real-time operating system hosted by The Linux Foundation, featuring support for a myriad of different platforms, architectures, and targets including SiFive's E-series CoreIP, and the HiFive 1 development board.
SiFive — Oct 19, 2018
Last Week in RISC-V: October 19, 2018
It's been another week, which means it's time to find another host for "Last Week in RISC-V". This week we're going to attempt a blog at riscv.org, which will hopefully be a good long-term home for this series of articles.
SiFive — Oct 12, 2018
Last Week in RISC-V: October 12, 2018
This week's entry is fairly short, but it does come with one major improvement: we now have a mailing list! I've decided to create a Google Group at SiFive, and while I understand that's not ideal it's the best I can figure out for now. The Google Groups interface is quick clunky, so if you're looking for archives it's probably still best to use GitHub. Hopefully this makes it easier for people to find the mailing list.
SiFive — Sep 21, 2018
Last Week in RISC-V: Sept 21, 2018
Introduction to Linux Kernel Development
SiFive — Sep 14, 2018
Last Week in RISC-V: Sept 14, 2018
GNU Tools Cauldron Trip Report, Part 2
SiFive — Sep 7, 2018
Last Week in RISC-V: Sept 7, 2018
This is the last version of "Last Week in RISC-V" that I plan on sending to the various mailing lists, as we'll be posting the rest of them on SiFive's Blog. I didn't get any contributions, but I also haven't gotten through my email yet -- sorry if I missed anything that's been sent it, but I'm not too far behind so I should have everything read from this week by the end of next week.
SiFive — Sep 6, 2018
An Open Source Release of the Freedom U540-C000's Bootloader
The FU540-C000, which is available on the HiFive Unleashed development board, is a Linux capable board based on the open source Freedom platform. We built this chip to drive RISC-V Linux development, and it's been incredibly successful. In the three months since we started shipping the board the RISC-V Linux distribution porting effort, with Debian and Fedora leading the charge, has come farther that it had come in the previous 5 years. It's been incredible watching the open source community get behind the RISC-V ISA, and the level of progress has exceeded anything we could have predicted at the beginning of this year.
SiFive — Aug 31, 2018
Last Week in RISC-V: August 31, 2018
Welcome to the first issue of "Last Week in RISC-V", a weekly newsletter tracking the RISC-V community. This newsletter was born out of a discussion in SiFive's internal RISC-V software team and I'm compiling it so it'll have a somewhat heavy focus on the open source software community for now as that's where I spend most of my time. The general idea behind "Last Week in RISC-V" is that the RISC-V ecosystem is getting big enough that it's impossible for any single person to track everything going on. For a while we had the patches mailing list, but we've outgrown a single mailing list for all development -- plus, this mailing list is just for patches to core RISC-V software components so it isn't wide enough in scope to cover everything going on it the RISC-V ecosystem.
SiFive — Jul 31, 2018
SiFive Hosts Girl Geek X and Champions Custom Silicon For All
On Wednesday, July 25th, SiFive had the pleasure of hosting Girl Geek X at our offices in San Mateo. Girl Geek X is a brilliant organization with the aim of connecting women across companies large and small for the purposes of networking and sharing career advice in the fast-paced tech industry. Over the past 10 years, Girl Geek X has grown from a 400-person dinner hosted by Google to a well-known Bay Area group with a membership base of more than 15,000.
SiFive — Jul 12, 2018
Interrupts on the SiFive E2 Series
Last week SiFive launched the new E2 Series RISC-V Core IP. The E2 Series represents SiFive’s smallest, most efficient Core IP Series and is targeted specifically for embedded microcontroller designs. One of the reasons it is great for microcontroller applications is because of its extremely small area footprint, just 0.023mm2 in 28nm for the entire E20 Standard Core! Another reason it's great for the embedded market is its configurability. The E2 Series can be configured even smaller than the E20 Standard Core by removing things like the Interrupt Controller and support for the M extension. Another major reason the E2 Series is great for microcontroller applications is its support for the new RISC-V Core Local Interrupt Controller (CLIC) which allows for extremely low latency interrupt operation, hardware preemption, and hardware prioritization of all interrupts. The CLIC specification is a result of collaboration between RISC-V members in the RISC-V Foundation’s Fast Interrupts Technical Group and the draft specification can be found here.
SiFive — Jun 4, 2018
Unleashing More Fun Under the Sun
Good news, HiFive fans! A limited supply of HiFive Unleashed Development Kits are now available on CrowdSupply for purchase.
SiFive — May 30, 2018
The SiFive Download - What's Up Next?
We recently announced that Intel Capital participated in our Series C funding round! Our CEO, Naveed Sherwani, revealed the investment earlier this month at the Intel Capital Global Summit.
SiFive — May 8, 2018
Intel Capital Investment Boosts Vision for the Future
We’re very happy to announce that Intel Capital participated in our recent Series C funding round. The investment was revealed at the Intel Capital Global Summit earlier today.
SiFive — Apr 25, 2018
RISC-V QEMU Part 2: The RISC-V QEMU port is upstream
QEMU 2.12.0 was released on April 24th 2018 and this version is the first official QEMU version to contain the RISC-V port. This is yet another milestone towards the development of the Open Source RISC-V tools on top of the recent acceptance of RISC-V in Linux kernel 4.15 in December last year and GLIBC 2.27 this past February.
SiFive — Apr 17, 2018
Dover Microsystems Brings Real-Time Chip Security to SiFive’s DesignShare
Boy have we been busy. Over the last few months, our DesignShare ecosystem has continued to expand, and, this week, we were excited to welcome Dover Microsystems into the program.
SiFive — Apr 16, 2018
The SiFive Download - The Next Revolution is Here!
First, we are thrilled to have recently announced that we raised $50.6 million in our Series C funding round! We wanted to thank our existing and new investors - including Chengwei Capital, Huami, SK Telecom and Western Digital - for the continued support and new engagement, so we held a party to celebrate!
SiFive — Mar 6, 2018
The SiFive Download - Are you ready to UNLEASH your genius?
We’re heading to the Embedded Linux Conference next week, March 12-14, to hold our first hackathon. Developers will be among the first to run code on the HiFive Unleashed board with a chance to take home a board of their own and win a $1,000 cash prize.
SiFive — Mar 3, 2018
All Aboard, Part 11: RISC-V Hackathon, Presented by SiFive
Date: Monday, March 12 – Wednesday, March 14
Time: 10:30am Monday – 1:00pm Wednesday
Location: Embedded Linux Conference, Hilton Portland Downtown, Skyline II, Floor 23
SiFive — Mar 1, 2018
Welcome Aboard, Sunil Shenoy!
As our business continues to grow, the people we hire continue to impact and shape our business more and more.
SiFive — Feb 20, 2018
All Aboard, Part 10: How to Contribute to the RISC-V Software Ecosystem
We recently announced the HiFive Unleashed, a development board for Freedom U540-C000, the world's first Linux-capable RISC-V ASIC. The announcement of this board roughly lined up with the first upstream releases of Linux and glibc that contain RISC-V support. As a result, our news has driven a lot of interest from the open source software community -- that was really the whole point of announcing the board in the first place, so in that sense it's working out very well.
SiFive — Jan 23, 2018
The SiFive Download - Ringing in 2018 with Fresh Faces and Big Resolutions
Before we dive into our newsletter, we want to take a moment to talk about the vulnerabilities around Meltdown and Spectre. First off -- and most fortunately -- SiFive’s RISC-V Core IP offerings are not affected by Meltdown and Spectre. Secondly, as the RISC-V Foundation’s statement on these vulnerabilities notes, now is the time for open architecture and open hardware designs to shine.
SiFive — Jan 5, 2018
SiFive Statement on Meltdown and Spectre
The recently disclosed speculation-based timing attacks Meltdown and Spectre have received much attention this week—and rightly so. The vulnerabilities these attacks exploit are not limited to a particular instruction-set architecture, nor are they restricted to a single vendor’s implementations. Many processors that rely upon speculation to improve performance are affected, even some that do not use out-of-order execution.
SiFive — Jan 3, 2018
A Look Back: 7th RISC-V Workshop
A new year brings new opportunities. Before we dive into 2018, we wanted to take some time to reflect on some of the excitement we experienced over the last couple of months.
SiFive — Dec 20, 2017
RISC-V QEMU Part 1: Privileged ISA v1.10, HiFive1 and VirtIO
This post covers recent development in RISC-V QEMU, the open source machine emulator and virtualizer. We’ve been playing a game of catch-up with the hardware folks so that we can match the capabilities of the Freedom U500 SDK. We’re not quite there yet, but we’ve made some important improvements that will allow for a more usable emulator.
SiFive — Dec 11, 2017
All Aboard, Part 9: Paging and the MMU in the RISC-V Linux Kernel
This entry will cover the RISC-V port of Linux's memory management subsystem. Since the vast majority of the memory management code in Linux is architecture-independent, the vast majority of our memory management code handles interfacing with our MMU, defining our page table format, and interfacing with drivers that have memory allocation constraints.
SiFive — Dec 5, 2017
All Aboard, Part 8: The RISC-V Linux Port is Upstream!
As some of you may have heard, the RISC-V Linux port has been accepted into Linus' tree and is slated to release as part of 4.15. While this is a major milestone, we're far from done in Linux kernel land and there's a whole lot of work left to be done in userspace.
SiFive — Nov 30, 2017
A New Season, New Partnerships and a New Frontier - The SiFive Download, Part IV
These last few months have been equal parts busy, exciting, and promising. We are eager to catch you up on the latest happenings at SiFive and within the RISC-V ecosystem as a whole.
SiFive — Nov 16, 2017
Awards Season Brings Big Surprises
It’s that time of year again--awards season, the time when companies submit their best-of-year products and initiatives for consideration by industry watchers and judging panels. It’s a familiar, fairly predictable cycle, but sometimes it can take one by surprise.
SiFive — Nov 15, 2017
Analog Bits Clocks into the DesignShare Ecosystem
Our DesignShare family is growing, and we’re thrilled to announce that Analog Bits, the industry’s leading provider of low-power mixed-signal IP solutions, is now a part of the ecosystem.
SiFive — Nov 9, 2017
The DesignShare Ecosystem Expands Its Catalog of IP to include eMemory’s Logic NVM
It’s been a fantastic few months for us with new initiatives and industry recognitions, and we’re excited to share more great news. Earlier this month, we welcomed eMemory, the IP provider of logic-based, non-volatile memory (Logic NVM), as the latest company to join the DesignShare movement!
SiFive — Oct 23, 2017
All Aboard, Part 7: Entering and Exiting the Linux Kernel on RISC-V
Continuing our journey into the RISC-V Linux kernel port, this week we'll discuss context switching. Context switching is one of the more important parts of an architecture port: it is all but impossible to completely abstract away the details of entering and exiting the kernel, Since this is on many critical paths (system calls and scheduling) it must go fast, but since it's the one line of protection the kernel has from userspace it must also be secure.
SiFive — Oct 11, 2017
A Core By Any Other Name...
With all apologies to Shakespeare, would a core by any other name still hit the sweet spot in the market for those looking for cost-effective custom silicon?
SiFive — Oct 10, 2017
Welcome - The SiFive Download, Part III
Earlier this month, we took a huge step in democratizing access to custom silicon when we unveiled our newest core, the U54-MC Coreplex - the industry’s first RISC-V based, 64-bit, quadcore application processor with support for full featured operating systems including Linux, Unix and FreeBSD.
SiFive — Oct 9, 2017
All Aboard, Part 6: Booting a RISC-V Linux Kernel
This post begins a short detour into Linux land, during which we'll be discussing the RISC-V Linux kernel port. SiFive has recently announced the Linux-capable U54-MC RISC-V Core IP, and our Linux port was recently submitted to linux-next, Linux's staging branch, so assuming that everything goes smoothly we should be merged at the end of the next merge window. Along with Linux we should soon have the full suite of core system components upstream, both for embedded systems (via binutils, GCC, and newlib) and larger (via binutils, GCC, glibc, and Linux).
SiFive — Oct 6, 2017
Introducing the U54-MC RISC-V Core IP – The First RISC-V Core with Linux Support
Since we launched the industry’s first open-source RISC-V SoC back in July of last year, we’ve had the pleasure of pushing the boundaries of the RISC-V ecosystem and have been delighted by the support that SiFive – and RISC-V – has gained from system designers and Makers alike.
SiFive — Sep 18, 2017
All Aboard, Part 5: Per-march and per-mabi Library Paths on RISC-V Systems
A previous blog
described how the
-march
and -mabi
command-line arguments to GCC can be used to
control code generation for the sources you compile as a user, but most
programs require linking against system libraries in order to function
correctly. Since users generally don't want to compile every library
along with their program, either because they're too complicated or
because they're meant to be shared, a mechanism is needed for linking against
the correct set of system libraries to match the ISA of the user's
target system and the ABI of the user's generated code.
SiFive — Sep 12, 2017
The DesignShare Ecosystem Grows with the Addition of UltraSoC’s Embedded Analytics IP
It’s been a busy summer for us. Our days have been filled with many prospect, customer and partner meetings with teams looking to leverage RISC-V in their roadmap. Last week, we announced the outcome of one of those meetings: UltraSoC, a provider of on-chip monitoring and analytics IP, is the latest company to join the DesignShare movement.
SiFive — Sep 12, 2017
RISC-V 101 Webinar
This one-hour webinar is for Embedded Developers who are interested in learning more about the RISC-V architecture. It covers areas such as the Register File, Instruction Types, Modes, Interrupts, and Control and Status Registers. Prior knowledge of RISC-V is not necessary, but having a basic understanding of Computer Architecture is beneficial.
SiFive — Sep 11, 2017
All Aboard, Part 4: The RISC-V Code Models
The RISC-V ISA was designed to be both simple and modular. In order to achieve these design goals, RISC-V minimizes one of the largest costs in implementing complex ISAs: addressing modes. Addressing modes are expensive both in small designs (due to decode cost) and large designs (due to implicit dependencies). RISC-V only has three addressing modes:
SiFive — Aug 29, 2017
Welcome - The SiFive Download, Part II
On August 15, we announced that regarded industry veteran Naveed Sherwani has joined SiFive as CEO. We invited him to share his vision for the company and his optimism for fomenting a revolution in the semiconductor industry.
SiFive — Aug 28, 2017
All Aboard, Part 3: Linker Relaxation in the RISC-V Toolchain
Last week's blog entry discussed relocations and how they apply to the RISC-V toolchain. This week we'll be delving a bit deeper into the RISC-V linker to discuss linker relaxation, a concept so important it has greatly shaped the design of the RISC-V ISA. Linker relaxation is a mechanism for optimizing programs at link-time, as opposed to traditional program optimization which happens at compile-time. This blog will follow an example linker relaxation through the toolchain, demonstrate an example of how linker relaxations meaningfully improve the performance of a real program and introduce a new RISC-V relocation. We'll shy away from discussing the impact of linker relaxations on the RISC-V ISA, until another blog entry.
SiFive — Aug 24, 2017
Our New Partnership with Rambus and the DesignShare Economy
As we continue to expand our product offerings to better serve the rapidly growing RISC-V and SiFive community, we are always looking to work with companies (big and small) who share our vision.
SiFive — Aug 21, 2017
All Aboard, Part 2: Relocations in ELF Toolchains
Our first stop on our exploration of the RISC-V toolchain will be an overview of ELF relocations and how they are used by the RISC-V toolchain. We'll shy away from discussing linker relaxations and their impact on performance for a follow-up blog post so this doesn't get too long. The example has been carefully constructed to be unrelaxable as to avoid confusion. Additionally we're only going to discuss the relocations used by statically linked executables, avoid discussing position independent executables and forget about thread local storage -- like linker relaxation, all of those warrant a whole post on their own. There will be a lot more to come about relocations in later blog posts.
SiFive — Aug 14, 2017
All Aboard, Part 1: The -march, -mabi, and -mtune arguments to RISC-V Compilers
Before we can board the RISC-V train, we'll have to take a stop
at the metaphorical ticket office: our machine-specific GCC command-line
arguments. These arguments all begin with -m
, and are all specific to
the RISC-V architecture port. In general, we've tried to match existing
conventions for these arguments, but like pretty much everything else
there are enough quirks to warrant a blog post. This blog discusses the
arguments most fundamental to the RISC-V ISA: the -march
, -mabi
, and
-mtune
arguments.
SiFive — Aug 7, 2017
All Aboard, Part 0: Introduction
I'm Palmer Dabbelt, a software engineer at SiFive and a maintainer of various RISC-V ports. I've been working with the RISC-V ISA for a few years, and it's finally starting to get ready for prime-time. We're not yet upstream in Linux or glibc, but hopefully by the end of the year we'll have the core set of system software in the relevant upstream repositories -- at which point distributions can begin porting to RISC-V and users can begin using our software. I started working with RISC-V before the user ISA had been finalized (at least v2 of the user ISA, the real one :)) and it's almost a bit scary how real things have gotten over the last few years.
SiFive — Jul 11, 2017
The SiFive Download: A Year in Review
Welcome to the first iteration of our bi-monthly newsletter, The SiFive Download! On a regular cadence, we will plan to give you a download on all things SiFive – from the events we will be attending to the articles we’ve been featured in. This newsletter is intended to give you a glimpse under the SiFive hood.
SiFive — Jun 14, 2017
The FE310 is in a Museum – Which is Pretty Cool
It’s been quite busy the past month and change for SiFive and the RISC-V community. On May 4, we unveiled our RISC-V Core IP, radically redefining the process by which you can license and buy custom IP. The RISC-V Core IP launch was followed by a panel at Maker Faire Bay Area, where we got to chat with American computer engineering pioneer Dave Patterson and other panelists about RISC-V and the future of open-source hardware (pictured below).