SiFive Performance
SiFive Performance P500
The SiFive Performance™ P500 application processor features a thirteen-stage, triple-issue, out-of-order pipeline compatible with the RISC-V RV64GBC ISA. The Performance P500 scales up to four-core complex configurations while delivering 30% higher performance in less than half the area of a comparable Arm® Cortex®-A75.
SiFive Performance P500 Key Features
- Breakthrough RISC-V performance
- Multi-core, multi-cluster processor configuration, up to 8 cores
- 3x Performance per mm2 compared to Arm® Cortex®-A75
- Performance >8.6 SpecINT2k6/GHz, higher single thread performance than Arm Cortex-A75
- P500 Core Architectural Features
- 64-bit RISC-V core with Sv39/Sv48 Virtual Memory Support
- Three Issue, out-of-order pipeline tuned for scalable performance
- Private L2 Caches and Streaming Prefetcher for improved memory performance
- SECDED ECC with Error Reporting
- Enabling next generation applications
- Cache stashing to L3 for tightly coupled accelerators
Performance P500 Development Kit
Dev Kit Deliverables
- RTL Evaluation
- Test Bench RTL
- Software Development Kit
- FPGA Bitstream
- Documentation
Core Evaluation
From idea to reality.
Ready to see your code in action? The SiFive Performance P500 Development Kit enables evaluation of SiFive RISC-V Core IP.
Key Deliverables
Evaluation RTL
- Full-Functional, synthesizable Verilog RTL
- Run it in your own simulator
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