What’s being said about SiFive
In the News
SiFive — Dec 4, 2018
SiFive leads RISC-V ecosystem at inaugural summit with range of cores, RISC-V silicon, proof points, demonstrations, partnerships, talks and panels
SiFive — Dec 4, 2018
Industry's First RISC-V SoC FPGA Architecture Brings Real-Time to Linux, Giving Developers the Freedom to Innovate in Low-Power, Secure and Reliable Designs
Demonstrations at RISC-V Summit Dec. 4-5 to Show Size, Power and Performance Benefits of Integrating PolarFire SoC's Hard CPU Subsystem with Programmable Logic
SiFive — Dec 4, 2018
Establish partnership for delivering increased possibilities for powerful RISC-V implementations
SiFive — Oct 31, 2018
Newly unveiled features and continued RISC-V investment in domain-specific architectures enable innovations in 5G, networking, storage, artificial intelligence and sensor fusion
TechCrunch — Apr 2, 2018
With the race to next-generation silicon in full swing, the waterfall of venture money flowing into custom silicon startups is already showing an enormous amount of potential for some more flexible hardware for an increasingly changing technology landscape — and Naveed Sherwani hopes to tap that for everyone else.
SHIFT Communications for SiFive
SiFive — Feb 12, 2019
Powerful and engaging events advance global knowledge about the RISC-V ISA and foster greater collaboration and opportunity within the open-source community
Rambus — Dec 3, 2018
At the RISC-V Summit, Rambus is demonstrating our programmable root of trust core that provides secure processing based on the RISC-V architecture and incorporating industry-leading hardware security and anti-tamper capabilities. The Rambus CryptoManager Root of Trust is designed for applications from networking to automotive to IoT.
SiFive — Nov 26, 2018
Latest contribution to ecosystem enables connectivity solutions for storage, networking, artificial intelligence, accelerators and high-performance computing applications
SiFive — Nov 16, 2018
Mohit Gupta will oversee the rapidly expanding DesignShare program
SiFive — Oct 22, 2018
Berkeley SkyDeck Launches First Official ‘Chip Track’ for Startups to Help Bring Silicon Back to Silicon Valley
Berkeley SkyDeck Collaborates with TSMC, Cadence, and SiFive to Provide Expertise and Support for its New Accelerator Chip Track
SiFive — Oct 2, 2018
SAN MATEO, Calif. – Oct. 2, 2018 – SiFive, the leading provider of commercial RISC-V processor IP, today announced the appointment of Keith Witek as Senior Vice President of Corporate Development and General Counsel.
SiFive — Sep 13, 2018
SAN MATEO, Calif. – Sept. 13, 2018 – SiFive, the leading provider of commercial RISC-V processor IP, today announced that Wasiela, a provider of innovative PHY-layer IP from the system and algorithmic levels all the way to implementation, has joined the DesignShare ecosystem. The availability of Wasiela encryption, forward error correction (FEC) and connectivity IP through the program will ease the development of reliable and secure high-throughput data communications for the RISC-V platform.
SiFive — Aug 21, 2018
SAN MATEO, Calif. – Aug. 21, 2018 – SiFive, the leading provider of commercial RISC-V processor IP, today announced that ASIC Design Services, a design house, IP provider, and a distributor for FPGA and EDA software, has joined the DesignShare ecosystem. Through this partnership, ASIC Design Services will provide its Core Deep Learning (CDL) technology that accelerates Convolutional Neural Networks (CNNs) on power-constrained embedded hardware platforms.
SiFive — Aug 20, 2018
SiFive Announces First Open-Source RISC-V-Based SoC Platform with Nvidia Deep Learning Accelerator Technology
Cupertino, Calif. – August 20, 2018 – SiFive, the leading provider of commercial RISC-V processor IP, today announced the first open-source RISC-V-based SoC platform for edge inference applications based on NVIDIA's Deep Learning Accelerator (NVDLA) technology.
SiFive — Aug 14, 2018
SAN MATEO, Calif. – Aug. 14, 2018 – SiFive, the leading provider of commercial RISC-V processor IP, today announced a new member to its growing DesignShare economy: OPENEDGES, a provider of IPs for smart computing. The partnership makes available OPENEDGES’ ORBITTM Memory Controller IP to system developers via DesignShare, which enables customers incorporate world-class IP into their prototypes without having to pay for IP costs upfront.
SiFive — Aug 7, 2018
SAN MATEO, Calif. and SANTA CLARA, Calif. – August 7, 2018 – SiFive, the leading provider of commercial RISC-V processor IP, and FADU, a fabless company developing solutions and systems for the memory and storage market, today announced the availability of FADU’s Annapurna SSD Controller and FADU Bravo Series Enterprise SSD, powered by SiFive’s industry leading 64-bit, E51 multicore RISC-V Core IP.
SiFive — Aug 7, 2018
SAN MATEO, Calif. and SAN JOSE, Calif. – August 7, 2018 – SiFive, the leading provider of commercial RISC-V processor IP, and eSilicon, an independent provider of FinFET-class ASICs, market-specific IP platforms and advanced 2.5D packaging solutions, today announced that, after extensive review and testing of available options in the market, eSilicon has selected the SiFive E2 Core IP Series as the best solution for its next-generation SerDes IP at 7nm.
SiFive — Aug 7, 2018
Mobiveil Inc. and SiFive partner to develop RISC-V based configurable SSD Platform For Data Center and Enterprise storage Applications
Milpitas, Calif. – August 7, 2018 – Mobiveil, Inc. a provider of Serial Interconnect IP blocks and platforms targeting Flash Storage, IoT and Communication markets, has selected SiFive’s multicore E51 and U54 Core IPs to power Mobiveil’s new advanced configurable Gen4 PCIe-NVMe SSD platform offering a high performance and low power SSD solution for data center storage applications. SiFive’s heterogenous, coherent RISC-V core complex in a high-performance FPGA along with Mobiveil's Silicon Proven IP blocks (Gen4 PCIe, NVMe , LDPC, ONFI and Memory controller IP), provides data center customers a platform to develop their unique applications on RISC-V processors.
SiFive — Jul 27, 2018
SAN MATEO, Calif. – July 27, 2018 – SiFive, the leading provider of commercial RISC-V processor IP, today welcomed Chipus Microelectronics, a semiconductor company with proven expertise in the development of ultra-low-power (ULP), low-voltage, analog and mixed-signal integrated circuits, to the growing DesignShare ecosystem. Through the partnership, Chipus will provide ULP IP for power management and ULP RF Front-Ends.
SiFive — Jul 10, 2018
SAN MATEO, Calif. – July 10, 2018 – SiFive, the leading provider of commercial RISC-V processor IP, today announced that Terminus Circuits, a provider of interconnect solutions, has joined the expanding DesignShare economy. Through DesignShare, Terminus Circuits will offer complete ASIC solutions for products that are modular and scalable.
SiFive — Jun 25, 2018
San Mateo, Calif. – June 25, 2018 – SiFive, the leading provider of commercial RISC-V processor IP, today announced the availability of its E2 Core IP Series, configurable low-area, low-power microcontroller (MCU) cores designed for use in embedded devices. The E2 Series extends SiFive’s product line with two new standard cores, the E21, which provides mainstream performance for MCUs, sensor fusion, minion cores and smart IoT markets; and the E20, the most power-efficient SiFive standard core designed for microcontrollers, IoT, analog mixed signal and finite state machine applications. Additionally, the company announced enhancements to its existing standard E3 and E5 Core IP Series.
SiFive — May 22, 2018
San Mateo, Calif. – May 22, 2018 – SiFive, the leading provider of commercial RISC-V processor IP, today welcomed Brite Semiconductor, an ASIC service company invested by SMIC, to the growing DesignShare ecosystem.
SiFive — May 17, 2018
Shanghai and San Mateo, Calif. – May 17, 2018 – Andes Technology Corporation, the prominent CPU IP provider, and SiFive Inc., the leading provider of ASIC design service and RISC-V CPU Core IP, have announced they are joining forces to jointly promote RISC-V. The two companies will each contribute their unique expertise in CPU development and support to expand the ecosystem for the RISC-V instruction set architecture (ISA) to enable a new era of processor innovation through open standard collaboration.
SiFive — May 15, 2018
SAN MATEO, Calif. – May 15, 2018
SiFive — May 8, 2018
SAN MATEO, Calif. – May 8, 2018 – SiFive, the leading provider of commercial RISC-V processor IP, today announced that Intel Capital participated in its recent Series C funding round. The investment was revealed at the Intel Capital Global Summit, at which SiFive CEO Naveed Sherwani pushed for the democratization of the semiconductor industry.
SiFive — May 8, 2018
SAN MATEO, Calif. – May 8, 2018 – SiFive, the leading provider of commercial RISC-V processor IP, today opened the call for partnership applications for the Democratizing Ideas partnership initiative, which aims to support new, innovative ideas from academia, research institutions, students and the open source community based on the company’s Freedom Unleashed or Freedom Everywhere platforms. Announced at the RISC-V Workshop in Barcelona, the initiative is designed to further the company’s mission to democratize access to custom silicon to anyone who wants it.
SiFive — May 2, 2018
SAN MATEO, Calif. – May 2, 2018 –
SiFive — Apr 12, 2018
SAN MATEO, Calif. – April 12, 2018 – SiFive, the leading provider of commercial RISC-V processor IP, today announced that Dover Microsystems, a cybersecurity solutions provider, is the latest vendor to join the DesignShare ecosystem.
SiFive — Apr 9, 2018
SAN MATEO – April 9, 2018
Data Center Knowledge — Apr 7, 2018
This week saw another indication that open source hardware is ready to seriously vie for a slice of the enterprise IT pie. On Monday the major company behind the open source RISC-V processor, SiFive, reported it had raised $50.6 million in a Series C funding round, bringing total funding to $64.1 million.
Electronic Design — Apr 5, 2018
The RISC-V architecture is making an impression. That was reflected Monday in the announcement of $50.6 million raised by SiFive, a semiconductor startup that has been leveraging the free and open source architecture to reduce the cost and manpower required for chip development.
SiFive — Apr 2, 2018
SAN FRANCISCO – April 2, 2018 – SiFive, the leading provider of commercial RISC-V processor IP, today announced it raised $50.6 million in a Series C round led by existing investors Sutter Hill Ventures, Spark Capital and Osage University Partners alongside new investor Chengwei Capital, and strategic investors including Huami, SK Telecom and Western Digital and other companies that are among the most respected and iconic companies in the industry. This Series C round brings the total investment in SiFive to $64.1 million. Additionally, the company also announced it has signed a multi-year license to its Freedom Platform with Western Digital, which has pledged to produce 1 billion RISC-V cores.
VentureBeat — Apr 2, 2018
SiFive has raised $50.6 million in a third round of funding to further its ambition to create a new licensing model for the semiconductor industry. San Francisco-based SiFive wants to democratize access to custom silicon chip designs. The company’s founders invented RISC-V, a free and open instruction set architecture for modern microprocessors. SiFive is taking that architecture and making it easy to design the custom variants that companies need.
SiFive — Mar 22, 2018
SAN MATEO, Calif. – March 22, 2018 – SiFive, the leading provider of commercial RISC-V processor IP, today announced that Mobiveil, a provider of Serial Interconnect IP blocks and platforms targeted for Flash Storage, IoT and Communication markets, has joined the growing DesignShare economy.
SiFive — Mar 8, 2018
Corigine adds certified USB IP to SiFive’s Growing DesignShare Economy to Accelerate Adoption of RISC-V
SAN MATEO, Calif. – March 8, 2018 – SiFive, the leading provider of commercial RISC-V processor IP, today announced the addition of Corigine, a fabless semiconductor and IP company, to the DesignShare economy.
Sensors Online — Feb 27, 2018
By now, you’ve likely heard someone tell you: Moore’s Law is dead. To be sure, it is worthwhile to point out that the design aspect of Moore’s Law is – in most circumstances – very much alive. There are still techniques to be discovered to make the transistors smaller, for them to work faster, and to still put more of them in the same footprint. Rather, it is the economics behind Moore’s Law that has clearly reached its endpoint. Chips might continue to get smaller and faster. But if the economics mean that almost no one can afford to buy them, where exactly are we headed?
SiFive — Feb 26, 2018
SAN MATEO, Calif. – Feb. 26, 2018
Design News — Feb 15, 2018
Only months after debuting the Freedom U540, the world's first Linux-compatible processor based on the open-source RISC-V chip architecture, RISC-V chipmaker SiFive has surprised the open-source community again by unveiling a full development board built around the ISA.
SiFive — Feb 14, 2018
SAN MATEO, Calif. – Feb. 14, 2018 – SiFive, the leading provider of commercial RISC-V processor IP, continues to grow its executive staff with the appointment of Shiva Natarajan as chief financial officer. Natarajan joins SiFive with more than two decades of financial management, accounting and strategic planning experience in both public and private technology companies.
Data Center Knowledge — Feb 13, 2018
While software is eating the world, open source hardware might soon be eating the data center. Definitely not tomorrow or next month, and probably not even next year, but sooner than you think, there might be as much open source hardware as the old-fashioned proprietary kind running data centers. Need proof? Take a look at RISC-V, an open processor architecture.
SiFive — Feb 7, 2018
SAN MATEO, Calif. – Feb. 7, 2018 – SiFive, the leading provider of commercial RISC-V processor IP, launched the industry’s first Linux-capable RISC-V based processor SoC. The company demonstrated the first real-world use of the HiFive Unleashed board featuring the Freedom U540 SoC, based on its U54-MC Core IP, at the FOSDEM open source developer conference on Saturday.
Tech Republic — Feb 5, 2018
For low-power and embedded purposes RISC-V, an ISA developed principally by researchers at UC Berkeley with significant outside contributions, is gaining popularity. While early RISC-V devices have been intended for embedded applications and IoT devices, SiFive has released the first RISC-V SoC (Freedom U540) and SBC (Hi-Five Unleashed) which are powerful enough to run Linux distributions.
FOSDEM 2018 — Feb 3, 2018
Interview with Palmer Dabbelt: Igniting the Open Hardware Ecosystem with RISC-V. SiFive's Freedom U500 is the World's First Linux-capable Open Source SoC Platform
Palmer Dabbelt will give a talk about Igniting the Open Hardware Ecosystem with RISC-V. SiFive's Freedom U500 is the World's First Linux-capable Open Source SoC Platform at FOSDEM 2018.
SiFive — Jan 30, 2018
SAN MATEO, Calif. – Jan. 30, 2018 – SiFive, the leading provider of commercial RISC-V processor IP, today announced Shafy Eltoukhy as vice president of operations. Eltoukhy, a veteran of Microsemi and Intel, will lead SiFive’s DesignShare activities and ensure the smooth rollout of new Core IP, SoCs and services.
SiFive — Jan 22, 2018
SAN MATEO, Calif. – Jan. 22, 2018 – SiFive, the leading provider of commercial RISC-V processor IP, today announced the appointment of Sunil Shenoy as vice president of hardware engineering. The news follows SiFive’s momentous expansion last quarter with its strategic partnerships, launch of the first Linux-capable RISC-V core and growth of the DesignShare program.
EE Journal — Jan 16, 2018
“Our vision is to enable two guys in a garage to build a custom chip.” Thus spake Jack Kang, Vice President of SiFive, the 40-person startup making RISC-V chips. SiFive isn’t just another company pulling the RISC-V bandwagon. They’re trying to change the way we create SoCs. The au courant open-source processor design is just a means to that end.
Microsemi — Dec 6, 2017
SiFive Joins Microsemi's New Mi-V Ecosystem to Accelerate Adoption of RISC-V Open Instruction Set Architecture
Microsemi Corporation (Nasdaq: MSCC), a leading provider of semiconductor solutions differentiated by power, security, reliability and performance, today announced SiFive, the first fabless provider of customized, open-source-enabled semiconductors, has joined Microsemi's new Mi-V™ RISC-V ecosystem, further building out the growing ecosystem and expanding the number of RISC-V designs users can consider. Microsemi will leverage its strategic relationship with SiFive and other ecosystem participants to increase adoption of RISC-V open instruction set architecture (ISA) central processing units (CPUs) and maximize their leadership positions with this expanding design technology.
SiFive — Dec 5, 2017
SAN JOSE, Calif. – Nov. 28, 2017 – SiFive, the first fabless provider of customized, open-source-enabled semiconductors, today announced that Think Silicon, a leader in developing ultra-low power graphics IP technology, has joined the growing DesignShare economy. Through DesignShare, Think Silicon will make its complementary NEMA®|GPU and NEMA®|dc IP available for SiFive’s Freedom SoCs Platform at reduced upfront investment from customers.
Forbes — Dec 5, 2017
Western Digital is known for its storage products. What many do not realize is that the company ships over 1 billion processor cores within its products each year and is moving toward 2 billion per year. At the workshop, Western Digital CTO Martin Fink announced that over the next few years those billion plus processors will be transitioned over to RISC-V.
SiFive — Nov 28, 2017
SiFive and Microsemi Expand Relationship with Strategic Roadmap Alignment and a Linux-Capable, RISC-V Development Board
SAN JOSE, Calif. – Nov. 28, 2017 – SiFive, the first fabless provider of customized, open-source-enabled semiconductors, and Microsemi Corporation (Nasdaq: MSCC), a leading provider of semiconductor solutions differentiated by power, security, reliability and performance, at the 7th RISC-V Workshop today announced the companies have formed a strategic relationship to meet the growing interest and demand in the RISC-V instruction set architecture. The companies have previously collaborated to provide RISC-V soft CPU cores for Microsemi’s PolarFire® FPGAs, IGLOO™2 FPGAs, SmartFusion™2 system-on-chip (SoC) FPGAs and RTG4™ FPGAs, currently available as part of the Microsemi Mi-V RISC-V ecosystem.
SiFive — Nov 28, 2017
SAN MATEO, Calif. – Nov. 28, 2017 – At the 7th RISC-V Workshop today, SiFive, the first fabless provider of customized, open-source-enabled semiconductors, announced a number of new partnerships and products that exemplify the company’s rapid growth over the past year. These announcements provide further proof of SiFive’s leadership in aligning with industry leaders to spur innovation in the plateauing semiconductor industry as well as the company’s ability to meet increased demand for open access to custom silicon. The adoption of SiFive’s RISC-V Core IP continues to grow, with more than 150 evaluation licenses in progress.
SiFive — Nov 28, 2017
SiFive Joins FDXcelerator™ Program to Bring RISC-V Core IP to GLOBALFOUNDRIES’ 22FDX® Process Technology
SAN MATEO, Calif. – Nov. 28, 2017 – SiFive announced today that it has joined GLOBALFOUNDRIES’ FDXcelerator™ Partner Program, and will be making RISC-V CPU IP including SiFive’s E31 and E51 RISC-V cores available on GF’s 22FDX® process technology. Based on the open source RISC-V ISA, the SiFive E31 offers embedded chip designers new capabilities in high performance within strict area and power requirements, and the SiFive E51 offers a full 64-bit performance at 32-bit price, power and area.
SiFive — Nov 14, 2017
SAN MATEO, Calif. – Nov. 14, 2017 – SiFive, the first fabless provider of customized, open-source-enabled semiconductors, today announced that Analog Bits, the industry’s leading provider of low-power mixed-signal IP (Intellectual Property) solutions, has joined the growing DesignShare economy. Analog Bits will provide precision clocking macros such as PLLs and SERDES IP available for the SiFive Freedom platforms through the DesignShare initiative.
SiFive — Nov 8, 2017
SAN MATEO, Calif. – Nov. 8, 2017 – SiFive, the first fabless provider of customized, open-source-enabled semiconductors, has once again made the shortlist for two UBM Annual Creativity in Electronics (ACE) Awards. Honored this year were the developers of the HiFive1 for "Design Team of the Year," and Jack Kang, SiFive vice president of product and business development as one of the finalists for "Executive of the Year."
SiFive — Nov 7, 2017
SiFive and eMemory Bring Embedded Memory to the DesignShare Economy to Accelerate Development of RISC-V Silicon
SAN MATEO, Calif. – Nov. 7, 2017 – SiFive, the first fabless provider of customized, open-source-enabled semiconductors, today announced the addition of eMemory, the IP provider of logic-based, non-volatile memory (Logic NVM), to the DesignShare economy. eMemory will make its embedded NVM silicon IP technology available for the SiFive RISC-V based Freedom platform as part of the DesignShare initiative.
SemiWiki — Nov 7, 2017
One of the barriers to silicon success has always been design costs, especially if you are an emerging company or targeting an emerging market such as IoT. Today design start costs are dominated by IP which is paid at the start of the project and that is after costly IP evaluations and other IP verification and integration challenges. Given that, reducing design costs and enabling design starts has always been a major industry focus starting with the fabless semiconductor transformation that began 30 years ago, which brings us to the DesignShare announcement made by SiFive and Flex Logix last week.
SemiAccurate — Nov 1, 2017
SiFive and FlexLogix have teamed up to offer embedded FPGAs in the DesignShare development program. This is the third IP vendor that SemiAccurate knows of to join that program and it is an interesting idea. SiFive’s DesignShare program is unique in it’s aim to lower the barriers of entry for companies interested in making silicon.
SiFive — Oct 31, 2017
SAN MATEO AND MOUNTAIN VIEW, Calif. – Oct. 31, 2017 – SiFive, the first fabless provider of customized, open-source-enabled semiconductors, and Flex Logix™, a leader in embedded FPGA IP and software, today announced they will partner to make Flex Logix EFLX® embedded FPGA available for the SiFive Freedom Platform as part of the DesignShare program. The availability of Flex Logix IP through DesignShare eases time to market and removes traditional barriers to entry that have blocked smaller companies from developing custom silicon.
SiFive — Oct 24, 2017
HÖHENKIRCHEN-SIEGERTSBRUNN, Germany, and SAN MATEO, Calif. – Oct. 24, 2017 – Lauterbach, the leading manufacturer of microprocessor development tools, and SiFive, the first fabless provider of customized, open-source-enabled semiconductors, today announced the availability of Lauterbach’s TRACE32 toolset to provide debug capabilities for SiFive’s E31 and E51 RISC-V Core IP, based on the free and open RISC-V ISA. Lauterbach support for SiFive cores is the latest addition to the growing ecosystem of industry-leading development tools to become available for RISC-V based silicon.
eeNews Europe — Oct 9, 2017
The Coreplex U54-MC contains four U54 CPUs and a single E51 CPU and is the first Coreplex processor core to offer multicore support and support for cache coherence. The U54 cores support the RV64GC ISA with a five-stage, in-order pipeline ALU. The 64bit E51 CPU serves as a management core and is fully coherent with the U54 cores. The U54-MC Coreplex is ideal for applications which need full operating system support such as AI, machine learning, networking, gateways, and smart IoT devices.
Electronics Weekly — Oct 9, 2017
RISC-V is a free and open instruction set architecture [ISA] designed to enable chips across the full spectrum of computing devices, from embedded devices to the data centre,” said the firm. “The release of the U54-MC Coreplex marks the architecture’s expansion into the application processor space – opening entirely new use cases for RISC-V. It is ideal for applications which need full operating system support such as AI, machine learning, networking, gateways and smart IoT devices.
Fossbytes — Oct 8, 2017
Last year, Silicon Valley Startup SiFive released the first open source SoC (system on a chip), which was named Freeform Everywhere 310. Now, going one step ahead from the embedded systems, the company has released U54-MC Coreplex IP, which is the world’s first RISC-V based 64-bit quad-core CPU that supports fully featured operating systems like Linux.
Fudzilla — Oct 8, 2017
Linux fanboys tend to announce a lot of “year of” events. There is the year of the desktop which appears to be every year and still never happens and now there is the year of RISC V Linux processor. SiFive has declared that 2018 will be the year of RISC V Linux processor, so mark your penguin diaries accordingly. In the UK there will be all sorts of events planned, including guess the weight of Linus Torvalds competitions, there will be penguin tossing at Slough.
Mention — Oct 5, 2017
SiFive launched U54-MC Coreplex IP, a RISC-V based, 64-bit, quadcore real-time capable application processor with support for full featured operating systems such as Linux. The cores utilize a five-stage in-order pipeline, support the RV64GC ISA and cache coherence. It is targeted at AI, machine learning, networking, gateways and smart IoT devices.
Design News — Oct 5, 2017
When it released its first open-source system on a chip, the Freeform Everywhere 310, last year, Silicon Valley startup SiFive was aiming to push the RISC-V ("risk five") architecture to transform the hardware industry in the way that Linux transformed the software industry. Now the company has delivered further on that promise with the release of the U54-MC Coreplex , the first RISC-V-based chip that supports Linux, Unix, and FreeBSD.
SiFive — Oct 4, 2017
SAN MATEO, Calif. – Oct. 4, 2017 – SiFive, the first fabless provider of customized, open-source-enabled semiconductors, today announced the availability of U54-MC Coreplex IP, the industry’s first RISC-V based, 64-bit, quadcore real-time capable application processor with support for full featured operating systems such as Linux. The free and open RISC-V architecture, which is supported by an ecosystem comprising more than 70 companies, has seen tremendous growth in the embedded segment. The release of the U54-MC Coreplex marks the architecture’s expansion into the application processor space – opening entirely new use cases for RISC-V.
LinuxGizmos.com — Oct 3, 2017
SiFive has taped out the first multi-core RISC-V based processor design, and the first to run Linux, featuring 4x 1.5GHz "U54" cores and a management core. SiFive announced "early access" availability of the 64-bit, quad-core U54-MC Coreplex – the first Linux-ready application processor built around the open source RISC-V architecture.
Electronic Design — Oct 3, 2017
The RISC-V universe just got a little bigger with SiFive’s 1.5 GHz U54-MC Coreplex (Fig. 1). The four U54 cores implement RV64GC that includes support for hardware multiple and divide, atomic instructions, 16-bit compressed instructions, and single and double precision floating point support.
EE Times — Oct 3, 2017
SiFive has taped out and started licensing its U54-MC Coreplex, its first RISC-V IP designed to run Linux. The design lags the performance of a comparable ARM Cortex-A53 but shows progress creating a commercial market for the open-source instruction set architecture.
Hackaday — Oct 3, 2017
At the Linley Processor Conference today, SiFive, the semiconductor company building chips around the Open RISC-V instruction set has announced the availability of a quadcore processor that runs Linux. We’ve seen RISC-V implementations before, and SiFive has already released silicon-based on the RISC-V ISA. These implementations are rather small, though, and this is the first implementation designed for more than simple embedded devices.
SiFive — Sep 26, 2017
SAN MATEO, Calif. – Sept. 26, 2017 – SiFive, the first fabless provider of customized, open-source-enabled semiconductors, today announced it has joined the TSMC (NYSE: TSM) IP Alliance Program, part of the TSMC Open Innovation Platform®, which accelerates innovation in the semiconductor design community. As an alliance member, SiFive’s RISC-V based Coreplex IP are made available to its customers to reduce time-to-market, increase return on investment and reduce waste in the manufacturing process.
SiFive — Sep 19, 2017
HILDEN, Germany, and SAN MATEO, Calif. – Sept. 19, 2017 – SEGGER Microcontroller, a leading supplier of software, hardware and development tools for embedded systems, and SiFive, the first fabless provider of customized, open-source-enabled semiconductors, today announced the availability of SEGGER J-Link support for SiFive Coreplex IP, based on the RISC-V architecture. The growing interest in Coreplex IP is increasingly prompting vendors like SEGGER to make its industry leading tools available as part of the RISC-V ecosystem.
SiFive — Sep 12, 2017
MEDIA ALERT: SiFive to Exhibit at the TSMC 2017 Open Innovation Platform Ecosystem Forum Pavilion Sept. 13
SANTA CLARA, Calif. – 9/12/2017
SiFive — Sep 7, 2017
SAN MATEO, Calif. – Sept. 7, 2017 – SiFive, the first fabless provider of customized, open-source-enabled semiconductors, today announced that UltraSoC will provide debug and trace technology for the SiFive Freedom platform, based on the RISC-V open source processor specification as part of the DesignShare initiative. UltraSoC’s embedded analytics IP will be available through the recently announced SiFive DesignShare ecosystem that gives any company, inventor or maker the ability to harness the power of custom silicon. UltraSoC’s debug and trace functionality will enable users of the Freedom platform to access a wide variety of tools and interfaces to use in their developments.
SiFive — Aug 21, 2017
SAN MATEO, Calif. – August 21, 2017 – SiFive, the first fabless provider of customized, open-source-enabled semiconductors, today announced it will partner with Rambus, (NASDAQ: RMBS), a leader in digital security, semiconductor and IP products and services, to make Rambus cryptography technology available for the SiFive Freedom platforms. To speed time to market and remove the barriers that traditionally have blocked smaller players from developing custom silicon, leading companies in the semiconductor ecosystem have developed a new DesignShare concept, which offers IP at a reduced cost.
SiFive — Aug 15, 2017
SAN FRANCISCO – August 15, 2017 – SiFive, the first fabless provider of customized, open-source-enabled semiconductors, today announced that industry veteran Naveed Sherwani has joined the company as CEO to lead it through its next phase of growth. Stefan Dyckerhoff, who had held the top spot at the company since its inception, will remain a member of the SiFive board of directors.
CPU Shack Museum — Jun 4, 2017
It is out of this that SiFive began. SiFive was founded by the creators of the first commercially successful open RISC architecture, known as RISC-V. RISC-V was developed at Berkeley, fittingly, in 2010 and was designed to be a truly useful, general purpose RISC processor, easy to design with, easy to code for, and with enough features to be commercially useful, not limited to the classroom. It is called the RISC-V because it is the fifth RISC design developed at Berkeley, RISC I and RISC II being designed in 1981, followed by SOAR (Smalltalk On A RISC) in 1984 and SPUR (Symbolic Processing Using RISC) in 1988. RISC-V has already proved to be a success, it is licensed freely, and in a way (BSD license) that allows products that use it to be either open, or proprietary. One of the more well known users is Nvidia, which announced they are replacing their own proprietary FALCON processors (used in their GPUs and Tegra processors) with RISC-V. Samsung, Qualcomm, and others are already using RISC-V. These cores are often so deeply embedded that their existence goes without mention, but they are there, working in the background to make whatever tech needs to work, work.
SiFive — May 19, 2017
SAN FRANCISCO – May 19, 2017 – SiFive, the first fabless provider of customized, open-source-enabled RISC-V semiconductors, today announced the release of the Arduino Cinque, the first RISC-V-based development board for the popular open-source hardware platform. Today’s announcement marks the latest development in SiFive’s work to democratize access to custom silicon.
EEFocus — May 17, 2017
开源是当今最热门的话题之一，也是未来的趋势，就像1998年时任微软CEO的鲍尔默痛斥Linux是癌症，而如今的CEO 却称“Microsoft love Linux”，因为开源“以人为本”，然而开源的商业化是一条必行却又难行的路。
如今的处理器、SoC基本被x86与ARM 这样封闭的指令集架构（ISA）所统治。所以谁能成为微处理器中的 Linux ，成为业界探讨与期待的事情。而目前RISC-V成为最受关注的对象。
EEWorld — May 9, 2017
由免费开源RISC-V指令集架构发明者创建的企业SiFive于今日在上海参加RISC-V基金会主办，NVIDIA和上海交通大学联合承办的第六届RISC-V技术研讨会，首次在中国与到会的200余名国内外顶尖学者和企业共同分享RISC-V指令集和其相关前景应用。作为首家基于免费开源RISC-V指令集架构的定制半导体公司，SiFive还在研讨会上分享了公司的最新进展 – SiFive即将推出目前访问RISC-V内核最快捷也最简单的方式 – Coreplex IP产品。随着RISC-V生态系统的快速发展，SiFive Coreplex IP设计已成为RISC-V内核的实际领导者，拥有比任何其他RISC-V架构厂商更多的客户群、硅产品和开发板。另外，SiFive还提供了简易的“调研-评估-购买”(Study – Evaluate – Buy)的采购流程，帮助工程师们迅速获得实用的Coreplex IP RTL源代码。
SiFive — May 8, 2017
SAN FRANCISCO – May 8, 2017 – SiFive, the first fabless provider of customized, open-source-enabled semiconductors, today announced it has raised $8.5 million in a Series B round led by Spark Capital with participation from Osage University Partners and existing investor Sutter Hill Ventures. This Series B round brings the total investment in SiFive to $13.5 million. The funding comes as SiFive experiences a growing demand for RISC-V IP and increased interest in custom silicon.
Electronic Design — May 8, 2017
Last year, SiFive went fishing for engineers willing to test out chips based on the RISC-V instruction set, releasing a basic core called Rocket that anyone could download and modify. But now the company, whose founders invented RISC-V, is using richer bait for more ambitious customers.
Last week, SiFive started selling two embedded cores under the brand Coreplex, with applications ranging from wearables to servers. The company is aiming to lower the bar for engineers trained on Intel or ARM instruction sets to take RISC-V for a spin, when few companies appear to be turned off by the inflexibility or licensing fees of rival technology.
谁是目标 (via 百家号) — May 8, 2017
SiliconAngle — May 7, 2017
SiFive Inc. wants to give businesses access to custom-designed silicon chips at an affordable price, and today the San Francisco-based semiconductor startup announced that ii has closed an $8.5 million Series B funding round.
The round was led by Spark Capital, and it also included participation from Osage University Partners and existing investor Sutter Hill Ventures. SiFive’s Series B round brings the startup’s total investments to date to $13.5 million.
Electronics Weekly — May 7, 2017
SiFive, the company set up to provide customised silicon using RISC-V cores, has raised $8.5 million in a Series B round.
This Series B round brings the total investment in SiFive to $13.5 million.
In its first six months of availability, more than 1,000 HiFive1 software development boards have been purchased and delivered to developers in over 40 countries.
LinuxGizmos — May 7, 2017
This week, SiFive announced a new “study-evaluate-buy” purchase process, that lets developers “get their hands on Coreplex IP RTL in a matter of minutes.” The immediately downloadable E31 Coreplex and E51 Coreplex IP RTL is described as “fully synthesizable and verified soft IP implementations that scale across multiple design nodes, making them ideal for your next SoC design.” On its Coreplex IP evaluation web page, SiFive describes the IP evaluation and purchase as being fast, NDA-free, and with a pricing model that is not based on royalties.
VentureBeat — May 7, 2017
SiFive is pioneering a new model in the semiconductor business and to do so has raised $8.5 million in a second round of funding, led by Spark Capital.
San Francisco-based SiFive is on a mission to democratize access to custom silicon chip designs. The company’s founders invented RISC-V, a free and open instruction set architecture for modern microprocessors. It consists of all of the software instructions needed to program a microprocessor based on the RISC-V architecture. And SiFive is taking that architecture and making it easy to design the custom variants that companies need.
SiFive — May 4, 2017
SiFive Launches CPU IP Industry into the Cloud with New RISC-V Cores and an Easy Online Business Model
SAN FRANCISCO – May 4, 2017 – SiFive, the company founded by the inventors of the free and open RISC-V instruction set architecture (ISA), today announced the immediate availability of its Coreplex IP, the fastest and easiest way to license RISC-V cores. With the rapid growth in the RISC-V ecosystem, SiFive Coreplex IP designs have become the de facto leader for RISC-V cores, with more public customers, silicon and development boards than any other RISC-V vendor. SiFive’s hassle-free “study-evaluate-buy” purchase process means that designers can get their hands on Coreplex IP RTL in a matter of minutes.
CIO — May 3, 2017
A startup called SiFive is the first to make a business out of the RISC-V architecture. The company is also the first to convert the RISC-V instruction set architecture into actual silicon. The company on Thursday announced it has created two new chip designs that can be licensed.
Make — May 2, 2017
There has been an upswell of interest in custom, open hardware among makers, in which community-developed and shared designs abound. The availability of low-cost development boards such as Arduino and Raspberry Pi, together with open source software, has made it easier to get started with making innovative, new hardware designs.
Hackaday — Apr 13, 2017
Come hang out for 30 or so minutes and talk to Jack Kang, VP of Product and Business Development at SiFive. Join this chat to learn about RISC-V, the free and open Instruction Set. Ask questions about what it means to have open-source chips, and how SiFive plans to help everybody—from the smallest company, inventor, and maker, get access to custom silicon.
Sidense — Mar 8, 2017
SiFive is the first fabless provider of customized, open-source-enabled semiconductors. The RISC-V ISA has been central to our vision of enabling a whole new range of applications for everyone. In November 2016, we announced the availability of the Freedom Everywhere 310 (FE310) SoC, the industry's first commercially available chip based on RISC-V. Bringing the first commercially available SoC based on the RISC-V ISA is a huge milestone for the open-source hardware community.
Cadence — Jan 22, 2017
The SiFive business model is that lots of people are locked out of silicon. SiFive can do custom design and deliver chips. "We believe we can do it cheaper, quicker and more predictably than anyone else.” They have also been getting lots of calls to help with designs. Growing the RISC-V ecosystem is a big opportunity.
The traditional semiconductor business models take a lot of resources, so you have to pick the winners. But there aren't any $1B sockets anymore, so you can't easily pick the winners. The market is fragmented. SiFive wants to give everyone a chance. In a bit more detail, they will do a customer microcontroller platform and deliver 100 or so chips for under $100K.
Hackaday — Jan 4, 2017
2016 was a great year for Open Hardware. The Open Source Hardware Association released their certification program, and late in the year, a few silicon wizards met in Mountain View to show off the latest happenings in the RISC-V instruction set architecture.
We’ve seen a lot of RISC-V stuff in recent months, from OnChip’s Open-V, and now the HiFive 1 from SiFive. The folks at SiFive offered to give me a look at the HiFive 1, so here it is, the first hands-on with the first Open Hardware microcontroller.
InfoWorld — Jan 4, 2017
In an interview, Jack Kang, VP of Product and Business Development at SiFive, discusses the FE310 chip, which will allow IoT vendors to build their own custom SoC on top of it
SiFive is a relatively new fabless chip manufacturing startup that is developing fully open source chips. Its new FE310 chip is its first chip (and apparently the first open source chip) targeted at IoT devices.
SemiEngineering — Jan 3, 2017
One of the lessons learned years ago in the open-source Linux world is that free software isn’t always good enough. Consequently, being able to add commercial value around freeware can turn into a lucrative business.
Enter SiFive, a startup that has been building customized platforms based on the RISC-V CPU. Started by the creators of the RISC V instruction set architecture (ISA), the company’s stated goal is to shake up the economics of the chip industry.
Design News — Dec 15, 2016
Moore's Law is dead...just not in the way everyone thinks. Technological advances keep allowing chips to scale, but the economics are another story – particularly for smaller companies that can't afford chips in the volumes that the big chipmakers would like from their customers.
The solution, according to San Francisco-based startup, SiFive, is open-source hardware, specifically an architecture developed by the company's founders called RISC-V (pronounced “risk-five”). Done right SiFive, which was awarded Startup of the Year at the 2016 Creativity in Electronics (ACE) Awards, believes that RISC-V will do for the hardware industry what Linux has done for software.
Design News — Dec 7, 2016
The best and brightest were on display last night as UBM announced the 2016 Annual Creativity in Electronics (ACE) Awards winners during a ceremony held in conjunction with ESC Silicon Valley and BIOMEDevice San Jose. The awards, presented in partnership with EETimes and EDN, showcase the best in today’s electronics industry, including the hottest new products, start-ups, design teams, executives, and more.
All About Circuits — Dec 6, 2016
The RISC-V footprint is expanding with the commercial availability of open-source chips and related development boards from silicon startups like SiFive and OnChip.
The open-source hardware movement's journey from academia to the commercial realm is finally gaining some momentum. This is in large part thanks to free RISC-V instruction set architecture (ISA), which was developed at the University of California, Berkeley a few years ago.
Cadence — Dec 5, 2016
One of the announcements at the recent RISC-V workshop was by SiFive. This is the company started by the creators of the RISC-V instruction set architecture (Krste, Andrew, and Yunsup) to commercialize silicon implementations.
Four months ago, at the previous RISC-V workshop, they announced FPGA implementations of the two flavors, Freedom Everywhere (16-bit microcontroller) and Freedom Unleashed (64-bit multi-core, high performance). They also announced that silicon would be coming "soon."
Well, it is now "soon."
Electronic Design — Dec 4, 2016
In a nutshell, RISC-V is an instruction set architecture (ISA) that scales from 16-bit to 128-bit register platforms. The E310 is targets the Cortex-M0 space, but it can run at 320 MHz while sipping power—making it an interesting solution for the Internet of Things (IoT). The chip is available on the HiFive1 board ... that has an Arduino form factor.
SiFive — Nov 29, 2016
SAN FRANCISCO – Nov. 29, 2016 – SiFive, the first fabless provider of customized, open-source-enabled semiconductors, today announced the availability of its Freedom Everywhere 310 (FE310) system on a chip (SoC), the industry’s first commercially available SoC based on the free and open RISC-V instruction set architecture, along with the corresponding low-cost HiFive1 software development board. As part of this availability, SiFive also has contributed the register-transfer level (RTL) code for FE310 to the open-source community, which the company revealed today at the 5th RISC-V Workshop in Mountain View, Calif.
VentureBeat — Nov 28, 2016
SiFive wants to democratize the custom chip business, and so today it is launching the industry’s first open-source RISC-V system-on-chip processor. The Freedom Everywhere 310 SoC and HiFive1 development board will enable a wide variety of system architects, embedded designers, and Internet of Things providers — people who normally have to rely on chip engineers for the detailed engineering work — to create their own products.
Hackaday — Nov 28, 2016
The RISC-V ISA has seen an uptick in popularity as of late — almost as if there’s a conference going on right now — thanks to the fact that this instruction set is big-O Open. This openness allows anyone to build their own software and hardware. Of course, getting your hands on a RISC-V chip has until now, been a bit difficult. You could always go over to opencores, grab some VHDL, and run a RISC-V chip on an FPGA. Last week, OnChip released the RISC-V Open-V in real, tangible silicon.
EE Times — Nov 28, 2016
Startup SiFive started selling today a $59 Arduino board running its first RISC-V-based SoC and made open source RTL code available online for the chip. The news marks a milestone for a still nascent open source hardware movement.
Open source cores have been available previously but they tended to be academic efforts or lacked broad commercial support. The HiFive board is intended to drive demand for custom SoCs SiFive will design and comes with a growing pool of open source Linux variants and tools fed by an expanding foundation that maintains the RISC-V instruction set.
PR Newswire — Nov 15, 2016
Microsemi is First FPGA Provider to Offer Open Architecture RISC‑V IP Core and Comprehensive Software Solution for Embedded Designs
Microsemi's new RV32IM RISC-V core, developed in collaboration with SiFive, enables customers to design with an open instruction set architecture (ISA), enabling complete portability and a more secure processor architecture governed by a permissive BSD license. RISC-V is a new ISA which is now a standard open architecture under the governance of the RISC-V Foundation. RISC-V offers a compelling soft processor solution for Microsemi's low power, reliable, secure FPGAs.
SemiWiki — Oct 2, 2016
Since its formation just last year, SiFive has been riding the RISC-V rocket from purely academic interest to first commercialization. In an exclusive discussion, I talked with CEO Stefan Dyckerhoff and VP of Product and Business Development Jack Kang about their progress so far and what may be coming next.
New Electronics — Sep 26, 2016
In their 2014 technical report for the University of California at Berkeley, Krste Asanovic and Professor David Patterson – who developed the concepts behind the SPARC architecture in the 1980s – argued that, while there are good commercial reasons for processor makers to maintain proprietary instruction sets, there is no good technical reason for users to adopt them. Their proposal was for an instruction set architecture (ISA) offered on a similar basis to open source software that could stimulate an ecosystem similar to that built around Linux.
As their proposal represented the fifth generation of RISC processor design, it was called RISC-V.
Linux Pro Magazine — Sep 20, 2016
As many would-be open hardware manufacturers have discovered, free-licensed computer chips are nearly non-existent. However, SiFive, a recently announced startup in San Francisco, is hoping to change that with its custom chip designs. SiFive has its origins in the RISC-V instruction set architecture (ISA) developed in the Computer Science Division of the Electrical Engineering and Computer Science Department at the University of California, Berkeley.
EE Times — Sep 18, 2016
It has been a year since EE Times produced a version16.1 of the Silicon 60. Over that time while the global economic situation can — at best — be said to have stabilized the semiconductor and electronics industries are on the edge of "great expectations.” There seems no doubt that the Internet of Things will have a revolutionary impact on how people can live their lives, but exactly how that will manifest itself in terms of components, software, platforms, legal and business models, is not yet clear nor is the next big thing.
Xilinx — Sep 7, 2016
Itching to Play With the Open-Source RISC-V Processor? Here Are Three Xilinx-Based Kits to Start With
RISC-V (pronounced “risk five”) is an open, 32/64-bit RISC microprocessor architecture first developed at the Computer Science Division of the EECS Department at the U. of California, Berkeley. Now it’s managed by the RISC-V Foundation. If you are an aficionado of processor architectures and you’re looking to get your feet wet with the RISC-V architecture, SiFive has released three Freedom FPGA Platforms based on Xilinx All Programmable devices that allow you to start working with the RISC-V ISA immediately.
Cadence — Sep 6, 2016
A couple of weeks ago I talked to Krste Asanović and Jack Kang of SiFive. One of their motivations is to bring the cost reduction that goes along with open-source software (and instruction sets!) to the hardware world. There is an increasing move in this direction as companies like Facebook, IBM, and Google put parts of their server infrastructure into the public domain. This is especially important in semiconductors since Moore's law has run into a wall, at least economically, even though we have a couple more process generations coming at us.
Cadence — Sep 1, 2016
A week or so ago I talked to Krste Asanović, who is the UC Berkeley professor who led the project to define RISC-V, chairman of the RISC-V foundation, and in July co-founded a fabless semiconductor company, SiFive, to produce silicon implementations (and IP). I'll talk about SiFive in Breakfast Bytes one day next week. RISC-V has taken off strongly in academic circles due to its unrestricted availability compared to other instruction sets, which are often not really ideal for academic work, and/or come with legal encumbrance.
Pinestream Consulting Group — Aug 15, 2016
SiFive recently unveiled its flagship Freedom family of SoC platforms. Built around the RISC-V ISA invented by the company’s founders at the University of California, Berkeley, the Freedom U500 and Freedom E300 platforms represent a new approach to designing and producing SoCs that redefines traditional silicon business models and reverses prohibitively rising licensing, design and implementation costs.
Electronics Lab — Aug 2, 2016
SiFive, a startup from San Francisco, is trying to democratize the access to the world of SoC designing and manufacturing by giving the ability of customizing silicon to the smallest company, inventor, or maker, and taking “the hard parts of building chips working with 3rd part IP, EDA tools and foundries. SiFive is a fabless semiconductor company building customizable SoCs. SiFive takes benefits from using RISC-V in their SoC design. Some of inventors of the open source ISA RISC-V are behind SiFive.
CIO — Aug 2, 2016
SiFive is a San Francisco-based fabless chip manufacturing startup that is developing the first fully open source chips. The company, which launched earlier this month, announced two chips of their flagship platform: Freedom U500 and Freedom E300, each targeting different audience.
IOT-DEV.net — Jul 25, 2016
As many of you may already know, SiFive is the first company that will make open source ISA Risc-V SoCs. What will be open and what not ? This was main question that people ask. In this video they answered that they will open as much as they can.PCI-E 3 controllers and some other 3-d party stuff will remain closed. They said time to develop some controllers and other 3d party tools and all to be open sourced will take ~ another 2 years of work.
Electronics Products — Jul 21, 2016
SiFive has introduced the Freedom family of open-source SoC-platform intellectual property based on the RISC-V instruction set architecture. The company offers the Freedom U500 and Freedom E300 processing platforms that are a new approach to designing and producing SoCs in that they are based on open-source and extensible architecture with no licensing fees.
Elektor Magazine — Jul 18, 2016
With its customizable, open-source SoCs built on the free and open RISC-V instruction set architecture, SiFive, a San Francisco start-up, is poised to reverse the industry’s rising licensing, design and implementation costs. System designers can use the SiFive Freedom platforms to focus on their own differentiated processor without having the overhead of developing a modern SoC, fabric or software infrastructure.
ModernLife Network — Jul 18, 2016
SiFive, a new Silicon Valley startup, is teaming up with RISC-V Foundation and the infrastructure set to develop open source chip products. Two chips are in development – Freedom Unleashed (designed for machine learning, storage and networking) and Freedom Everywhere (designed for low-power devices in the “Internet of Things” market). SiFive is trying to drive down the cost of chip manufacturing, open the industry up to designers and engineers, and squeeze into an industry that has several barriers of entry.
AnandTech — Jul 17, 2016
SiFive, a company established by researchers who invented the RISC-V instruction set architecture in the University of California Berkeley several years ago, has this week announced two platforms which could be used to design semi-custom SoCs based on RISC-V cores.
Linux Insider — Jul 12, 2016
SiFive on Monday announced its flagship Freedom family of system on a chip platforms. The platforms are based on the free and open source RISC-V instruction set architecture that several of the company's founders created at the University of California at Berkeley. SiFive's Freedom U500 and E300 platforms take a new approach to SoCs, redefining traditional silicon business models and reversing the industry's increasingly high licensing, design and implementation costs.
HPCwire — Jul 12, 2016
Momentum for open source hardware made a significant step this week with the launch of startup SiFive and its open source chip platforms based on the RISC-V instruction set architecture. The founders of the fabless semiconductor company — Krste Asanovic, Andrew Waterman, and Yunsup Lee — invented the free and open RISC-V ISA at the University of California, Berkeley, six years ago.
SiFive — Jul 11, 2016
SAN FRANCISCO – July 11, 2016 – SiFive, the first fabless semiconductor company to build customized, open-source enabled semiconductors, today announced its flagship Freedom family of system on a chip (SoC) platforms. Built around the free and open RISC-V instruction set architecture invented by the company’s founders at the University of California, Berkeley, SiFive’s Freedom U500 and Freedom E300 platforms represent a fundamentally new approach to designing and producing SoCs that redefines traditional silicon business models and reverses the industry’s prohibitively rising licensing, design and implementation costs.
Rambus — Jul 11, 2016
A San Francisco-based startup known as SiFive has announced plans to develop and sell chips based on open-source RISC-V architecture. According to Don Clark of the Wall Street Journal, the tech includes a set of instructions that define the functions of a microprocessor, which can serve as a starting point for designing a chip.
Product Design and Development — Jul 11, 2016
Fabless semiconductor company SiFive has announced a new system on a chip platform that takes the SoC platform into the realm of open-source. The RISC-V instruction set architecture was originally developed by SiFive’s founders at the University of California, Berkeley, and has now been packaged into the Freedom U500 and Freedom E300 platforms.
Linux Magazine — Jul 11, 2016
A San Francisco-based company known as SiFive is trying to bring the open source development model to the chip industry. The company has announced its first Freedom family of system-on-a-chip (SoC) products, including the Freedom U500 and Freedom E300 platforms. SiFive is a fabless semiconductor company, similar to AMD. The company doesn’t fabricate the chip but outsources it to manufacturers.
Journal Dunet (French Publication) — Jul 11, 2016
Un groupe de chercheurs de l'Université de Californie lançait en avril dernier une fondation visant à porter un projet d'architecture de processeur open source (le projet RISC-V). Ces chercheurs passent maintenant à la vitesse supérieure : ils lancent une entreprise, baptisée SiFive, visant à commercialiser leur technologie. SiFive doit développer des puces reposant sur l'architecture open source RISC-V.
IOT-DEV.net — Jul 11, 2016
SiFive will publish specifications for an SoC based high-performance Unix-capable cache-coherent 64-bit multiprocessor U500 and one using a microcontroller core E300 both based on work of the RISC-V Foundation. The U500 platform is the first member of SiFive's Freedom Unleashed family of customizable RISC-VSoCs. Freedom Un-leashed family reduces NRE and time-to-market for customized SoCs in diverse markets such as machine learning, storage and networking.
HackerBoards — Jul 11, 2016
SiFive unveiled the first embedded SoCs based on the open source RISC-V platform: A Linux-ready octa-core Freedom U500 and a FreeRTOS-based Freedom E300. A VC-backed startup closely associated with the RISC-V project announced the first system-on-chip implementations of the open source RISC-V processor platform.
Electronics Weekly — Jul 11, 2016
It has developed customizable, open-source SoCs built on the free and open RISC-V instruction set architecture. “The semiconductor industry is at an important crossroads. Moore’s Law has ended, and the traditional economic model of chip building no longer works,” said Yunsup Lee, co-founder of SiFive and one of the original creators of RISC-V at UC Berkeley.
CNXSoft — Jul 11, 2016
SiFive, a startup founded by the creators of the free and open RISC-V architecture, has announced two open source SoCs with Freedom U500 processor and Freedom E300 micro-controller. Three real-time operating systems, including FreeRTOS, have already been ported to Freedom E300 for embedded micro-controllers, IoT, and wearable markets.
SemiAccurate — Jul 10, 2016
SiFive is unveiling two open source RISC-V based platforms today called the Freedom U500 and E300 Series. SemiAccurate thinks what SiFive is doing has a good chance of changing how the silicon market works.
EE Times — Jul 10, 2016
A startup aims to help a broader set of engineers roll their own silicon using its customizable open-source systems-on-chips. SiFive will publish specifications for an SoC based on an embedded Linux processor core and one using a microcontroller core both based on work of the RISC-V Foundation.
eWEEK — Jul 10, 2016
The open-source RISC-V chip architecture was created to help developers more easily and cheaply customize processors that run their devices, and last year an industry consortium was formed around the technology. Now the inventors of RISC-V want to see if they can build a business based on the architecture.
SemiWiki — Jul 10, 2016
When we talk about open source, free usually comes in the context of “freedom”, not as in “free beer”, and open IP often serves as a base layer of value add for commercialization. The creators of the RISC-V instruction set, now working at startup SiFive, have released specifications for their aptly-named Freedom processor IP cores looking for "enablement of great ideas".
Forbes — Jul 10, 2016
Open source has taken off in the software world. RISC-V maybe has the opportunity to bring open source to the rigid chip industry. Born out of university research, RISC-V is a chip architecture that lets developers freely change and customize chip designs without having to pay for expensive licenses or royalty fees.
Wall Street Journal — Jul 10, 2016
A group of university researchers recently attracted attention by applying principles of open-source software to computer chips. Now they’re turning the concept into a company. A San Francisco-based startup called SiFive on Monday is announcing plans to develop and sell chips based on a technology called RISC-V. The tech includes a set of instructions that define the functions of a microprocessor, which can serve as a starting point for designing a chip.
SemiEngineering — Jun 29, 2016
Open source is getting a second look by the semiconductor industry, driven by the high cost of design at complex nodes along with fragmentation in end markets, which increasingly means that one size or approach no longer fits all.
Cadence Blogs — Jun 16, 2016
I had never heard of RISC-V (pronounced five, not vee) until earlier this year when there was a presentation about it at EDPS in Monterey. I immediately texted the daughter of a friend of mine who is a CS major at Berkeley where it originated and she gave me a bit more background.
Next Platform — May 15, 2016
The running joke is that when a headline begs a question, the answer is, quite simply, “No.” However, when the question is multi-layered, wrought with dependencies that stretch across an entire supply chain, user bases, and device range, and across companies in the throes of their own economic and production uncertainties, a much more nuanced answer is required.
Linley Group — Mar 31, 2016
RISC-V is a new general-purpose instruction-set archi-tecture (ISA) that’s BSD licensed, extensible, and royalty free. It’s clean and modular with a 32-, 64-, or 128-bit inte-ger base and various optional extensions (e.g., floating point). RISC-V is easier to implement than some alterna-tives—minimal RISC-V cores are roughly half the size of equivalent ARM cores—and the ISA has already gathered some support from the semiconductor industry.
Next Platform — Mar 7, 2016
Back in the early 1990s, the common view was that there was little money to be made in the business of open source. As the wave of Linux distributions rolled forth, however, that was quickly disproven, setting the decades-long chain of companies that have secured their footing, funding, and futures on the back of open software.
XDA Developers — Jan 7, 2016