The SiFive 21G3 Release introduces the new SiFive Essential 6-Series range of RISC-V processors for area-focused computing applications

The SiFive Performance P650 processor is expected to be the fastest licensable RISC-V processor IP core in the market, bringing RISC-V into new markets and applications, and will debut to lead partners in Q1 2022.

New SiFive Performance Family of application processors offers best in class performance, area, and efficiency for a wide variety of markets

Configurable SiFive RISC-V AI SoC Development Platform is built on 14nm Samsung process technology to accelerate custom Machine Learning solutions

SiFive Intelligence IP integral component of future Tenstorrent AI architectures

SiFive to License Industry-Leading RISC-V Core IP Portfolio to Renesas

Leading provider of RISC-V processor IP to share details of new initiatives for AI-enabled markets

Licensing agreement provides access to a broad portfolio of IP from the inventors of RISC-V

New Edge AI processor accelerates key workloads while offering flexibility for changing AI needs

RISC-V Leader Recognized by Global Semiconductor Alliance For Developing RISC-V-based IP Solutions to Solve Next-Generation Computing Challenges

Featuring the voice and star of the Thirteenth Doctor, Jodie Whittaker, the HiFive Inventor is a powerful Internet of Things programmable computer designed to teach kids to code

SiFive E2 Core IP Flexibility and Power-efficient Performance Enable Bouffalo Product differentiation

Industry Veteran To Lead Mission To Develop RISC-V-based Platforms to Solve Next-Generation Computing Challenges

SiFive Founders and Inventors of RISC-V will deep dive new vector-based architecture, and debut new SoC for professional developers of RISC-V applications

The new API adds critical capabilities to widely used compilers, GCC & LLVM

Innovium TERALYNX® products integrate SiFive RISC-V processor cores to increase lead in breakthrough switch silicon for Cloud and Edge data center networks

OpenFive is a solution-centric and processor agnostic custom silicon business unit dedicated to building optimized domain-specific SoCs

Demand for Domain-Specific Architecture Drives Continued Investment in Processor Innovation

The SiFive 20G1 release delivers up to 2.8x more performance(1); up to 25% lower power(2); and up to 11% smaller area(3), for designing next-generation SoCs

SiFive Core IP Enables Market-Leading Applications for Military and Aerospace Markets

The idea-to-silicon company pledges free SiFive E21 Standard Core for use in healthcare products

Tech industry veteran to lead financial operations and drive SiFive growth

The idea-to-silicon company will be hosting two sessions during the online conference, in addition to serving as a Platinum sponsor.

The portfolio enables users to access, observe, and control processor development in real-time, accelerating silicon time-to-market

Distinguished Silicon Valley software engineer to bring increased customization and implementation tooling to SiFive SoC design methodology

Joint silicon development through SiFive’s DesignShare Program combines IP and design strengths of both companies to develop Edge AI SoCs for a range of high-volume end markets including smart home, automotive, robotics, security, augmented reality, industrial and IoT

SiFive to deepen AI portfolio with strategic new disclosures at CES 2020, unleashing semiconductor product roadmaps for consumer and commercial SoCs

Scalable Processor Core IP Running on Low Power, Small Form Factor FPGAs Could Power Millions of Smart Devices at the Edge

SiFive’s new hire brings unparalleled experience in vectorization

New SiFive Apex cores for mission-critical markets and SiFive Intelligence cores for vector processing workloads create a comprehensive IP portfolio for high-growth markets

RISC-V leader honored for second consecutive year for its hypergrowth, products and performance by Global Semiconductor Alliance

Tech Industry Veteran to Lead SiFive Silicon BU Growth and Execution

Mike Schroeder to Lead Talent Acquisition and Employee Engagement to Guide SiFive's Hypergrowth

Key new technologies for artificial intelligence, automotive, and industrial markets to be unveiled

SiFive RISC-V-based rapid design methodology enables fast development of IoT devices connected to AWS

Innovative New SiFive Learn Inventor To Empower a New Generations of Makers and Engineers

Arm Veteran to Enable Next-Generation High-Performance Processor Development

Arm Veteran to Oversee and Drive Strategy for Continued Sales and Revenue Hypergrowth

Use of SiFive’s RISC-V Core IP Enables Low Power AI IoT Edge and End Point Devices

Use of SiFive’s RISC-V Core IP Enables Low Power AI IoT Edge and End Point Devices

Linley Fall Processor Conference Presentation Details New SiFive IP For Automotive and IoT Edge Markets

Linley Fall Processor Conference Presentation Details New SiFive IP For Secure SoC Designs

Gives SoC designers an easy way to add post-manufacturing design flexibility Builds on previously announced strategic partnership and SoC template

Mentor Graphics, a Siemens business; EITESAL NGO; the American University in Cairo. and Efabless are co hosting the RISC-V symposium & workshop

New Partnerships Add Key IP For Efficient Embedded Vision SoC Designs

DTS INSIGHT expands into Semiconductor Market with SiFive IP and tools

World Leading RISC-V IP Portfolio with integrated Instruction Trace Encoder

Proven Expertise In Developing Custom Silicon Drives Datacenter Innovation

SiFive Keynote and Presentation detail new technology for Intelligence and Security

Signature third-party IP ecosystem allows low-cost, rapid prototyping and innovative IP licensing for AI, edge computing

Central Texas' Hill Country area populated by high-tech companies is joined by the latest office of the leader in RISC-V semiconductor IP design and development

Compelling Portfolio and Strategic Partnerships Propel RISC-V Leader into Hypergrowth

RISC-V Leader's Global Hypergrowth Attracts Strong Venture Backing

LAS VEGAS, June 3, 2019 -- Design Automation Conference -- SiFive, the leading provider of commercial RISC-V processor IP, design platforms, and custom SoC solutions, announced today a new partnership with Avatar Integrated Systems, a leader in next-generation physical design solutions. The partnership enables SiFive to use Avatar's physical design implementation tools within the SiFive cloud design environment.

Imagination Technologies joins SiFive's DesignShare Ecosystem, Enabling RISC-V users to access industry-leading IP

Powerful one-day events to be held in Cambridge, Grenoble, Stockholm, Moscow, Munich and Amsterdam

Metropolitan Portland area has evolved into an international center of open source hardware development

RISC-V pioneer and ultra-low power leader bring Freedom Aware SoC Templates to market

Includes critical IP validation for HBM2E 3.2Gbps Interface, TCAM and more

RISC-V Leader brings unmatched advanced 64-bit Core IP capability to embedded space

Human interface solutions leader uses SiFive Core Designer to configure embedded processor in two months

Executives to discuss new business models, optimizing RISC-V based processors and customizing architectures for AI implementations at Design and Reuse IP-SOC day and Linley Group events

Hiren Majmudar joins RISC-V leader to head business development efforts

Optimized for data centers, 5G/edge cloud and autonomous vehicles

Powerful and engaging events advance global knowledge about the RISC-V ISA and foster greater collaboration and opportunity within the open-source community

RISC-V leader honored for its products, growth and performance by Global Semiconductor Alliance

Establish partnership for delivering increased possibilities for powerful RISC-V implementations

Demonstrations at RISC-V Summit Dec. 4-5 to Show Size, Power and Performance Benefits of Integrating PolarFire SoC's Hard CPU Subsystem with Programmable Logic

SiFive leads RISC-V ecosystem at inaugural summit with range of cores, RISC-V silicon, proof points, demonstrations, partnerships, talks and panels

Latest contribution to ecosystem enables connectivity solutions for storage, networking, artificial intelligence, accelerators and high-performance computing applications

Mohit Gupta will oversee the rapidly expanding DesignShare program

Newly unveiled features and continued RISC-V investment in domain-specific architectures enable innovations in 5G, networking, storage, artificial intelligence and sensor fusion

Berkeley SkyDeck Collaborates with TSMC, Cadence, and SiFive to Provide Expertise and Support for its New Accelerator Chip Track

SAN MATEO, Calif. – Oct. 2, 2018 – SiFive, the leading provider of commercial RISC-V processor IP, today announced the appointment of Keith Witek as Senior Vice President of Corporate Development and General Counsel.

SAN MATEO, Calif. – Sept. 13, 2018 – SiFive, the leading provider of commercial RISC-V processor IP, today announced that Wasiela, a provider of innovative PHY-layer IP from the system and algorithmic levels all the way to implementation, has joined the DesignShare ecosystem. The availability of Wasiela encryption, forward error correction (FEC) and connectivity IP through the program will ease the development of reliable and secure high-throughput data communications for the RISC-V platform.

SAN MATEO, Calif. – Aug. 21, 2018 – SiFive, the leading provider of commercial RISC-V processor IP, today announced that ASIC Design Services, a design house, IP provider, and a distributor for FPGA and EDA software, has joined the DesignShare ecosystem. Through this partnership, ASIC Design Services will provide its Core Deep Learning (CDL) technology that accelerates Convolutional Neural Networks (CNNs) on power-constrained embedded hardware platforms.

Cupertino, Calif. – August 20, 2018 – SiFive, the leading provider of commercial RISC-V processor IP, today announced the first open-source RISC-V-based SoC platform for edge inference applications based on NVIDIA's Deep Learning Accelerator (NVDLA) technology.

SAN MATEO, Calif. – Aug. 14, 2018 – SiFive, the leading provider of commercial RISC-V processor IP, today announced a new member to its growing DesignShare economy: OPENEDGES, a provider of IPs for smart computing. The partnership makes available OPENEDGES’ ORBIT^TM Memory Controller IP to system developers via DesignShare, which enables customers incorporate world-class IP into their prototypes without having to pay for IP costs upfront.

Milpitas, Calif. – August 7, 2018 – Mobiveil, Inc. a provider of Serial Interconnect IP blocks and platforms targeting Flash Storage, IoT and Communication markets, has selected SiFive’s multicore E51 and U54 Core IPs to power Mobiveil’s new advanced configurable Gen4 PCIe-NVMe SSD platform offering a high performance and low power SSD solution for data center storage applications. SiFive’s heterogenous, coherent RISC-V core complex in a high-performance FPGA along with Mobiveil's Silicon Proven IP blocks (Gen4 PCIe, NVMe , LDPC, ONFI and Memory controller IP), provides data center customers a platform to develop their unique applications on RISC-V processors.

SAN MATEO, Calif. and SANTA CLARA, Calif. – August 7, 2018 – SiFive, the leading provider of commercial RISC-V processor IP, and FADU, a fabless company developing solutions and systems for the memory and storage market, today announced the availability of FADU’s Annapurna SSD Controller and FADU Bravo Series Enterprise SSD, powered by SiFive’s industry leading 64-bit, E51 multicore RISC-V Core IP.

SAN MATEO, Calif. and SAN JOSE, Calif. – August 7, 2018 – SiFive, the leading provider of commercial RISC-V processor IP, and eSilicon, an independent provider of FinFET-class ASICs, market-specific IP platforms and advanced 2.5D packaging solutions, today announced that, after extensive review and testing of available options in the market, eSilicon has selected the SiFive E2 Core IP Series as the best solution for its next-generation SerDes IP at 7nm.

SAN MATEO, Calif. – July 27, 2018 – SiFive, the leading provider of commercial RISC-V processor IP, today welcomed Chipus Microelectronics, a semiconductor company with proven expertise in the development of ultra-low-power (ULP), low-voltage, analog and mixed-signal integrated circuits, to the growing DesignShare ecosystem. Through the partnership, Chipus will provide ULP IP for power management and ULP RF Front-Ends.

SAN MATEO, Calif. – July 10, 2018 – SiFive, the leading provider of commercial RISC-V processor IP, today announced that Terminus Circuits, a provider of interconnect solutions, has joined the expanding DesignShare economy. Through DesignShare, Terminus Circuits will offer complete ASIC solutions for products that are modular and scalable.

San Mateo, Calif. – June 25, 2018 – SiFive, the leading provider of commercial RISC-V processor IP, today announced the availability of its E2 Core IP Series, configurable low-area, low-power microcontroller (MCU) cores designed for use in embedded devices. The E2 Series extends SiFive’s product line with two new standard cores, the E21, which provides mainstream performance for MCUs, sensor fusion, minion cores and smart IoT markets; and the E20, the most power-efficient SiFive standard core designed for microcontrollers, IoT, analog mixed signal and finite state machine applications. Additionally, the company announced enhancements to its existing standard E3 and E5 Core IP Series.

San Mateo, Calif. – May 22, 2018 – SiFive, the leading provider of commercial RISC-V processor IP, today welcomed Brite Semiconductor, an ASIC service company invested by SMIC, to the growing DesignShare ecosystem.

Shanghai and San Mateo, Calif. – May 17, 2018 – Andes Technology Corporation, the prominent CPU IP provider, and SiFive Inc., the leading provider of ASIC design service and RISC-V CPU Core IP, have announced they are joining forces to jointly promote RISC-V. The two companies will each contribute their unique expertise in CPU development and support to expand the ecosystem for the RISC-V instruction set architecture (ISA) to enable a new era of processor innovation through open standard collaboration.

SAN MATEO, Calif. – May 15, 2018

SAN MATEO, Calif. – May 8, 2018 – SiFive, the leading provider of commercial RISC-V processor IP, today announced that Intel Capital participated in its recent Series C funding round. The investment was revealed at the Intel Capital Global Summit, at which SiFive CEO Naveed Sherwani pushed for the democratization of the semiconductor industry.

SAN MATEO, Calif. – May 8, 2018 – SiFive, the leading provider of commercial RISC-V processor IP, today opened the call for partnership applications for the Democratizing Ideas partnership initiative, which aims to support new, innovative ideas from academia, research institutions, students and the open source community based on the company’s Freedom Unleashed or Freedom Everywhere platforms. Announced at the RISC-V Workshop in Barcelona, the initiative is designed to further the company’s mission to democratize access to custom silicon to anyone who wants it.

SAN MATEO, Calif. – May 2, 2018 –

SAN MATEO, Calif. – April 12, 2018 – SiFive, the leading provider of commercial RISC-V processor IP, today announced that Dover Microsystems, a cybersecurity solutions provider, is the latest vendor to join the DesignShare ecosystem.

SAN MATEO – April 9, 2018

SAN FRANCISCO – April 2, 2018 – SiFive, the leading provider of commercial RISC-V processor IP, today announced it raised $50.6 million in a Series C round led by existing investors Sutter Hill Ventures, Spark Capital and Osage University Partners alongside new investor Chengwei Capital, and strategic investors including Huami, SK Telecom and Western Digital and other companies that are among the most respected and iconic companies in the industry. This Series C round brings the total investment in SiFive to $64.1 million. Additionally, the company also announced it has signed a multi-year license to its Freedom Platform with Western Digital, which has pledged to produce 1 billion RISC-V cores.

SAN MATEO, Calif. – March 22, 2018 – SiFive, the leading provider of commercial RISC-V processor IP, today announced that Mobiveil, a provider of Serial Interconnect IP blocks and platforms targeted for Flash Storage, IoT and Communication markets, has joined the growing DesignShare economy.

SAN MATEO, Calif. – March 8, 2018 – SiFive, the leading provider of commercial RISC-V processor IP, today announced the addition of Corigine, a fabless semiconductor and IP company, to the DesignShare economy.

SAN MATEO, Calif. – Feb. 26, 2018

SAN MATEO, Calif. – Feb. 14, 2018 – SiFive, the leading provider of commercial RISC-V processor IP, continues to grow its executive staff with the appointment of Shiva Natarajan as chief financial officer. Natarajan joins SiFive with more than two decades of financial management, accounting and strategic planning experience in both public and private technology companies.

SAN MATEO, Calif. – Feb. 7, 2018 – SiFive, the leading provider of commercial RISC-V processor IP, launched the industry’s first Linux-capable RISC-V based processor SoC. The company demonstrated the first real-world use of the HiFive Unleashed board featuring the Freedom U540 SoC, based on its U54-MC Core IP, at the FOSDEM open source developer conference on Saturday.

SAN MATEO, Calif. – Jan. 30, 2018 – SiFive, the leading provider of commercial RISC-V processor IP, today announced Shafy Eltoukhy as vice president of operations. Eltoukhy, a veteran of Microsemi and Intel, will lead SiFive’s DesignShare activities and ensure the smooth rollout of new Core IP, SoCs and services.

SAN MATEO, Calif. – Jan. 22, 2018 – SiFive, the leading provider of commercial RISC-V processor IP, today announced the appointment of Sunil Shenoy as vice president of hardware engineering. The news follows SiFive’s momentous expansion last quarter with its strategic partnerships, launch of the first Linux-capable RISC-V core and growth of the DesignShare program.

SAN JOSE, Calif. – Nov. 28, 2017 – SiFive, the first fabless provider of customized, open-source-enabled semiconductors, today announced that Think Silicon, a leader in developing ultra-low power graphics IP technology, has joined the growing DesignShare economy. Through DesignShare, Think Silicon will make its complementary NEMA^®|GPU and NEMA^®|dc IP available for SiFive’s Freedom SoCs Platform at reduced upfront investment from customers.

SAN MATEO, Calif. – Nov. 28, 2017 – At the 7th RISC-V Workshop today, SiFive, the first fabless provider of customized, open-source-enabled semiconductors, announced a number of new partnerships and products that exemplify the company’s rapid growth over the past year. These announcements provide further proof of SiFive’s leadership in aligning with industry leaders to spur innovation in the plateauing semiconductor industry as well as the company’s ability to meet increased demand for open access to custom silicon. The adoption of SiFive’s RISC-V Core IP continues to grow, with more than 150 evaluation licenses in progress.

SAN MATEO, Calif. – Nov. 28, 2017 – SiFive announced today that it has joined GLOBALFOUNDRIES’ FDXcelerator™ Partner Program, and will be making RISC-V CPU IP including SiFive’s E31 and E51 RISC-V cores available on GF’s 22FDX® process technology. Based on the open source RISC-V ISA, the SiFive E31 offers embedded chip designers new capabilities in high performance within strict area and power requirements, and the SiFive E51 offers a full 64-bit performance at 32-bit price, power and area.

SAN JOSE, Calif. – Nov. 28, 2017 – SiFive, the first fabless provider of customized, open-source-enabled semiconductors, and Microsemi Corporation (Nasdaq: MSCC), a leading provider of semiconductor solutions differentiated by power, security, reliability and performance, at the 7th RISC-V Workshop today announced the companies have formed a strategic relationship to meet the growing interest and demand in the RISC-V instruction set architecture. The companies have previously collaborated to provide RISC-V soft CPU cores for Microsemi’s PolarFire^® FPGAs, IGLOO™2 FPGAs, SmartFusion™2 system-on-chip (SoC) FPGAs and RTG4™ FPGAs, currently available as part of the Microsemi Mi-V RISC-V ecosystem.

SAN MATEO, Calif. – Nov. 14, 2017 – SiFive, the first fabless provider of customized, open-source-enabled semiconductors, today announced that Analog Bits, the industry’s leading provider of low-power mixed-signal IP (Intellectual Property) solutions, has joined the growing DesignShare economy. Analog Bits will provide precision clocking macros such as PLLs and SERDES IP available for the SiFive Freedom platforms through the DesignShare initiative.

SAN MATEO, Calif. – Nov. 8, 2017 – SiFive, the first fabless provider of customized, open-source-enabled semiconductors, has once again made the shortlist for two UBM Annual Creativity in Electronics (ACE) Awards. Honored this year were the developers of the HiFive1 for "Design Team of the Year," and Jack Kang, SiFive vice president of product and business development as one of the finalists for "Executive of the Year."

SAN MATEO, Calif. – Nov. 7, 2017 – SiFive, the first fabless provider of customized, open-source-enabled semiconductors, today announced the addition of eMemory, the IP provider of logic-based, non-volatile memory (Logic NVM), to the DesignShare economy. eMemory will make its embedded NVM silicon IP technology available for the SiFive RISC-V based Freedom platform as part of the DesignShare initiative.

SAN MATEO AND MOUNTAIN VIEW, Calif. – Oct. 31, 2017 – SiFive, the first fabless provider of customized, open-source-enabled semiconductors, and Flex Logix™, a leader in embedded FPGA IP and software, today announced they will partner to make Flex Logix EFLX^® embedded FPGA available for the SiFive Freedom Platform as part of the DesignShare program. The availability of Flex Logix IP through DesignShare eases time to market and removes traditional barriers to entry that have blocked smaller companies from developing custom silicon.

HÖHENKIRCHEN-SIEGERTSBRUNN, Germany, and SAN MATEO, Calif. – Oct. 24, 2017 – Lauterbach, the leading manufacturer of microprocessor development tools, and SiFive, the first fabless provider of customized, open-source-enabled semiconductors, today announced the availability of Lauterbach’s TRACE32 toolset to provide debug capabilities for SiFive’s E31 and E51 RISC-V Core IP, based on the free and open RISC-V ISA. Lauterbach support for SiFive cores is the latest addition to the growing ecosystem of industry-leading development tools to become available for RISC-V based silicon.

SAN MATEO, Calif. – Oct. 4, 2017 – SiFive, the first fabless provider of customized, open-source-enabled semiconductors, today announced the availability of U54-MC Coreplex IP, the industry’s first RISC-V based, 64-bit, quadcore real-time capable application processor with support for full featured operating systems such as Linux. The free and open RISC-V architecture, which is supported by an ecosystem comprising more than 70 companies, has seen tremendous growth in the embedded segment. The release of the U54-MC Coreplex marks the architecture’s expansion into the application processor space – opening entirely new use cases for RISC-V.

SAN MATEO, Calif. – Sept. 26, 2017 – SiFive, the first fabless provider of customized, open-source-enabled semiconductors, today announced it has joined the TSMC (NYSE: TSM) IP Alliance Program, part of the TSMC Open Innovation Platform®, which accelerates innovation in the semiconductor design community. As an alliance member, SiFive’s RISC-V based Coreplex IP are made available to its customers to reduce time-to-market, increase return on investment and reduce waste in the manufacturing process.

HILDEN, Germany, and SAN MATEO, Calif. – Sept. 19, 2017 – SEGGER Microcontroller, a leading supplier of software, hardware and development tools for embedded systems, and SiFive, the first fabless provider of customized, open-source-enabled semiconductors, today announced the availability of SEGGER J-Link support for SiFive Coreplex IP, based on the RISC-V architecture. The growing interest in Coreplex IP is increasingly prompting vendors like SEGGER to make its industry leading tools available as part of the RISC-V ecosystem.

SANTA CLARA, Calif. – 9/12/2017

SAN MATEO, Calif. – Sept. 7, 2017 – SiFive, the first fabless provider of customized, open-source-enabled semiconductors, today announced that UltraSoC will provide debug and trace technology for the SiFive Freedom platform, based on the RISC-V open source processor specification as part of the DesignShare initiative. UltraSoC’s embedded analytics IP will be available through the recently announced SiFive DesignShare ecosystem that gives any company, inventor or maker the ability to harness the power of custom silicon. UltraSoC’s debug and trace functionality will enable users of the Freedom platform to access a wide variety of tools and interfaces to use in their developments.

SAN MATEO, Calif. – August 21, 2017 – SiFive, the first fabless provider of customized, open-source-enabled semiconductors, today announced it will partner with Rambus, (NASDAQ: RMBS), a leader in digital security, semiconductor and IP products and services, to make Rambus cryptography technology available for the SiFive Freedom platforms. To speed time to market and remove the barriers that traditionally have blocked smaller players from developing custom silicon, leading companies in the semiconductor ecosystem have developed a new DesignShare concept, which offers IP at a reduced cost.

SAN FRANCISCO – August 15, 2017 – SiFive, the first fabless provider of customized, open-source-enabled semiconductors, today announced that industry veteran Naveed Sherwani has joined the company as CEO to lead it through its next phase of growth. Stefan Dyckerhoff, who had held the top spot at the company since its inception, will remain a member of the SiFive board of directors.

SAN FRANCISCO – May 19, 2017 – SiFive, the first fabless provider of customized, open-source-enabled RISC-V semiconductors, today announced the release of the Arduino Cinque, the first RISC-V-based development board for the popular open-source hardware platform. Today’s announcement marks the latest development in SiFive’s work to democratize access to custom silicon.

SAN FRANCISCO – May 8, 2017 – SiFive, the first fabless provider of customized, open-source-enabled semiconductors, today announced it has raised $8.5 million in a Series B round led by Spark Capital with participation from Osage University Partners and existing investor Sutter Hill Ventures. This Series B round brings the total investment in SiFive to $13.5 million. The funding comes as SiFive experiences a growing demand for RISC-V IP and increased interest in custom silicon.

SAN FRANCISCO – May 4, 2017 – SiFive, the company founded by the inventors of the free and open RISC-V instruction set architecture (ISA), today announced the immediate availability of its Coreplex IP, the fastest and easiest way to license RISC-V cores. With the rapid growth in the RISC-V ecosystem, SiFive Coreplex IP designs have become the de facto leader for RISC-V cores, with more public customers, silicon and development boards than any other RISC-V vendor. SiFive’s hassle-free “study-evaluate-buy” purchase process means that designers can get their hands on Coreplex IP RTL in a matter of minutes.

SAN FRANCISCO – Nov. 29, 2016 – SiFive, the first fabless provider of customized, open-source-enabled semiconductors, today announced the availability of its Freedom Everywhere 310 (FE310) system on a chip (SoC), the industry’s first commercially available SoC based on the free and open RISC-V instruction set architecture, along with the corresponding low-cost HiFive1 software development board. As part of this availability, SiFive also has contributed the register-transfer level (RTL) code for FE310 to the open-source community, which the company revealed today at the 5th RISC-V Workshop in Mountain View, Calif.

SAN FRANCISCO – July 11, 2016 – SiFive, the first fabless semiconductor company to build customized, open-source enabled semiconductors, today announced its flagship Freedom family of system on a chip (SoC) platforms. Built around the free and open RISC-V instruction set architecture invented by the company’s founders at the University of California, Berkeley, SiFive’s Freedom U500 and Freedom E300 platforms represent a fundamentally new approach to designing and producing SoCs that redefines traditional silicon business models and reverses the industry’s prohibitively rising licensing, design and implementation costs.