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All About Circuits — Dec 10, 2021
The 2021 RISC-V Summit Charts the Wildfire Expansion of Open-source Hardware
With this year’s RISC-V Summit officially concluded, open-source processors are being adopted faster than ever. Membership in RISC-V International has grown by 130% in 2021 alone—and individual contributors have enthusiastically chipped in. What has the electrical-engineering community achieved throughout the past 12 months with RISC-V?
CNX Software — Dec 10, 2021
SiFive Essential 6-Series RISC-V processors target Linux, real-time applications
SiFive has been busy. Just a few days after the SiFive Performance P650 announcement, the company has announced the SiFive Essential 6-Series RISC-V processor family starting with four 64-bit/32-bit real-time core, and two Linux capable application cores, plus the SiFive 21G3 release with various improvements to existing families.
SiFive — Dec 6, 2021
SiFive Expands and Improves Industry-Leading RISC-V Processor Portfolio
The SiFive 21G3 Release introduces the new SiFive Essential 6-Series range of RISC-V processors for area-focused computing applications
RISC-V International — Dec 6, 2021
Next generation music AI engine available for RISC-V
Helios is an advanced patent-protected AI music recommendation engine that can be used to search commercial music catalogues using music itself as the search key. Applications are wide ranging, such as production studios seeking synchronization licenses from record labels, streaming services, online music stores, and much more.
The engine’s debut on RISC-V opens a goldmine of new commercial opportunities in the embedded space for digital jukeboxes, IoT, in-flight entertainment, and luxury vehicles to name a few.
Tom's Hardware — Dec 3, 2021
SiFive Announces Latest RISC-V CPU, The P650
San Francisco-based fabless semiconductor provider SiFive today announced a new processor it describes as “the fastest licensable RISC-V processor IP core in the market”. The SiFive Performance P650.
VentureBeat — Dec 2, 2021
SiFive moves into high-end RISC-V processors with P650 design
The design for the P650 processor, which other companies will take and turn into working products, is the highest-performing member of the SiFive Performance family, which the company said is expected to be the fastest licensable RISC-V processor IP core. It’s another step in the ongoing quest to show that the open source hardware movement can keep pace with rivals such as Arm and Intel.
CNET — Dec 2, 2021
SiFive's new chip could lead to revamped phone brains in 2023
A startup called SiFive announced a new processor design Thursday that could revamp mobile phones, cars and other digital devices if the company's plans work out. Its Performance P650 design comes with a 50% speed boost over the P550 that arrived in June.
Reuters — Dec 2, 2021
SiFive speeds up computing chip designs as it staffs up
Chip technology firm SiFive Inc on Thursday said it has sped up its computing core designs by 40% and now has a headcount of 700 employees, with plans to double its staff by next year.
SiFive — Dec 2, 2021
SiFive Raises RISC-V performance bar with New Best-in-Class SiFive Performance P650 Processor
The SiFive Performance P650 processor is expected to be the fastest licensable RISC-V processor IP core in the market, bringing RISC-V into new markets and applications, and will debut to lead partners in Q1 2022.
HardwareLuxx — Nov 13, 2021
FADU's PCIe 5.0 SSD controller uses S5 cores from SiFive
The South Korean chip startup FADU has announced its new generation of SSD controllers, the FC5161.If the South Koreans have their way, this will be one of the fastest for PCIe 5.0 SSDs, primarily in the data center area.The FADU FC5161 is to connect the storage via four PCIe 5.0 lanes, speaks NVMe 1.4+ and OCP Cloud Spec 2.0. [GER]
Military & Aerospace Electronics — Nov 4, 2021
Safety-critical real-time operating system (RTOS) for RISC-V microprocessors introduced by Green Hills
The INTEGRITY for RISC-V RTOS is integrated with RISC-V processor solutions including hardware reference boards from Microchip and SiFive, along with processor intellectual property (IP) from SiFive, a RISC-V IP provider.
Electronics Weekly — Oct 26, 2021
Sneak peek into SiFive’s most powerful RISC-V yet
SiFive has briefly pulled back the curtains on its most powerful Risc-V processor yet.
So far only called ‘Next Generation Core’ or Next-Gen, its official name, final design specs and availability will be unveiled early in December at the Risc-V Summit.
Golem — Oct 22, 2021
SiFive has the fastest RISC-V core
The performance of the as yet nameless RISC-V core should be 50 percent higher than that of its predecessor, and there is also the option for 16-core clusters. [GER]
Tom's Hardware — Oct 22, 2021
SiFive Envisions 128-Core RISC-V SoCs as Gap With x86 and Arm Closes
SiFive: RISC-V has no limits. SiFive emerged from stealth mode as a developer of small, low-power cores for microcontrollers in 2016. By late 2020, the company had a chip that could run Linux and this week said that it developed a CPU core that is comparable to modern offerings designed by Intel and Arm. The company believes that such high-performance designs could be used for a wide variety of applications, including server-grade system-on-chips with 128-cores.
The Register — Oct 21, 2021
We're closing the gap with Arm and x86, claims SiFive: New RISC-V CPU core for PCs, servers, mobile incoming
SiFive reckons its fastest RISC-V processor core yet is closing the gap on being a mainstream computing alternative to x86 and Arm.
The Register — Oct 8, 2021
Proposed RISC-V vector instructions crank up computing power on small devices
When you need to do audio, voice or image processing at the network edge or on a battery budget.
Golem — Oct 7, 2021
RISC-V is here to stay
With the HiFive Unmatched, there is finally a powerful developer board with RISC-V, the software is also well-engineered. Apple, Google, Nvidia, Samsung, Qualcomm - they all use them: The open instruction set architecture RISC-V is primarily used in embedded controllers in smartphones, for example. With the HiFive Unmatched, however, Sifive has released a well-equipped mini-ITX board that is aimed at developers or people who want to try out RISC-V. [GER]
HardwareLuxx — Oct 1, 2021
A look into the future? SiFive HiFive Unmatched viewed
X86 designs have dominated for years, but not only the power niche of IBM or the up-and-coming arm competition are putting pressure on the established microprocessor architecture. The open instruction set architecture (ISA) RISC-V could play an increasingly important role in many areas in the future. On the basis of the SiFive HiFive Unmatched, we want to take a closer look at this topic. [GER]
Phoronix — Sep 24, 2021
SiFive HiFive Unmatched Hands-On, Initial RISC-V Performance Benchmarks
A few weeks ago I finally received the HiFive Unmatched from SiFive as their flagship RISC-V development board. As a reminder this is their mini-ITX development board that is powered by their U740 SoC and features 16GB of DDR4 system memory, one PCI Express x16 slot that can work with AMD Radeon graphics cards on Linux, and other features. It's been a delight playing with this developer platform and enclosed are some early benchmarks as well showing off the U740 performance as well as how the Linux software support/performance has been evolving.
Tom's Hardware — Jul 22, 2021
World's First Desktop PC RISC-V Board Meets AMD Radeon RX 6700 XT
When SiFive introduced its HiFive Unmatched RISC-V desktop motherboard for developers last year, it was clear from the start that sooner or later an enthusiast would attempt to try using its U7 SoC for something it is not meant for: general PC usage with high-performance graphics and video decoding. That time has come as an enthusiast has managed to make AMD's Radeon RX 6700 XT work with a RISC-V SoC under Linux.
451 Research — Jul 12, 2021
SiFive shepherds RISC-V ISA to enterprise applications, broader adoption
The company is pushing the capabilities of the heretofore predominately embedded and IoT-focused RISC-V ISA further into visibility with the introduction of the SiFive Performance and SiFive Intelligence processor lines. The latter integrates RISC-V vector extensions and SiFive's proprietary vector extensions for use with AI/ML applications.
Canonical — Jun 23, 2021
Canonical enables Ubuntu on SiFive’s HiFive RISC-V boards
With Canonical announcing Ubuntu support for so much new hardware, the announcement of Ubuntu ported to a new architecture can go unnoticed. But today, we have a big one. Working with the leading RISC-V core IP designer and development board manufacturer, SiFive, we are proud to announce the first Ubuntu release for two of the most prominent SiFive boards, Unmatched and Unleashed.
Barcelona Supercomputing Center — Jun 22, 2021
BSC, Codeplay, and SiFive help accelerate applications on RISC-V thanks to V-extension support in LLVM
The Barcelona Supercomputing Center (BSC) has been collaborating with Codeplay Software and SiFive to implement support for the RISC-V V-extension v0.10 in the LLVM compilation infrastructure. Thanks to this support, users of RISC-V will be able to take advantage of vector computation capabilities of the RISC-V V-extension through C/C++ intrinsics.
CNet — Jun 22, 2021
SiFive chip design challenges Arm and leads to Intel alliance
Startup SiFive announced a faster new processor design, the P550, that means its chips can better challenge Arm, the leader in processors for mobile devices and many other electronics products. And the company also deepened a partnership with another rival, Intel, for actually manufacturing the chips.
Reuters — Jun 22, 2021
SiFive Inc on Tuesday released a new computing chip design that aims to challenge Arm Ltd's dominance in smartphone chips
Intel said it is working with SiFive to ensure that the new cores can be manufactured in its newest 7-nanometer chip factories. Intel will offer those manufacturing services to outside chip companies as part of its effort to become a chip contract manufacturer.
Anandtech — Jun 22, 2021
Intel Licenses SiFive’s Portfolio for Intel Foundry Services on 7nm
Today’s announcement from SiFive comes in two parts; this part is significant as it recognizes that Intel will be enabling SiFive’s IP portfolio on its 7nm manufacturing process for upcoming foundry customers.
[Note - this process technology is now known as 'Intel 4']
SiFive — Jun 22, 2021
SiFive Performance P550 Core Sets New Standard as Highest Performance RISC-V Processor IP
New SiFive Performance Family of application processors offers best in class performance, area, and efficiency for a wide variety of markets
ArsTechnica — Jun 22, 2021
SiFive’s brand-new P550 is one of the world’s fastest RISC-V CPUs
Today, RISC-V CPU design company SiFive launched a new processor family with two core designs: P270 (a Linux-capable CPU with full support for RISC-V's vector extension 1.0 release candidate) and P550 (the highest-performing RISC-V CPU to date).
CRN — Jun 16, 2021
The 10 Hottest Semiconductor Startups of 2021
These startups are taking on semiconductor heavyweights like Intel and Nvidia with new kinds of silicon solutions for compute, storage and networking, many of which are headed for the data center. SiFive is providing an open-source alternative to Arm’s CPU design business with core designs and custom silicon solutions for AI, high-performance computing and other growing markets based on the open and free RISC-V instruction set architecture.
SEGGER — May 27, 2021
SEGGER’s emRun Runtime Library Licensed by SiFive for Superior Code Size and Performance Improvements
The SEGGER emRun runtime library is available as part of the recently announced SiFive 21G1 release. SiFive’s focus on toolchain and library support enables key market requirements, including reduced code size and lower memory footprints. To support this goal, SiFive has licensed emRun as part of the SiFive Freedom Tools and Freedom-E-SDK packages. This integration enables chip designers to easily achieve optimum performance, while reducing code size by up to 25%.
Liliputing — May 21, 2021
HiFive Unmatched RISC-V computer board is now shipping
At first glance, the HiFive Unmatched from SiFive looks like just another mini ITX computer motherboard. But rather than an x86 chip, this system is powered by RISC-V processor.
First introduced last fall, the board is aimed at developers rather than the general public, and with a $665 price tag, it’s a lot more expensive than some other RISC-V development boards. But the HiFive Unmatched is also one of the most powerful products in this emerging category to date, thanks to SiFive’s FU740 processor.
Dialog Semiconductor — May 11, 2021
Dialog Semiconductor Selected as SiFive Preferred Power Management Partner for RISC-V Development Platforms
Dialog is the preferred power management partner for the SiFive HiFive Unmatched PC form-factor RISC-V Linux Development Platform, featuring the SiFive Freedom U740 RISC-V SoC.
The Linley Group Microprocessor Report — May 11, 2021
SiFive 21G1 Update Boosts Hash Rates
SiFive’s intellectual-property (IP) portfolio is getting smarter thanks to its “Intelligence” platform and 21G1 release. At the recent Linley Spring Processor Conference, the company announced a new AI platform that uses the Intelligence extensions to reduce convolution-processing time by 4x compared with a standard RISC-V vector implementation. A few weeks earlier, it announced the 21G1 update, which increases SHA-256 hash rates by 35%, among other instruction-set and architectural improvements.
Phoronix — May 6, 2021
A Number Of Exciting RISC-V Improvements For Linux 5.13
From bringing up the PolarFire ICICLE SoC to adding support for KProbes, FORTIFY_SOURCE, and other new kernel features for the RISC-V architecture, the Linux 5.13 kernel changes are exciting for this open-source processor ISA.
SiFive — Apr 29, 2021
SiFive and Samsung Foundry Extend Partnership to Accelerate AI SoC Development
Configurable SiFive RISC-V AI SoC Development Platform is built on 14nm Samsung process technology to accelerate custom Machine Learning solutions
Tom's Hardware — Apr 22, 2021
Jim Keller-Led Tenstorrent Licenses RISC-V for AI
The very fact that Tenstorrent chose to use SiFive-developed RISC-V CPU design is noteworthy by itself and is a testament to the new architecture.
SiFive — Apr 22, 2021
Tenstorrent Selects SiFive Intelligence X280 for Next-Generation AI Processors
SiFive Intelligence IP integral component of future Tenstorrent AI architectures
SiFive — Apr 21, 2021
Renesas and SiFive Partner to Jointly-Develop Next-Generation High-End RISC-V Solutions for Automotive Applications
SiFive to License Industry-Leading RISC-V Core IP Portfolio to Renesas
Renesas — Apr 20, 2021
Renesas and SiFive Partner to Jointly-Develop Next-Generation High-End RISC-V Solutions for Automotive Applications
“RISC-V is an important element in providing additional capabilities and options for new and existing customers,” said Takeshi Kataoka, Senior Vice President, General Manager of Automotive Solution Business Unit at Renesas. “We are very excited to work with SiFive as their lead partner to develop next-generation semiconductor solutions through the collaboration of our accumulated expertise in the automotive field, and SiFive’s high-end RISC-V technologies.”
Tom's Hardware — Apr 13, 2021
SiFive Tapes Out First 5nm TSMC RISC-V Chip With 7.2 Gbps HBM3
SiFive on Tuesday said that its OpenFive division has successfully taped out the company's first system-on-chip (SoC) on TSMC's N5 process technology. The SoC can be used for AI and HPC applications and can be further customized by SiFive customers to meet their needs.
SiFive — Apr 8, 2021
SiFive Intelligence for Modern ML Architectures Presentation at Linley Spring Processor Conference
Leading provider of RISC-V processor IP to share details of new initiatives for AI-enabled markets
SiFive — Mar 31, 2021
SiFive and DARPA collaborate to bring the power of RISC-V to Technology Innovation
Licensing agreement provides access to a broad portfolio of IP from the inventors of RISC-V
SiFive — Mar 18, 2021
SiFive and ArchiTek Enable Secure, Private, Flexible Edge AI Computing With AiOnIc® Processor
New Edge AI processor accelerates key workloads while offering flexibility for changing AI needs
AWS IoT — Feb 25, 2021
AWS IoT at Embedded World 2021 DIGITAL Features SiFive HiFive Unmatched
Building a successful IoT solution depends on the tens of billions of devices that sit at the edge, in our homes and offices, in factories, in oil and agricultural fields, in planes and ships, in automobiles — everywhere. Quickly start building with solutions for cross-industry edge applications using the SiFive HiFive Unmatched developer board, as featured in the demonstrations.
Wanxiang Blockchain on Medium — Feb 23, 2021
Wanxiang Blockchain Forms RISC-V International Blockchain SIG with SiFive & Others
At MWC Shanghai, Wanxiang Blockchain and aitos.io announced they joined RISC-V International as strategic members and have formed RISC-V International’s new Blockchain SIG (special interest group) in collaboration with LeapFive, StarFive and SiFive. This group will help integrate blockchain technologies with RISC-V solutions, and promote the development of trusted blockchain databases.
“The adoption of RISC-V to develop blockchain technologies, and the use of RISC-V International working groups to encourage broad industry collaboration, demonstrates the power and flexibility of the freely available and open specification ISA,” said Dr. Chris Lattner, President of Engineering and Product, SiFive.
aicas — Feb 18, 2021
aicas and SiFive Bridge Flexibility and Performance with RISC-V, JamaicaVM Integration
Together with Amazon Web Services (AWS), SiFive and aicas will deliver a virtual demonstration of the solution during embedded world 2021 DIGITAL, March 1-5, 2021. See aicas events online for details about the demo of AWS IoT Greengrass 2.0 running on a SiFive RISC-V unmatched board and go to aicas’ virtual exhibition stand and claim a voucher for a free ticket to attend the virtual event
eTopus — Feb 10, 2021
eTopus Technology Announces Innovative SerDes Technology for Data Center, Cloud, Edge, and 5G Base Stations
Danfeng Xu, co-founder & VP of analog design, will present the paper titled “A Scalable Adaptive ADC/DSP-Based 1.25-to-56Gbps/112Gbps High-Speed Transceiver Architecture Using Decision-Directed MMSE CDR in 16nm and 7nm” in the 2021 International Solid-State Circuits Virtual Conference Ultra-High-Speed Wireline session beginning on Tuesday, February 16th, 2021. The eTopus high-speed transceiver architecture supports a wide range of data rates for multiple standards, such as Ethernet, OIF CEI-112G, PCI-SIG® PCIe® Gen 1 through 6, and insertion loss from few to above 35dB. eTopus has selected SiFive E2-Series RISC-V Core IP to power the receiver DSP control functions.
PRTimes (JP) — Feb 8, 2021
ArchiTek announces "AiOnIc" AI processor for edge computing using "aIPE" architecture combined with SiFive RISC-V processor cores
ArchiTek announces "AiOnIc" proof-of-concept chip equipped with its own "aIPE" (ArchiTek Intelligence® Pixel Engine) architecture and featuring SiFive RISC-V Processor cores. The chip aims to be the de facto edge AI processor through offering fanless operation in a small size and low power consumption, using a 12nm process. Highly efficient hardware processing makes it ideal for embedded systems such as IoT. In addition, a cooling fan is not required, and a waterproof and dustproof system can be constructed in a closed housing.
BusinessWire — Jan 13, 2021
BeagleV™ single-board computer features SiFive 7-Series Multicore RISC-V Processor IP
Seeed, BeagleBoard.org, and StarFive are collaborating to produce an affordable, Linux-capable 64-bit multicore RISC-V single board computer at an affordable price, using SiFive U74-MC Core IP
SiFive — Dec 8, 2020
SiFive Wins 3rd Consecutive Title of Most Respected Private Semiconductor Company
RISC-V Leader Recognized by Global Semiconductor Alliance For Developing RISC-V-based IP Solutions to Solve Next-Generation Computing Challenges
Global Semiconductor Alliance — Dec 3, 2020
SiFive Wins 3rd Consecutive Global Semiconductor Alliance 'Most Respected Private Company' Award!
For over a quarter century, the GSA Awards have recognized the achievements of top performing semiconductor companies in several categories ranging from outstanding leadership to financial accomplishments, as well as overall respect within the industry.
SiFive — Nov 19, 2020
BBC Learning and Tynker Collaborate on Coding for Kids with a Next-Generation Education Technology Mini-Computer
Featuring the voice and star of the Thirteenth Doctor, Jodie Whittaker, the HiFive Inventor is a powerful Internet of Things programmable computer designed to teach kids to code
SiFive — Nov 18, 2020
Bouffalo Lab Standardizes on SiFive RISC-V Embedded CPU Core IP for New IoT Products
SiFive E2 Core IP Flexibility and Power-efficient Performance Enable Bouffalo Product differentiation
OpenFive — Oct 5, 2020
OpenFive and AnalogX to Provide Optimized Chip-to-Chip Interface IP Solutions
OpenFive, the leading provider of customizable, silicon-focused solutions with differentiated IP, along with AnalogX, a provider of SerDes interface IP, today announced a complete sub-system solution and implementation for Chip-to-Chip (C2C) interface with ultra-low latency and power.
Level1Techs on YouTube — Sep 24, 2020
RISC-V Business: Testing Gaming and More on the HiFive Unmatched from SiFive
Wendell Wilson of Level 1 Techs tests the SiFive HiFive Unmatched RISC-V developer board in this 13:50 video on YouTube.
SiFive — Sep 17, 2020
SiFive Appoints Patrick Little as President and Chief Executive Officer
Industry Veteran To Lead Mission To Develop RISC-V-based Platforms to Solve Next-Generation Computing Challenges
NotebookCheck — Sep 15, 2020
SiFive announces new RISC-V processor architecture plus its first-ever desktop PC processor
In the event that Nvidia compromises most processor-related ARM IPs, SiFive's RISC-V scalable CPUs could see increased adoption even from mobile and smartphone OEMs. SiFive is already prepared to meet the increased demand with its updated AI-focused RISC-V microarchitecture that enables different classes of performance, efficiency and features for server-grade, HPC and even desktop PC systems.
SiFive — Sep 14, 2020
SiFive To Introduce New RISC-V Processor Architecture and RISC-V PC at Linley Fall Virtual Processor Conference
SiFive Founders and Inventors of RISC-V will deep dive new vector-based architecture, and debut new SoC for professional developers of RISC-V applications
SiFive — Sep 3, 2020
SiFive and Barcelona Supercomputing Center Advance Industry Adoption of RISC-V Vector Extension
The new API adds critical capabilities to widely used compilers, GCC & LLVM
SiFive — Aug 18, 2020
SiFive and Innovium Announce Collaboration to Accelerate Innovation in Data Center Networking
Innovium TERALYNX® products integrate SiFive RISC-V processor cores to increase lead in breakthrough switch silicon for Cloud and Edge data center networks
SiFive — Aug 17, 2020
SiFive Announces OpenFive, an Industry-Leading Custom Silicon Business Unit
OpenFive is a solution-centric and processor agnostic custom silicon business unit dedicated to building optimized domain-specific SoCs
The Register — Aug 17, 2020
ISA-agnostic OpenFive unit will focus on custom SoCs while parent will crack on with CPU blueprints
RISC-V processor specialist SiFive will double down on improving its CPU cores after pushing its system-on-chip design efforts into a new unit.
SiFive — Aug 11, 2020
SiFive Secures $61 Million in Series E Funding
Demand for Domain-Specific Architecture Drives Continued Investment in Processor Innovation
StarFive (China) — Jul 27, 2020
H3C Creates Research Network Processor using U7-Series Core IP
The new development chip from H3C Semiconductor Technology is a dual-core design with 400G Ethernet interface built using TSMC 16nm FinFET Compact Technology (FFC) process technology, and was able to run at up to 3.2GHz.
SiFive — Jul 22, 2020
SiFive Elevates Custom SoC Design With Enhanced Processor IP Portfolio
The SiFive 20G1 release delivers up to 2.8x more performance(1); up to 25% lower power(2); and up to 11% smaller area(3), for designing next-generation SoCs
EETimes — Jun 28, 2020
SiFive named to EETimes 2020 'Silicon 100' List
The EETimes Silicon 100 is a place identify the building blocks for future wonders: the daring innovators, fervent visionaries, serial investors, and barrier-busting men and women who have collectively given the world inventions that were unimaginable barely 100 years ago.
IAR Systems — Jun 24, 2020
IAR Systems delivers advanced trace for RISC-V based applications
Enhanced support for the SiFive Insight solution in IAR Embedded Workbench brings leading debug and trace capabilities to the RISC-V community
Embedded Computing Design — Jun 24, 2020
Special COVID-19 Edition of Embedded Executive featuring SiFive CEO, Dr. Naveed Sherwani
Different vendors are doing different things to cope with the COVID-19 pandemic. Many of them are doing their part to help get us through this awful time. One of those is SiFive, a fabless semiconductor company specializing in the RISC-V instruction set architecture. Hear what they are doing to help society in this week’s Embedded Executives podcast.
Green Hills Software — Jun 2, 2020
Green Hills Software Adds Industry-Leading Advanced Software Development Tools Support for RISC-V
Green Hills Software, the worldwide leader in embedded safety and security, today announced the availability and early customer adoption of its advanced software development tools targeting 32- and 64-bit RISC-V processor architectures.
SiFive — May 19, 2020
SiFive Partners With Coherent Logix for Mission-Critical Processor Solutions
SiFive Core IP Enables Market-Leading Applications for Military and Aerospace Markets
SiFive — Apr 30, 2020
SiFive Joins Open COVID Pledge to Fight Global Pandemic
The idea-to-silicon company pledges free SiFive E21 Standard Core for use in healthcare products
SiFive — Apr 2, 2020
Leading Industry Veteran Joins SiFive as Chief Financial Officer
Tech industry veteran to lead financial operations and drive SiFive growth
SiFive — Mar 31, 2020
SiFive to Present at Virtual Linley Spring Processor Conference
The idea-to-silicon company will be hosting two sessions during the online conference, in addition to serving as a Platinum sponsor.
Synopsys — Mar 25, 2020
SiFive Selects Synopsys Fusion Design Platform and Verification Continuum Platform to Enable Rapid SoC Design
SiFive, Inc. has selected Synopsys Fusion Design Platform™ and Verification Continuum® platform to enable rapid cloud-based design of next-generation customer silicon products.
SiFive — Mar 17, 2020
SiFive Launches Advanced Trace and Debug Portfolio, SiFive Insight
The portfolio enables users to access, observe, and control processor development in real-time, accelerating silicon time-to-market
SiFive — Jan 27, 2020
Former Google and Tesla Engineer Chris Lattner to Lead SiFive Platform
Distinguished Silicon Valley software engineer to bring increased customization and implementation tooling to SiFive SoC design methodology
Golem.de — Jan 24, 2020
Qualcomm uses RISC-V in Snapdragon chips
One of the largest SoC developers is now relying on RISC-V: Qualcomm integrates cores with the open instruction set architecture for embedded use in current and future Snapdragon chips.
TheRegister — Jan 8, 2020
RISC-V business: SiFive and CEVA join forces to enable the development AI-amenable, edge-oriented processors
System-on-a-chip IP partnership seeks to create more smart home, automobile, robotics, IoT, and industrial applications, among others
SiFive — Jan 7, 2020
SiFive and CEVA Partner to Bring Machine Learning Processors to Mainstream Markets
Joint silicon development through SiFive’s DesignShare Program combines IP and design strengths of both companies to develop Edge AI SoCs for a range of high-volume end markets including smart home, automotive, robotics, security, augmented reality, industrial and IoT
SiFive — Dec 30, 2019
SiFive to Attend CES 2020
SiFive to deepen AI portfolio with strategic new disclosures at CES 2020, unleashing semiconductor product roadmaps for consumer and commercial SoCs
ServeTheHome — Dec 14, 2019
Key Takeways from the 2019 RISC-V Summit
This week in San Jose, California I had the opportunity to join the 2019 RISC-V Summit. I wanted to do a short piece giving some thoughts on the summit itself while also covering a few of the big announcements from Western Digital, Microchip, and SiFive
Embedded Computing Design — Dec 12, 2019
Brekker RISC-V TrekApp for Automated, High-Coverage System Integration Test Suite Synthesis
Breker Verification Systems, a provider of Test Suite Synthesis tools based on the Portable Stimulus Standard (PSS), introduced its RISC-V TrekApp
Anandtech — Dec 12, 2019
Samsung to use SiFive RISC-V Cores for SoCs, Automotive, 5G Applications
At the annual RISC-V Summit this week, Samsung disclosed the use SiFive’s RISC-V cores for upcoming chips for a variety of applications. The company is joining a growing list of leading high-tech companies that have adopted the RISC-V architecture
SiFive — Dec 11, 2019
Lattice and SiFive Announce Collaboration to Allow Lattice FPGA Developers Easy Access to RISC-V Processors
Scalable Processor Core IP Running on Low Power, Small Form Factor FPGAs Could Power Millions of Smart Devices at the Edge
SiFive — Dec 11, 2019
Industry Veteran Randy Allen Joins SiFive as Vice President of RISC-V Software
SiFive’s new hire brings unparalleled experience in vectorization
Embedded Computing Design — Dec 11, 2019
Wind River Announces RISC-V Support for VxWorks RTOS
Wind River, a developer of software for the intelligent edge, announced RISC-V open architecture support for its VxWorks real-time operating system (RTOS)
Venturebeat — Dec 11, 2019
RISC-V grows globally as an alternative to Arm and it’s licensing fees
ARM is the most successful microprocessor architecture on the planet, with its licensees shipping billions of chips a year. But a rival has emerged in the past few years called RISC-V, a new kind of royalty-free architecture started by academics. Its proponents are holding an event in the heart of Silicon Valley to tout its growth
SiFive — Dec 10, 2019
SiFive Announces New Technologies for Mission-Critical and AI Markets
New SiFive Apex cores for mission-critical markets and SiFive Intelligence cores for vector processing workloads create a comprehensive IP portfolio for high-growth markets
TheRegister — Dec 10, 2019
RISC-V Xmas gifts: SiFive Emits Vector Enabled Cores
The RISC-V Summit kicks off in Silicon Valley today, and there were a few interesting announcements this morning
SiFive — Dec 9, 2019
SiFive Retains Title of Most Respected Private Semiconductor Company
RISC-V leader honored for second consecutive year for its hypergrowth, products and performance by Global Semiconductor Alliance
SiFive — Dec 6, 2019
Tech Industry Heavyweight Joins SiFive - Manoj Gujral Tapped As SVP & GM of Silicon Business Unit
Tech Industry Veteran to Lead SiFive Silicon BU Growth and Execution
SiFive — Dec 5, 2019
Another Leading Industry Veteran Joins SiFive As SVP of EX (Employee eXperience)
Mike Schroeder to Lead Talent Acquisition and Employee Engagement to Guide SiFive's Hypergrowth
SiFive — Dec 4, 2019
SiFive To Present New Technologies At RISC-V Summit 2019
Key new technologies for artificial intelligence, automotive, and industrial markets to be unveiled
SiFive — Dec 3, 2019
SiFive Learn Inventor Development System Now AWS Qualified
SiFive RISC-V-based rapid design methodology enables fast development of IoT devices connected to AWS
SiFive — Dec 2, 2019
SiFive Announces SiFive Learn Initiative
Innovative New SiFive Learn Inventor To Empower a New Generations of Makers and Engineers
SiFive — Nov 26, 2019
SiFive Welcomes Ann Chin As SiFive IP Business Unit General Manager
Arm Veteran to Enable Next-Generation High-Performance Processor Development
SiFive — Nov 21, 2019
SiFive Welcomes Stuart Ching As Chief Revenue Officer
Arm Veteran to Oversee and Drive Strategy for Continued Sales and Revenue Hypergrowth
SiFive — Nov 18, 2019
ArchiTek Select SiFive and DTS-Insight To Enable Next-Generation AI Solution Development
Use of SiFive’s RISC-V Core IP Enables Low Power AI IoT Edge and End Point Devices
SiFive — Nov 12, 2019
Aerendir Mobile Inc. and SiFive Inc. Collaborate to Accelerate the Adoption of AI-Enabled Processors
Use of SiFive’s RISC-V Core IP Enables Low Power AI IoT Edge and End Point Devices
GLOBALFOUNDRIES (GF) — Nov 5, 2019
GLOBALFOUNDRIES and SiFive to Deliver Next Level of High Bandwidth Memory on 12LP Platform for AI Applications
Next generation high bandwidth memory solution based on GF’s most advanced FinFET platform aims to deliver capacity, speed and power for cloud based AI Applications
SiFive — Oct 24, 2019
SiFive Announces New U8-Series Core IP For High-Performance Compute
Linley Fall Processor Conference Presentation Details New SiFive IP For Automotive and IoT Edge Markets
SiFive — Oct 23, 2019
SiFive Announces New SiFive Shield For Modern SoC Design
Linley Fall Processor Conference Presentation Details New SiFive IP For Secure SoC Designs
SiFive — Oct 16, 2019
QuickLogic Teams with SiFive to Make eFPGA Technology Available via DesignShare Portfolio
Gives SoC designers an easy way to add post-manufacturing design flexibility Builds on previously announced strategic partnership and SoC template
SiFive — Oct 6, 2019
SiFive to Host RISC-V Tech Symposium and Workshop in Cairo on October 12, 2019
Mentor Graphics, a Siemens business; EITESAL NGO; the American University in Cairo. and Efabless are co hosting the RISC-V symposium & workshop
SiFive — Sep 30, 2019
SiFive Enables Embedded Vision With New DesignShare Partners
New Partnerships Add Key IP For Efficient Embedded Vision SoC Designs
SiFive — Sep 24, 2019
SiFive Signs DTS INSIGHT as Official Distributor to Japan
DTS INSIGHT expands into Semiconductor Market with SiFive IP and tools
SiFive — Sep 23, 2019
SiFive Announces Key Enablement Of Trace And Debug
World Leading RISC-V IP Portfolio with integrated Instruction Trace Encoder
SiFive — Sep 16, 2019
SiFive to Present at Linley Fall Processor Conference
SiFive Keynote and Presentation detail new technology for Intelligence and Security
SiFive — Jul 1, 2019
SiFive Expands DesignShare IP Ecosystem to 20 Partner Companies
Signature third-party IP ecosystem allows low-cost, rapid prototyping and innovative IP licensing for AI, edge computing
ChipEstimate — Jun 18, 2019
Morse Micro Partners with SiFive to Host Tech Symposium on RISC-V in Sydney
Powerful and engaging one-day event fosters education and collaboration within the RISC-V ecosystem.
Qualcomm Ventures — Jun 7, 2019
Portfolio Watch: By Democratizing Custom Silicon, SiFive Is Igniting Global Innovation in the Semiconductor Industry and Beyond
What if anyone could afford to build customized chips? And what if it was as easy as pushing a button?
The Information — Jun 6, 2019
Qualcomm Backs Startup Taking On SoftBank-Owned Arm
An emerging open source chip design, called RISC-V, appears to be picking up steamin the tech industry, changing how companies make custom chips, and one of the technology’s leading startups is growing fast along with it
SiFive — Jun 6, 2019
SiFive Celebrates Historic 100 Design Win Milestone
Compelling Portfolio and Strategic Partnerships Propel RISC-V Leader into Hypergrowth
SiFive — Jun 3, 2019
Avatar Integrated Systems Partnership Strengthens SiFive Cloud-Based Design
LAS VEGAS, June 3, 2019 -- Design Automation Conference -- SiFive, the leading provider of commercial RISC-V processor IP, design platforms, and custom SoC solutions, announced today a new partnership with Avatar Integrated Systems, a leader in next-generation physical design solutions. The partnership enables SiFive to use Avatar's physical design implementation tools within the SiFive cloud design environment.
SiFive — May 14, 2019
PowerVR GPU and NNA available on SiFive platform
Imagination Technologies joins SiFive's DesignShare Ecosystem, Enabling RISC-V users to access industry-leading IP
SiFive — May 1, 2019
SiFive Expands into Silicon Forest With new Development Office in Beaverton, Oregon
Metropolitan Portland area has evolved into an international center of open source hardware development
SiFive — Apr 25, 2019
SiFive Announces Strategic Partnership with QuickLogic and Launches SoC Templates for Rapid Chip Design
RISC-V pioneer and ultra-low power leader bring Freedom Aware SoC Templates to market
SiFive — Apr 10, 2019
SiFive Launches the World’s Smallest Commercial 64-bit Embedded Core
RISC-V Leader brings unmatched advanced 64-bit Core IP capability to embedded space
SiFive — Apr 9, 2019
Synaptics Selects and Designs SiFive Custom E2 Series Core IP in Record Time
Human interface solutions leader uses SiFive Core Designer to configure embedded processor in two months
SiFive — Apr 8, 2019
SiFive to Present at Leading IP, Processor Conferences
Executives to discuss new business models, optimizing RISC-V based processors and customizing architectures for AI implementations at Design and Reuse IP-SOC day and Linley Group events
SiFive — Feb 28, 2019
SiFive Welcomes Former Intel Capital VP to Executive Team
Hiren Majmudar joins RISC-V leader to head business development efforts
SiFive — Dec 11, 2018
SiFive Recognized as Most Respected Private Semiconductor Company
RISC-V leader honored for its products, growth and performance by Global Semiconductor Alliance
SiFive — Dec 11, 2018
SiFive Recognized as Most Respected Private Semiconductor Company
RISC-V leader honored for its products, growth and performance by Global Semiconductor Alliance
SiFive — Dec 4, 2018
SiFive Announces Multiple Technical Advances at RISC-V Summit
SiFive leads RISC-V ecosystem at inaugural summit with range of cores, RISC-V silicon, proof points, demonstrations, partnerships, talks and panels
Rambus — Dec 3, 2018
Media Alert: Rambus to Demo CryptoManager Root of Trust at the RISC-V Summit in Santa Clara
At the RISC-V Summit, Rambus is demonstrating our programmable root of trust core that provides secure processing based on the RISC-V architecture and incorporating industry-leading hardware security and anti-tamper capabilities. The Rambus CryptoManager Root of Trust is designed for applications from networking to automotive to IoT.
SiFive — Nov 16, 2018
SiFive Appoints VP of SoC IP to Lead Innovative IP Ecosystem
Mohit Gupta will oversee the rapidly expanding DesignShare program
Linley Group — Nov 12, 2018
SiFive Raises RISC-V Performance
Series 7 Comprises First Superscalar RISC-V CPUs
SiFive — Oct 31, 2018
SiFive Core IP 7 Series Creates New Class of Embedded Intelligent Devices Powered by RISC-V
Newly unveiled features and continued RISC-V investment in domain-specific architectures enable innovations in 5G, networking, storage, artificial intelligence and sensor fusion
SiFive — Aug 20, 2018
SiFive Announces First Open-Source RISC-V-Based SoC Platform with Nvidia Deep Learning Accelerator Technology
Cupertino, Calif. – August 20, 2018 – SiFive, the leading provider of commercial RISC-V processor IP, today announced the first open-source RISC-V-based SoC platform for edge inference applications based on NVIDIA's Deep Learning Accelerator (NVDLA) technology.
SiFive — Aug 14, 2018
OPENEDGES Joins SiFive’s DesignShare
SAN MATEO, Calif. – Aug. 14, 2018 – SiFive, the leading provider of commercial RISC-V processor IP, today announced a new member to its growing DesignShare economy: OPENEDGES, a provider of IPs for smart computing. The partnership makes available OPENEDGES’ ORBITTM Memory Controller IP to system developers via DesignShare, which enables customers incorporate world-class IP into their prototypes without having to pay for IP costs upfront.
SiFive — Aug 7, 2018
FADU Launches Industry Leading SSD Solutions Powered by SiFive RISC-V Core IP
SAN MATEO, Calif. and SANTA CLARA, Calif. – August 7, 2018 – SiFive, the leading provider of commercial RISC-V processor IP, and FADU, a fabless company developing solutions and systems for the memory and storage market, today announced the availability of FADU’s Annapurna SSD Controller and FADU Bravo Series Enterprise SSD, powered by SiFive’s industry leading 64-bit, E51 multicore RISC-V Core IP.
SiFive — Aug 7, 2018
eSilicon Licenses Industry-Leading SiFive E2 Core IP for Next-Generation SerDes IP
SAN MATEO, Calif. and SAN JOSE, Calif. – August 7, 2018 – SiFive, the leading provider of commercial RISC-V processor IP, and eSilicon, an independent provider of FinFET-class ASICs, market-specific IP platforms and advanced 2.5D packaging solutions, today announced that, after extensive review and testing of available options in the market, eSilicon has selected the SiFive E2 Core IP Series as the best solution for its next-generation SerDes IP at 7nm.
SiFive — Jun 25, 2018
SiFive Unveils E2 Core IP Series for Smallest, Lowest Power RISC-V Designs
San Mateo, Calif. – June 25, 2018 – SiFive, the leading provider of commercial RISC-V processor IP, today announced the availability of its E2 Core IP Series, configurable low-area, low-power microcontroller (MCU) cores designed for use in embedded devices. The E2 Series extends SiFive’s product line with two new standard cores, the E21, which provides mainstream performance for MCUs, sensor fusion, minion cores and smart IoT markets; and the E20, the most power-efficient SiFive standard core designed for microcontrollers, IoT, analog mixed signal and finite state machine applications. Additionally, the company announced enhancements to its existing standard E3 and E5 Core IP Series.
SiFive — May 17, 2018
SiFive Inc. and Andes Technology Corporation Join Forces to Promote RISC-V
Shanghai and San Mateo, Calif. – May 17, 2018 – Andes Technology Corporation, the prominent CPU IP provider, and SiFive Inc., the leading provider of ASIC design service and RISC-V CPU Core IP, have announced they are joining forces to jointly promote RISC-V. The two companies will each contribute their unique expertise in CPU development and support to expand the ecosystem for the RISC-V instruction set architecture (ISA) to enable a new era of processor innovation through open standard collaboration.
SiFive — May 15, 2018
SiFive to Hold Inaugural Technical Symposium in Shanghai
SAN MATEO, Calif. – May 15, 2018
SiFive — May 8, 2018
SiFive Challenge Calls for RISC-V Hardware Innovations
SAN MATEO, Calif. – May 8, 2018 – SiFive, the leading provider of commercial RISC-V processor IP, today opened the call for partnership applications for the Democratizing Ideas partnership initiative, which aims to support new, innovative ideas from academia, research institutions, students and the open source community based on the company’s Freedom Unleashed or Freedom Everywhere platforms. Announced at the RISC-V Workshop in Barcelona, the initiative is designed to further the company’s mission to democratize access to custom silicon to anyone who wants it.
SiFive — May 2, 2018
SiFive To Discuss Latest Technology Developments at RISC-V Workshop
SAN MATEO, Calif. – May 2, 2018 –
SiFive — Apr 12, 2018
Dover Microsystems Brings Secure Silicon IP to DesignShare
SAN MATEO, Calif. – April 12, 2018 – SiFive, the leading provider of commercial RISC-V processor IP, today announced that Dover Microsystems, a cybersecurity solutions provider, is the latest vendor to join the DesignShare ecosystem.
Data Center Knowledge — Apr 7, 2018
RISC-V Silicon Startup Raises $50.6 Million and Inks Western Digital Deal
This week saw another indication that open source hardware is ready to seriously vie for a slice of the enterprise IT pie. On Monday the major company behind the open source RISC-V processor, SiFive, reported it had raised $50.6 million in a Series C funding round, bringing total funding to $64.1 million.
Electronic Design — Apr 5, 2018
SiFive Raises $50.6 Million to Recreate Chip Prototyping
The RISC-V architecture is making an impression. That was reflected Monday in the announcement of $50.6 million raised by SiFive, a semiconductor startup that has been leveraging the free and open source architecture to reduce the cost and manpower required for chip development.
SiFive — Apr 2, 2018
SiFive Secures $50.6 Million Funding to Advance RISC-V Based Semiconductors
SAN FRANCISCO – April 2, 2018 – SiFive, the leading provider of commercial RISC-V processor IP, today announced it raised $50.6 million in a Series C round led by existing investors Sutter Hill Ventures, Spark Capital and Osage University Partners alongside new investor Chengwei Capital, and strategic investors including Huami, SK Telecom and Western Digital and other companies that are among the most respected and iconic companies in the industry. This Series C round brings the total investment in SiFive to $64.1 million. Additionally, the company also announced it has signed a multi-year license to its Freedom Platform with Western Digital, which has pledged to produce 1 billion RISC-V cores.
VentureBeat — Apr 2, 2018
SiFive raises $50.6 million for licensable custom microprocessors
SiFive has raised $50.6 million in a third round of funding to further its ambition to create a new licensing model for the semiconductor industry. San Francisco-based SiFive wants to democratize access to custom silicon chip designs. The company’s founders invented RISC-V, a free and open instruction set architecture for modern microprocessors. SiFive is taking that architecture and making it easy to design the custom variants that companies need.
Sensors Online — Feb 27, 2018
Moore’s Law is Dead: So, Let’s Talk About the Future of SoCs
By now, you’ve likely heard someone tell you: Moore’s Law is dead. To be sure, it is worthwhile to point out that the design aspect of Moore’s Law is – in most circumstances – very much alive. There are still techniques to be discovered to make the transistors smaller, for them to work faster, and to still put more of them in the same footprint. Rather, it is the economics behind Moore’s Law that has clearly reached its endpoint. Chips might continue to get smaller and faster. But if the economics mean that almost no one can afford to buy them, where exactly are we headed?
Design News — Feb 15, 2018
First Open-Source RISC-V SoC for Linux Released
Only months after debuting the Freedom U540, the world's first Linux-compatible processor based on the open-source RISC-V chip architecture, RISC-V chipmaker SiFive has surprised the open-source community again by unveiling a full development board built around the ISA.
Data Center Knowledge — Feb 13, 2018
Is Open Source RISC-V Ready to Take on Intel, AMD, and ARM in the Data Center?
While software is eating the world, open source hardware might soon be eating the data center. Definitely not tomorrow or next month, and probably not even next year, but sooner than you think, there might be as much open source hardware as the old-fashioned proprietary kind running data centers. Need proof? Take a look at RISC-V, an open processor architecture.
SiFive — Feb 7, 2018
SiFive Launches World’s First Linux-Capable RISC-V Based SoC
SAN MATEO, Calif. – Feb. 7, 2018 – SiFive, the leading provider of commercial RISC-V processor IP, launched the industry’s first Linux-capable RISC-V based processor SoC. The company demonstrated the first real-world use of the HiFive Unleashed board featuring the Freedom U540 SoC, based on its U54-MC Core IP, at the FOSDEM open source developer conference on Saturday.
Tech Republic — Feb 5, 2018
HiFive Unleashed: The first Linux-capable RISC-V single board computer is here
For low-power and embedded purposes RISC-V, an ISA developed principally by researchers at UC Berkeley with significant outside contributions, is gaining popularity. While early RISC-V devices have been intended for embedded applications and IoT devices, SiFive has released the first RISC-V SoC (Freedom U540) and SBC (Hi-Five Unleashed) which are powerful enough to run Linux distributions.
FOSDEM 2018 — Feb 3, 2018
Interview with Palmer Dabbelt: Igniting the Open Hardware Ecosystem with RISC-V. SiFive's Freedom U500 is the World's First Linux-capable Open Source SoC Platform
Palmer Dabbelt will give a talk about Igniting the Open Hardware Ecosystem with RISC-V. SiFive's Freedom U500 is the World's First Linux-capable Open Source SoC Platform at FOSDEM 2018.
EE Journal — Jan 16, 2018
The Bisquick Alternative
“Our vision is to enable two guys in a garage to build a custom chip.” Thus spake Jack Kang, Vice President of SiFive, the 40-person startup making RISC-V chips. SiFive isn’t just another company pulling the RISC-V bandwagon. They’re trying to change the way we create SoCs. The au courant open-source processor design is just a means to that end.
Microsemi — Dec 6, 2017
SiFive Joins Microsemi's New Mi-V Ecosystem to Accelerate Adoption of RISC-V Open Instruction Set Architecture
Microsemi Corporation (Nasdaq: MSCC), a leading provider of semiconductor solutions differentiated by power, security, reliability and performance, today announced SiFive, the first fabless provider of customized, open-source-enabled semiconductors, has joined Microsemi's new Mi-V™ RISC-V ecosystem, further building out the growing ecosystem and expanding the number of RISC-V designs users can consider. Microsemi will leverage its strategic relationship with SiFive and other ecosystem participants to increase adoption of RISC-V open instruction set architecture (ISA) central processing units (CPUs) and maximize their leadership positions with this expanding design technology.
Forbes — Dec 5, 2017
Western Digital Gives A Billion Unit Boost To Open Source RISC-V CPU
Western Digital is known for its storage products. What many do not realize is that the company ships over 1 billion processor cores within its products each year and is moving toward 2 billion per year. At the workshop, Western Digital CTO Martin Fink announced that over the next few years those billion plus processors will be transitioned over to RISC-V.
SiFive — Nov 7, 2017
SiFive and eMemory Bring Embedded Memory to the DesignShare Economy to Accelerate Development of RISC-V Silicon
SAN MATEO, Calif. – Nov. 7, 2017 – SiFive, the first fabless provider of customized, open-source-enabled semiconductors, today announced the addition of eMemory, the IP provider of logic-based, non-volatile memory (Logic NVM), to the DesignShare economy. eMemory will make its embedded NVM silicon IP technology available for the SiFive RISC-V based Freedom platform as part of the DesignShare initiative.
SemiWiki — Nov 7, 2017
DesignShare is all About Enabling Design Wins!
One of the barriers to silicon success has always been design costs, especially if you are an emerging company or targeting an emerging market such as IoT. Today design start costs are dominated by IP which is paid at the start of the project and that is after costly IP evaluations and other IP verification and integration challenges. Given that, reducing design costs and enabling design starts has always been a major industry focus starting with the fabless semiconductor transformation that began 30 years ago, which brings us to the DesignShare announcement made by SiFive and Flex Logix last week.
SemiAccurate — Nov 1, 2017
FlexLogix joins SiFive’s DesignShare program
SiFive and FlexLogix have teamed up to offer embedded FPGAs in the DesignShare development program. This is the third IP vendor that SemiAccurate knows of to join that program and it is an interesting idea. SiFive’s DesignShare program is unique in it’s aim to lower the barriers of entry for companies interested in making silicon.
SiFive — Oct 31, 2017
Flex Logix to Provide Embedded FPGA IP to 'DesignShare' for SiFive Freedom Platform
SAN MATEO AND MOUNTAIN VIEW, Calif. – Oct. 31, 2017 – SiFive, the first fabless provider of customized, open-source-enabled semiconductors, and Flex Logix™, a leader in embedded FPGA IP and software, today announced they will partner to make Flex Logix EFLX® embedded FPGA available for the SiFive Freedom Platform as part of the DesignShare program. The availability of Flex Logix IP through DesignShare eases time to market and removes traditional barriers to entry that have blocked smaller companies from developing custom silicon.
SiFive — Oct 24, 2017
Lauterbach and SiFive Bring TRACE32 Support for High-Performance RISC-V Cores
HÖHENKIRCHEN-SIEGERTSBRUNN, Germany, and SAN MATEO, Calif. – Oct. 24, 2017 – Lauterbach, the leading manufacturer of microprocessor development tools, and SiFive, the first fabless provider of customized, open-source-enabled semiconductors, today announced the availability of Lauterbach’s TRACE32 toolset to provide debug capabilities for SiFive’s E31 and E51 RISC-V Core IP, based on the free and open RISC-V ISA. Lauterbach support for SiFive cores is the latest addition to the growing ecosystem of industry-leading development tools to become available for RISC-V based silicon.
eeNews Europe — Oct 9, 2017
SiFive launches Linux-ready RISC-V quad-core processor
The Coreplex U54-MC contains four U54 CPUs and a single E51 CPU and is the first Coreplex processor core to offer multicore support and support for cache coherence. The U54 cores support the RV64GC ISA with a five-stage, in-order pipeline ALU. The 64bit E51 CPU serves as a management core and is fully coherent with the U54 cores. The U54-MC Coreplex is ideal for applications which need full operating system support such as AI, machine learning, networking, gateways, and smart IoT devices.
Electronics Weekly — Oct 9, 2017
64bit quad-core RISC-V for Linux
RISC-V is a free and open instruction set architecture [ISA] designed to enable chips across the full spectrum of computing devices, from embedded devices to the data centre,” said the firm. “The release of the U54-MC Coreplex marks the architecture’s expansion into the application processor space – opening entirely new use cases for RISC-V. It is ideal for applications which need full operating system support such as AI, machine learning, networking, gateways and smart IoT devices.
Fossbytes — Oct 8, 2017
Linux Gets Its First Multi-Core, RISC-V Based Open Source Processor
Last year, Silicon Valley Startup SiFive released the first open source SoC (system on a chip), which was named Freeform Everywhere 310. Now, going one step ahead from the embedded systems, the company has released U54-MC Coreplex IP, which is the world’s first RISC-V based 64-bit quad-core CPU that supports fully featured operating systems like Linux.
Fudzilla — Oct 8, 2017
2018 will be the year of the RISC V Linux processors
Linux fanboys tend to announce a lot of “year of” events. There is the year of the desktop which appears to be every year and still never happens and now there is the year of RISC V Linux processor. SiFive has declared that 2018 will be the year of RISC V Linux processor, so mark your penguin diaries accordingly. In the UK there will be all sorts of events planned, including guess the weight of Linus Torvalds competitions, there will be penguin tossing at Slough.
Mention — Oct 5, 2017
The Week In Review: Design
SiFive launched U54-MC Coreplex IP, a RISC-V based, 64-bit, quadcore real-time capable application processor with support for full featured operating systems such as Linux. The cores utilize a five-stage in-order pipeline, support the RV64GC ISA and cache coherence. It is targeted at AI, machine learning, networking, gateways and smart IoT devices.
Design News — Oct 5, 2017
Linux Now Has its First Open Source RISC-V Processor
When it released its first open-source system on a chip, the Freeform Everywhere 310, last year, Silicon Valley startup SiFive was aiming to push the RISC-V ("risk five") architecture to transform the hardware industry in the way that Linux transformed the software industry. Now the company has delivered further on that promise with the release of the U54-MC Coreplex , the first RISC-V-based chip that supports Linux, Unix, and FreeBSD.
SiFive — Oct 4, 2017
SiFive Launches First RISC-V Based CPU Core with Linux Support
SAN MATEO, Calif. – Oct. 4, 2017 – SiFive, the first fabless provider of customized, open-source-enabled semiconductors, today announced the availability of U54-MC Coreplex IP, the industry’s first RISC-V based, 64-bit, quadcore real-time capable application processor with support for full featured operating systems such as Linux. The free and open RISC-V architecture, which is supported by an ecosystem comprising more than 70 companies, has seen tremendous growth in the embedded segment. The release of the U54-MC Coreplex marks the architecture’s expansion into the application processor space – opening entirely new use cases for RISC-V.
LinuxGizmos.com — Oct 3, 2017
SiFive Unleashes the First Linux-Ready, 64-Bit RISC-V SoC
SiFive has taped out the first multi-core RISC-V based processor design, and the first to run Linux, featuring 4x 1.5GHz "U54" cores and a management core. SiFive announced "early access" availability of the 64-bit, quad-core U54-MC Coreplex – the first Linux-ready application processor built around the open source RISC-V architecture.
Electronic Design — Oct 3, 2017
SiFive's RISC-V Goes Multicore
The RISC-V universe just got a little bigger with SiFive’s 1.5 GHz U54-MC Coreplex (Fig. 1). The four U54 cores implement RV64GC that includes support for hardware multiple and divide, atomic instructions, 16-bit compressed instructions, and single and double precision floating point support.
EE Times — Oct 3, 2017
RISC-V Boots Linux at SiFive
SiFive has taped out and started licensing its U54-MC Coreplex, its first RISC-V IP designed to run Linux. The design lags the performance of a comparable ARM Cortex-A53 but shows progress creating a commercial market for the open-source instruction set architecture.
Hackaday — Oct 3, 2017
SiFive Announces RISC-V SoC
At the Linley Processor Conference today, SiFive, the semiconductor company building chips around the Open RISC-V instruction set has announced the availability of a quadcore processor that runs Linux. We’ve seen RISC-V implementations before, and SiFive has already released silicon-based on the RISC-V ISA. These implementations are rather small, though, and this is the first implementation designed for more than simple embedded devices.
SiFive — Aug 21, 2017
SiFive and Rambus to Provide IP to the 'DesignShare' Economy
SAN MATEO, Calif. – August 21, 2017 – SiFive, the first fabless provider of customized, open-source-enabled semiconductors, today announced it will partner with Rambus, (NASDAQ: RMBS), a leader in digital security, semiconductor and IP products and services, to make Rambus cryptography technology available for the SiFive Freedom platforms. To speed time to market and remove the barriers that traditionally have blocked smaller players from developing custom silicon, leading companies in the semiconductor ecosystem have developed a new DesignShare concept, which offers IP at a reduced cost.
SiFive — Aug 15, 2017
SiFive Appoints Naveed Sherwani as CEO
SAN FRANCISCO – August 15, 2017 – SiFive, the first fabless provider of customized, open-source-enabled semiconductors, today announced that industry veteran Naveed Sherwani has joined the company as CEO to lead it through its next phase of growth. Stefan Dyckerhoff, who had held the top spot at the company since its inception, will remain a member of the SiFive board of directors.
CPU Shack Museum — Jun 4, 2017
SiFive FE310: Setting The RISC Free
It is out of this that SiFive began. SiFive was founded by the creators of the first commercially successful open RISC architecture, known as RISC-V. RISC-V was developed at Berkeley, fittingly, in 2010 and was designed to be a truly useful, general purpose RISC processor, easy to design with, easy to code for, and with enough features to be commercially useful, not limited to the classroom. It is called the RISC-V because it is the fifth RISC design developed at Berkeley, RISC I and RISC II being designed in 1981, followed by SOAR (Smalltalk On A RISC) in 1984 and SPUR (Symbolic Processing Using RISC) in 1988. RISC-V has already proved to be a success, it is licensed freely, and in a way (BSD license) that allows products that use it to be either open, or proprietary. One of the more well known users is Nvidia, which announced they are replacing their own proprietary FALCON processors (used in their GPUs and Tegra processors) with RISC-V. Samsung, Qualcomm, and others are already using RISC-V. These cores are often so deeply embedded that their existence goes without mention, but they are there, working in the background to make whatever tech needs to work, work.
SiFive — May 19, 2017
SiFive Unveils the first RISC-V-based Arduino Board at Maker Faire Bay Area
SAN FRANCISCO – May 19, 2017 – SiFive, the first fabless provider of customized, open-source-enabled RISC-V semiconductors, today announced the release of the Arduino Cinque, the first RISC-V-based development board for the popular open-source hardware platform. Today’s announcement marks the latest development in SiFive’s work to democratize access to custom silicon.
EEFocus — May 17, 2017
开源是当今最热门的话题之一，也是未来的趋势，就像1998年时任微软CEO的鲍尔默痛斥Linux是癌症，而如今的CEO 却称“Microsoft love Linux”，因为开源“以人为本”，然而开源的商业化是一条必行却又难行的路。
如今的处理器、SoC基本被x86与ARM 这样封闭的指令集架构（ISA）所统治。所以谁能成为微处理器中的 Linux ，成为业界探讨与期待的事情。而目前RISC-V成为最受关注的对象。
EEWorld — May 9, 2017
由免费开源RISC-V指令集架构发明者创建的企业SiFive于今日在上海参加RISC-V基金会主办，NVIDIA和上海交通大学联合承办的第六届RISC-V技术研讨会，首次在中国与到会的200余名国内外顶尖学者和企业共同分享RISC-V指令集和其相关前景应用。作为首家基于免费开源RISC-V指令集架构的定制半导体公司，SiFive还在研讨会上分享了公司的最新进展 – SiFive即将推出目前访问RISC-V内核最快捷也最简单的方式 – Coreplex IP产品。随着RISC-V生态系统的快速发展，SiFive Coreplex IP设计已成为RISC-V内核的实际领导者，拥有比任何其他RISC-V架构厂商更多的客户群、硅产品和开发板。另外，SiFive还提供了简易的“调研-评估-购买”(Study – Evaluate – Buy)的采购流程，帮助工程师们迅速获得实用的Coreplex IP RTL源代码。
SiFive — May 8, 2017
SiFive Secures $8.5 Million Series B Funding to Advance RISC-V Based Semiconductors
SAN FRANCISCO – May 8, 2017 – SiFive, the first fabless provider of customized, open-source-enabled semiconductors, today announced it has raised $8.5 million in a Series B round led by Spark Capital with participation from Osage University Partners and existing investor Sutter Hill Ventures. This Series B round brings the total investment in SiFive to $13.5 million. The funding comes as SiFive experiences a growing demand for RISC-V IP and increased interest in custom silicon.
Electronic Design — May 8, 2017
A Patient Disciple of RISC-V, SiFive Starts Selling Cores
Last year, SiFive went fishing for engineers willing to test out chips based on the RISC-V instruction set, releasing a basic core called Rocket that anyone could download and modify. But now the company, whose founders invented RISC-V, is using richer bait for more ambitious customers.
Last week, SiFive started selling two embedded cores under the brand Coreplex, with applications ranging from wearables to servers. The company is aiming to lower the bar for engineers trained on Intel or ARM instruction sets to take RISC-V for a spin, when few companies appear to be turned off by the inflexibility or licensing fees of rival technology.
谁是目标 (via 百家号) — May 8, 2017
SiliconAngle — May 7, 2017
SiFive raises $8.5M to build low-cost custom chips
SiFive Inc. wants to give businesses access to custom-designed silicon chips at an affordable price, and today the San Francisco-based semiconductor startup announced that ii has closed an $8.5 million Series B funding round.
The round was led by Spark Capital, and it also included participation from Osage University Partners and existing investor Sutter Hill Ventures. SiFive’s Series B round brings the startup’s total investments to date to $13.5 million.
LinuxGizmos — May 7, 2017
Design your own RISC-V SoC with SiFive’s new “hassle-free” process
This week, SiFive announced a new “study-evaluate-buy” purchase process, that lets developers “get their hands on Coreplex IP RTL in a matter of minutes.” The immediately downloadable E31 Coreplex and E51 Coreplex IP RTL is described as “fully synthesizable and verified soft IP implementations that scale across multiple design nodes, making them ideal for your next SoC design.” On its Coreplex IP evaluation web page, SiFive describes the IP evaluation and purchase as being fast, NDA-free, and with a pricing model that is not based on royalties.
VentureBeat — May 7, 2017
SiFive raises $8.5 million for licensable custom microprocessors
SiFive is pioneering a new model in the semiconductor business and to do so has raised $8.5 million in a second round of funding, led by Spark Capital.
San Francisco-based SiFive is on a mission to democratize access to custom silicon chip designs. The company’s founders invented RISC-V, a free and open instruction set architecture for modern microprocessors. It consists of all of the software instructions needed to program a microprocessor based on the RISC-V architecture. And SiFive is taking that architecture and making it easy to design the custom variants that companies need.
SiFive — May 4, 2017
SiFive Launches CPU IP Industry into the Cloud with New RISC-V Cores and an Easy Online Business Model
SAN FRANCISCO – May 4, 2017 – SiFive, the company founded by the inventors of the free and open RISC-V instruction set architecture (ISA), today announced the immediate availability of its Coreplex IP, the fastest and easiest way to license RISC-V cores. With the rapid growth in the RISC-V ecosystem, SiFive Coreplex IP designs have become the de facto leader for RISC-V cores, with more public customers, silicon and development boards than any other RISC-V vendor. SiFive’s hassle-free “study-evaluate-buy” purchase process means that designers can get their hands on Coreplex IP RTL in a matter of minutes.
CIO — May 3, 2017
Open-source chip mimics Linux's path to take on closed x86, ARM CPUs
A startup called SiFive is the first to make a business out of the RISC-V architecture. The company is also the first to convert the RISC-V instruction set architecture into actual silicon. The company on Thursday announced it has created two new chip designs that can be licensed.
Make — May 2, 2017
SiFive Is Bringing Open Source to the Chip Level
There has been an upswell of interest in custom, open hardware among makers, in which community-developed and shared designs abound. The availability of low-cost development boards such as Arduino and Raspberry Pi, together with open source software, has made it easier to get started with making innovative, new hardware designs.
Hackaday — Apr 13, 2017
Open Source Chip Design Hack Chat Transcript
Come hang out for 30 or so minutes and talk to Jack Kang, VP of Product and Business Development at SiFive. Join this chat to learn about RISC-V, the free and open Instruction Set. Ask questions about what it means to have open-source chips, and how SiFive plans to help everybody—from the smallest company, inventor, and maker, get access to custom silicon.
Sidense — Mar 8, 2017
Customer Corner: SiFive's Freedom Everywhere 310 (FE310) SoC Alternative
SiFive is the first fabless provider of customized, open-source-enabled semiconductors. The RISC-V ISA has been central to our vision of enabling a whole new range of applications for everyone. In November 2016, we announced the availability of the Freedom Everywhere 310 (FE310) SoC, the industry's first commercially available chip based on RISC-V. Bringing the first commercially available SoC based on the RISC-V ISA is a huge milestone for the open-source hardware community.
Cadence — Jan 22, 2017
RISC-V "The thing that you learn and the thing that you use are the same"
The SiFive business model is that lots of people are locked out of silicon. SiFive can do custom design and deliver chips. "We believe we can do it cheaper, quicker and more predictably than anyone else.” They have also been getting lots of calls to help with designs. Growing the RISC-V ecosystem is a big opportunity.
The traditional semiconductor business models take a lot of resources, so you have to pick the winners. But there aren't any $1B sockets anymore, so you can't easily pick the winners. The market is fragmented. SiFive wants to give everyone a chance. In a bit more detail, they will do a customer microcontroller platform and deliver 100 or so chips for under $100K.
Micro-Electronics (Taiwanese Publication) — Jan 11, 2017
Hackaday — Jan 4, 2017
Hands On With The First Open Source Microcontroller
2016 was a great year for Open Hardware. The Open Source Hardware Association released their certification program, and late in the year, a few silicon wizards met in Mountain View to show off the latest happenings in the RISC-V instruction set architecture.
We’ve seen a lot of RISC-V stuff in recent months, from OnChip’s Open-V, and now the HiFive 1 from SiFive. The folks at SiFive offered to give me a look at the HiFive 1, so here it is, the first hands-on with the first Open Hardware microcontroller.
InfoWorld — Jan 4, 2017
SiFive rolls out fully open source chip for IoT devices
In an interview, Jack Kang, VP of Product and Business Development at SiFive, discusses the FE310 chip, which will allow IoT vendors to build their own custom SoC on top of it
SiFive is a relatively new fabless chip manufacturing startup that is developing fully open source chips. Its new FE310 chip is its first chip (and apparently the first open source chip) targeted at IoT devices.
SemiEngineering — Jan 3, 2017
SiFive: Low-Cost Custom Silicon
One of the lessons learned years ago in the open-source Linux world is that free software isn’t always good enough. Consequently, being able to add commercial value around freeware can turn into a lucrative business.
Enter SiFive, a startup that has been building customized platforms based on the RISC-V CPU. Started by the creators of the RISC V instruction set architecture (ISA), the company’s stated goal is to shake up the economics of the chip industry.
Design News — Dec 15, 2016
SiFive Is Setting Silicon Free with Open-Source Chips
Moore's Law is dead...just not in the way everyone thinks. Technological advances keep allowing chips to scale, but the economics are another story – particularly for smaller companies that can't afford chips in the volumes that the big chipmakers would like from their customers.
The solution, according to San Francisco-based startup, SiFive, is open-source hardware, specifically an architecture developed by the company's founders called RISC-V (pronounced “risk-five”). Done right SiFive, which was awarded Startup of the Year at the 2016 Creativity in Electronics (ACE) Awards, believes that RISC-V will do for the hardware industry what Linux has done for software.
Design News — Dec 7, 2016
UBM Announces 2016 ACE Award Winners
The best and brightest were on display last night as UBM announced the 2016 Annual Creativity in Electronics (ACE) Awards winners during a ceremony held in conjunction with ESC Silicon Valley and BIOMEDevice San Jose. The awards, presented in partnership with EETimes and EDN, showcase the best in today’s electronics industry, including the hottest new products, start-ups, design teams, executives, and more.
All About Circuits — Dec 6, 2016
Open Source RISC-V Architecture Makes Strides Towards Customizable SoCs
The RISC-V footprint is expanding with the commercial availability of open-source chips and related development boards from silicon startups like SiFive and OnChip.
The open-source hardware movement's journey from academia to the commercial realm is finally gaining some momentum. This is in large part thanks to free RISC-V instruction set architecture (ISA), which was developed at the University of California, Berkeley a few years ago.
Cadence — Dec 5, 2016
RISC-V Available in Silicon
One of the announcements at the recent RISC-V workshop was by SiFive. This is the company started by the creators of the RISC-V instruction set architecture (Krste, Andrew, and Yunsup) to commercialize silicon implementations.
Four months ago, at the previous RISC-V workshop, they announced FPGA implementations of the two flavors, Freedom Everywhere (16-bit microcontroller) and Freedom Unleashed (64-bit multi-core, high performance). They also announced that silicon would be coming "soon."
Well, it is now "soon."
Electronic Design — Dec 4, 2016
Will RISC-V Rescue the Internet of Things?
In a nutshell, RISC-V is an instruction set architecture (ISA) that scales from 16-bit to 128-bit register platforms. The E310 is targets the Cortex-M0 space, but it can run at 320 MHz while sipping power—making it an interesting solution for the Internet of Things (IoT). The chip is available on the HiFive1 board ... that has an Arduino form factor.
VentureBeat — Nov 28, 2016
SiFive Launches Open Source RISC-V Custom Chip
SiFive wants to democratize the custom chip business, and so today it is launching the industry’s first open-source RISC-V system-on-chip processor. The Freedom Everywhere 310 SoC and HiFive1 development board will enable a wide variety of system architects, embedded designers, and Internet of Things providers — people who normally have to rely on chip engineers for the detailed engineering work — to create their own products.
Hackaday — Nov 28, 2016
HiFive1: RISC-V In An Arduino Form Factor
The RISC-V ISA has seen an uptick in popularity as of late — almost as if there’s a conference going on right now — thanks to the fact that this instruction set is big-O Open. This openness allows anyone to build their own software and hardware. Of course, getting your hands on a RISC-V chip has until now, been a bit difficult. You could always go over to opencores, grab some VHDL, and run a RISC-V chip on an FPGA. Last week, OnChip released the RISC-V Open-V in real, tangible silicon.
EE Times — Nov 28, 2016
Open Source SoC Debuts
Startup SiFive started selling today a $59 Arduino board running its first RISC-V-based SoC and made open source RTL code available online for the chip. The news marks a milestone for a still nascent open source hardware movement.
Open source cores have been available previously but they tended to be academic efforts or lacked broad commercial support. The HiFive board is intended to drive demand for custom SoCs SiFive will design and comes with a growing pool of open source Linux variants and tools fed by an expanding foundation that maintains the RISC-V instruction set.
PR Newswire — Nov 15, 2016
Microsemi is First FPGA Provider to Offer Open Architecture RISC‑V IP Core and Comprehensive Software Solution for Embedded Designs
Microsemi's new RV32IM RISC-V core, developed in collaboration with SiFive, enables customers to design with an open instruction set architecture (ISA), enabling complete portability and a more secure processor architecture governed by a permissive BSD license. RISC-V is a new ISA which is now a standard open architecture under the governance of the RISC-V Foundation. RISC-V offers a compelling soft processor solution for Microsemi's low power, reliable, secure FPGAs.
SemiWiki — Oct 2, 2016
SiFive execs share ideas on their RISC-V strategy
Since its formation just last year, SiFive has been riding the RISC-V rocket from purely academic interest to first commercialization. In an exclusive discussion, I talked with CEO Stefan Dyckerhoff and VP of Product and Business Development Jack Kang about their progress so far and what may be coming next.
New Electronics — Sep 26, 2016
Back to the future for RISC
In their 2014 technical report for the University of California at Berkeley, Krste Asanovic and Professor David Patterson – who developed the concepts behind the SPARC architecture in the 1980s – argued that, while there are good commercial reasons for processor makers to maintain proprietary instruction sets, there is no good technical reason for users to adopt them. Their proposal was for an instruction set architecture (ISA) offered on a similar basis to open source software that could stimulate an ecosystem similar to that built around Linux.
As their proposal represented the fifth generation of RISC processor design, it was called RISC-V.
Linux Pro Magazine — Sep 20, 2016
Creating the free-licensed semiconductor market
As many would-be open hardware manufacturers have discovered, free-licensed computer chips are nearly non-existent. However, SiFive, a recently announced startup in San Francisco, is hoping to change that with its custom chip designs. SiFive has its origins in the RISC-V instruction set architecture (ISA) developed in the Computer Science Division of the Electrical Engineering and Computer Science Department at the University of California, Berkeley.
EE Times — Sep 18, 2016
EE Times Silicon 60: 2016’s Emerging Companies to Watch
It has been a year since EE Times produced a version16.1 of the Silicon 60. Over that time while the global economic situation can — at best — be said to have stabilized the semiconductor and electronics industries are on the edge of "great expectations.” There seems no doubt that the Internet of Things will have a revolutionary impact on how people can live their lives, but exactly how that will manifest itself in terms of components, software, platforms, legal and business models, is not yet clear nor is the next big thing.
Xilinx — Sep 7, 2016
Itching to Play With the Open-Source RISC-V Processor? Here Are Three Xilinx-Based Kits to Start With
RISC-V (pronounced “risk five”) is an open, 32/64-bit RISC microprocessor architecture first developed at the Computer Science Division of the EECS Department at the U. of California, Berkeley. Now it’s managed by the RISC-V Foundation. If you are an aficionado of processor architectures and you’re looking to get your feet wet with the RISC-V architecture, SiFive has released three Freedom FPGA Platforms based on Xilinx All Programmable devices that allow you to start working with the RISC-V ISA immediately.
Cadence — Sep 6, 2016
SiFive: A RISC-V Fabless Semiconductor Company
A couple of weeks ago I talked to Krste Asanović and Jack Kang of SiFive. One of their motivations is to bring the cost reduction that goes along with open-source software (and instruction sets!) to the hardware world. There is an increasing move in this direction as companies like Facebook, IBM, and Google put parts of their server infrastructure into the public domain. This is especially important in semiconductors since Moore's law has run into a wall, at least economically, even though we have a couple more process generations coming at us.
Cadence — Sep 1, 2016
RISC-V Gathering Momentum
A week or so ago I talked to Krste Asanović, who is the UC Berkeley professor who led the project to define RISC-V, chairman of the RISC-V foundation, and in July co-founded a fabless semiconductor company, SiFive, to produce silicon implementations (and IP). I'll talk about SiFive in Breakfast Bytes one day next week. RISC-V has taken off strongly in academic circles due to its unrestricted availability compared to other instruction sets, which are often not really ideal for academic work, and/or come with legal encumbrance.
Pinestream Consulting Group — Aug 15, 2016
SiFive – Freedom Family of RISC-V ISA-Based SoC Platforms
SiFive recently unveiled its flagship Freedom family of SoC platforms. Built around the RISC-V ISA invented by the company’s founders at the University of California, Berkeley, the Freedom U500 and Freedom E300 platforms represent a new approach to designing and producing SoCs that redefines traditional silicon business models and reverses prohibitively rising licensing, design and implementation costs.
EE Journal — Aug 10, 2016
Custom Silicon for Makers
Makers are the epitome of what big chip vendors used to consider a waste of time for their valuable salesfolk. “Fred in the shed,” as they said. No volume, no ROI. “Stick with Tier 1s.”
Electronics Lab — Aug 2, 2016
An Open-Source SoCs with RISC-V From SiFive
SiFive, a startup from San Francisco, is trying to democratize the access to the world of SoC designing and manufacturing by giving the ability of customizing silicon to the smallest company, inventor, or maker, and taking “the hard parts of building chips working with 3rd part IP, EDA tools and foundries. SiFive is a fabless semiconductor company building customizable SoCs. SiFive takes benefits from using RISC-V in their SoC design. Some of inventors of the open source ISA RISC-V are behind SiFive.
CIO — Aug 2, 2016
Why the Time Is Right for Open Source to Meet Hardware
SiFive is a San Francisco-based fabless chip manufacturing startup that is developing the first fully open source chips. The company, which launched earlier this month, announced two chips of their flagship platform: Freedom U500 and Freedom E300, each targeting different audience.
IOT-DEV.net — Jul 25, 2016
SiFive More News
As many of you may already know, SiFive is the first company that will make open source ISA Risc-V SoCs. What will be open and what not ? This was main question that people ask. In this video they answered that they will open as much as they can.PCI-E 3 controllers and some other 3-d party stuff will remain closed. They said time to develop some controllers and other 3d party tools and all to be open sourced will take ~ another 2 years of work.
Electronics Products — Jul 21, 2016
SiFive Introduces E300 & U500 Open-Source Chip Platforms
SiFive has introduced the Freedom family of open-source SoC-platform intellectual property based on the RISC-V instruction set architecture. The company offers the Freedom U500 and Freedom E300 processing platforms that are a new approach to designing and producing SoCs in that they are based on open-source and extensible architecture with no licensing fees.
Elektor Magazine — Jul 18, 2016
California Dreaming: DIY, Open-Source SoCs With RISC-V
With its customizable, open-source SoCs built on the free and open RISC-V instruction set architecture, SiFive, a San Francisco start-up, is poised to reverse the industry’s rising licensing, design and implementation costs. System designers can use the SiFive Freedom platforms to focus on their own differentiated processor without having the overhead of developing a modern SoC, fabric or software infrastructure.
ModernLife Network — Jul 18, 2016
SiFive, STEM and Apple Reality TV
SiFive, a new Silicon Valley startup, is teaming up with RISC-V Foundation and the infrastructure set to develop open source chip products. Two chips are in development – Freedom Unleashed (designed for machine learning, storage and networking) and Freedom Everywhere (designed for low-power devices in the “Internet of Things” market). SiFive is trying to drive down the cost of chip manufacturing, open the industry up to designers and engineers, and squeeze into an industry that has several barriers of entry.
AnandTech — Jul 17, 2016
SiFive Unveils Freedom Platforms for RISC-V-Based Semi-Custom Chips
SiFive, a company established by researchers who invented the RISC-V instruction set architecture in the University of California Berkeley several years ago, has this week announced two platforms which could be used to design semi-custom SoCs based on RISC-V cores.
Linux Insider — Jul 12, 2016
SiFive Launches Freedom FOSS SoC Platforms
SiFive on Monday announced its flagship Freedom family of system on a chip platforms. The platforms are based on the free and open source RISC-V instruction set architecture that several of the company's founders created at the University of California at Berkeley. SiFive's Freedom U500 and E300 platforms take a new approach to SoCs, redefining traditional silicon business models and reversing the industry's increasingly high licensing, design and implementation costs.
HPCwire — Jul 12, 2016
RISC-V Startup Aims to Democratize Silicon
Momentum for open source hardware made a significant step this week with the launch of startup SiFive and its open source chip platforms based on the RISC-V instruction set architecture. The founders of the fabless semiconductor company — Krste Asanovic, Andrew Waterman, and Yunsup Lee — invented the free and open RISC-V ISA at the University of California, Berkeley, six years ago.
SiFive — Jul 11, 2016
SiFive Introduces Industry’s First Open-Source Chip Platforms
SAN FRANCISCO – July 11, 2016 – SiFive, the first fabless semiconductor company to build customized, open-source enabled semiconductors, today announced its flagship Freedom family of system on a chip (SoC) platforms. Built around the free and open RISC-V instruction set architecture invented by the company’s founders at the University of California, Berkeley, SiFive’s Freedom U500 and Freedom E300 platforms represent a fundamentally new approach to designing and producing SoCs that redefines traditional silicon business models and reverses the industry’s prohibitively rising licensing, design and implementation costs.
Rambus — Jul 11, 2016
SiFive Eyes Silicon Reset With RISC-V
A San Francisco-based startup known as SiFive has announced plans to develop and sell chips based on open-source RISC-V architecture. According to Don Clark of the Wall Street Journal, the tech includes a set of instructions that define the functions of a microprocessor, which can serve as a starting point for designing a chip.
Product Design and Development — Jul 11, 2016
Startup Releases Open Source System-on-Chip
Fabless semiconductor company SiFive has announced a new system on a chip platform that takes the SoC platform into the realm of open-source. The RISC-V instruction set architecture was originally developed by SiFive’s founders at the University of California, Berkeley, and has now been packaged into the Freedom U500 and Freedom E300 platforms.
Linux Magazine — Jul 11, 2016
SiFive Launches a Line of Open Source Chips
A San Francisco-based company known as SiFive is trying to bring the open source development model to the chip industry. The company has announced its first Freedom family of system-on-a-chip (SoC) products, including the Freedom U500 and Freedom E300 platforms. SiFive is a fabless semiconductor company, similar to AMD. The company doesn’t fabricate the chip but outsources it to manufacturers.
Journal Dunet (French Publication) — Jul 11, 2016
L'Américain SiFive se lance dans la conception de puces open source
Un groupe de chercheurs de l'Université de Californie lançait en avril dernier une fondation visant à porter un projet d'architecture de processeur open source (le projet RISC-V). Ces chercheurs passent maintenant à la vitesse supérieure : ils lancent une entreprise, baptisée SiFive, visant à commercialiser leur technologie. SiFive doit développer des puces reposant sur l'architecture open source RISC-V.
IOT-DEV.net — Jul 11, 2016
SiFive Comes with World First U500 and U300 Open Source RISC-V SoCs
SiFive will publish specifications for an SoC based high-performance Unix-capable cache-coherent 64-bit multiprocessor U500 and one using a microcontroller core E300 both based on work of the RISC-V Foundation. The U500 platform is the first member of SiFive's Freedom Unleashed family of customizable RISC-VSoCs. Freedom Un-leashed family reduces NRE and time-to-market for customized SoCs in diverse markets such as machine learning, storage and networking.
HackerBoards — Jul 11, 2016
First SoCs Based on Open Source RISC-V Run Linux
SiFive unveiled the first embedded SoCs based on the open source RISC-V platform: A Linux-ready octa-core Freedom U500 and a FreeRTOS-based Freedom E300. A VC-backed startup closely associated with the RISC-V project announced the first system-on-chip implementations of the open source RISC-V processor platform.
Electronics Weekly — Jul 11, 2016
SiFive brings open-source SoCs
It has developed customizable, open-source SoCs built on the free and open RISC-V instruction set architecture. “The semiconductor industry is at an important crossroads. Moore’s Law has ended, and the traditional economic model of chip building no longer works,” said Yunsup Lee, co-founder of SiFive and one of the original creators of RISC-V at UC Berkeley.
CNXSoft — Jul 11, 2016
SiFive Introduces Freedom U500 and E500 Open Source RISC-V SoCs
SiFive, a startup founded by the creators of the free and open RISC-V architecture, has announced two open source SoCs with Freedom U500 processor and Freedom E300 micro-controller. Three real-time operating systems, including FreeRTOS, have already been ported to Freedom E300 for embedded micro-controllers, IoT, and wearable markets.
The Next Platform — Jul 10, 2016
Startup Takes a Risk on RISC-V Custom Silicon
As we are carefully watching here, there is a perfect storm brewing in the semiconductor space, both for manufacturers and system designers.
SemiAccurate — Jul 10, 2016
SiFive Opens Up Silicon Access With Freedom E300 and U500
SiFive is unveiling two open source RISC-V based platforms today called the Freedom U500 and E300 Series. SemiAccurate thinks what SiFive is doing has a good chance of changing how the silicon market works.
EE Times — Jul 10, 2016
Startup Debuts Open Source SoCs
A startup aims to help a broader set of engineers roll their own silicon using its customizable open-source systems-on-chips. SiFive will publish specifications for an SoC based on an embedded Linux processor core and one using a microcontroller core both based on work of the RISC-V Foundation.
eWEEK — Jul 10, 2016
Startup SiFive Aims for Open-Source Chips
The open-source RISC-V chip architecture was created to help developers more easily and cheaply customize processors that run their devices, and last year an industry consortium was formed around the technology. Now the inventors of RISC-V want to see if they can build a business based on the architecture.
SemiWiki — Jul 10, 2016
RISC-V opens for business with SiFive Freedom
When we talk about open source, free usually comes in the context of “freedom”, not as in “free beer”, and open IP often serves as a base layer of value add for commercialization. The creators of the RISC-V instruction set, now working at startup SiFive, have released specifications for their aptly-named Freedom processor IP cores looking for "enablement of great ideas".
Forbes — Jul 10, 2016
This New Chip Startup Wants To Bring Open Source To A Stagnant Industry
Open source has taken off in the software world. RISC-V maybe has the opportunity to bring open source to the rigid chip industry. Born out of university research, RISC-V is a chip architecture that lets developers freely change and customize chip designs without having to pay for expensive licenses or royalty fees.
Wall Street Journal — Jul 10, 2016
Backers of Open Source Chips Launch Startup
A group of university researchers recently attracted attention by applying principles of open-source software to computer chips. Now they’re turning the concept into a company. A San Francisco-based startup called SiFive on Monday is announcing plans to develop and sell chips based on a technology called RISC-V. The tech includes a set of instructions that define the functions of a microprocessor, which can serve as a starting point for designing a chip.
SemiEngineering — Jun 29, 2016
Will Open-Source Work For Chips?
Open source is getting a second look by the semiconductor industry, driven by the high cost of design at complex nodes along with fragmentation in end markets, which increasingly means that one size or approach no longer fits all.
Cadence Blogs — Jun 16, 2016
RISC-V—Instruction Sets Want to Be Free
I had never heard of RISC-V (pronounced five, not vee) until earlier this year when there was a presentation about it at EDPS in Monterey. I immediately texted the daughter of a friend of mine who is a CS major at Berkeley where it originated and she gave me a bit more background.
SemiEngineering — Jun 6, 2016
Alternative To X86, Arm Architectures?
Software developed by professors and graduate students from the University of California at Berkeley? That will never fly in the semiconductor industry, right?
Next Platform — May 15, 2016
Can Open Source Hardware Crack Semiconductor Industry Economics?
The running joke is that when a headline begs a question, the answer is, quite simply, “No.” However, when the question is multi-layered, wrought with dependencies that stretch across an entire supply chain, user bases, and device range, and across companies in the throes of their own economic and production uncertainties, a much more nuanced answer is required.
Linley Group — Mar 31, 2016
RISC-V Offers Simple, Modular ISA
RISC-V is a new general-purpose instruction-set architecture (ISA) that’s BSD licensed, extensible, and royalty free. It’s clean and modular with a 32-, 64-, or 128-bit integer base and various optional extensions (e.g., floating point). RISC-V is easier to implement than some alternatives—minimal RISC-V cores are roughly half the size of equivalent ARM cores—and the ISA has already gathered some support from the semiconductor industry.
Next Platform — Mar 7, 2016
RISC-V Inching Closer to Reality at Scale
Back in the early 1990s, the common view was that there was little money to be made in the business of open source. As the wave of Linux distributions rolled forth, however, that was quickly disproven, setting the decades-long chain of companies that have secured their footing, funding, and futures on the back of open software.
XDA Developers — Jan 7, 2016
Open Source RISC-V Core Designs, Why Google Cares and Why They Matter
EE Times — Aug 6, 2014
RISC-V: An Open Standard for SoCs
Just as Linux has become the standard OS for most computing devices, Berkeley researchers envision RISC-V becoming the standard ISA for all computing...