SiFive vectors. Optimized for the modern workload.

RISC‑V Vector solutions built for data-driven applications

Data driven applications increasingly require multiple cores combined in ways that can create complex and inefficient environments. Layering in capabilities like AI, ML, or computer vision introduces challenges like managing power consumption, extra data movement, the need for multiple libraries, and issues with generational incompatibility. To solve these obstacles, many of the world’s largest data and device companies are turning to SiFive vector processing based on the RISC‑V Vector (RVV) 1.0 ISA.

Built on a trusted RISC‑V standard foundation, and supported by a robust, growing ecosystem, SiFive solutions offer an easy-to-program, more efficient environment. The ability to utilize different vector lengths with the same software code offers scalability and flexibility. Reduced software complexity and eliminating the need for multiple accelerators or DSPs is also a big advantage, bringing significant power reductions and greater efficiency. SiFive market leading vector solutions, such as the SiFive® Intelligence™ X280 processor, enable the creation of a unified, more efficient, and easier to program design, allowing you to add your own differentiation to your product to better target demanding market requirements.

Introduction to SiFive Vector Processors

A short vector processor tutorial

SiFive - The Market Leader In RISC‑V Vectors

Top-tier customers see growing vector benefits

10 Important Things To Know About SiFive Vectors

Quick review of the advantages of vector processing

Introduction To The SiFive Intelligence X280

Solutions for demanding vector applications

SiFive's RISC-V Leadership Strengthens with New Vector Solutions

Exciting SiFive® Intelligence™ X280 Momentum

Introducing the Latest SiFive® Intelligence™ X280 Processor Innovation - the Vector Coprocessor Interface Extension (VCIX)

SiFive VCIX is a vector instruction-mapped interface, enabling a direct connection between the X280 vector ALU to a custom accelerator, allowing custom vector instructions to be executed on the accelerator from the vector pipeline.

The Past, Present and Future of RISC-V

A wide ranging overview of RISC-V and SiFive in this video featuring the Founder, Krste Asanovich