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Graham Wilson, Director Product Marketing—March 30, 2021
SiFive Core IP 21G1
The best just got better--SiFive’s latest Processor Core IP Portfolio release
We’re pleased to announce a comprehensive update to SiFive’s RISC-V Core IP Portfolio with the SiFive 21G1 release. This release brings important enhancements and new capabilities to SiFive® Core IP, the industry's broadest RISC-V IP Portfolio, ranging from the ultra-capable SiFive U7-Series to the extremely popular SiFive E2-Series, offering up to 35% more performance for bit processing algorithms; and up to 25% smaller code size. For a deep dive into the details of this exciting release, register to watch the webinar on-demand.
Improved Performance for IoT and AI Applications
There are several key enhancements to SiFive Core IP in the 21G1 release to improve computation throughput, not only through ISA and architecture, but also processor interface connectivity. The SiFive 2-Series and 7-Series processors are now available with the RISC-V “Bit Manipulation” extension, RV32B, with Zba and Zbb extensions. This gives much higher performance in bit processing algorithms, for example Cryptographic Hash algorithm can be accelerated by 35%.
SiFive processors previously supported double and single precision floating point computation. In the 21G1 release, half precision floating point (FP16) has been added for a more complete floating point computation support. This has been added based on customer needs to reduce memory size and power consumption of floating point computation, as well as use in AI algorithm computation, which uses FP16 extensively.
Flexibility in SoC Hardware and Software Integration
This latest release improves SoC implementation of SiFive processors giving more flexibility and options in software programming and hardware connectivity. The organization of the memory map is now fully programmable, where SoC architects can set memory and block positioning to support legacy code or application specific requirements.
For the U5 Series and U7 Series products (RV64 application processors), virtual addressing up to 48-bits and physical addressing up to 47-bits is supported with the new Sv48 option. This greatly extends the addressing range, allowing the SiFive cores to be easily integrated into large system designs with huge memory requirements.
In the release, a new ultra low latency, high-bandwidth, interface is added to the 7-series processors, called the Core Local Port. This port is a dedicated interface for each processor, offering direct connectivity. High performance, time critical hardware blocks can be connected directly to the processor, giving low latency throughput, fully deterministic operation for time critical computation. In line with this, SiFive processors now support the new proposed RISC-V NMI specification, for mission critical applications.
Higher Performance, Smaller Code size
With the new computation features and data type support in this 21G1 release, high performance is achieved. However a key requirement from SiFive customers is reduction of code size, memory requirements, hence cost. As a result, SiFive has focused on improved libraries and toolchain support. A new and greatly improved C-library that has been fully integrated into the toolchain and SDK allows designers to easily achieve optimum performance, while reducing code size by up to 25% (compared to the previous 20G1 release).
The processor enhancements in this release increase benchmark performance to 5.18 CoreMarks/MHz and 2.63 Dhrystone/MHz for 7-series processors.
Improved Trace, Debug and Security
SiFive Insight is the industry’s first pre-integrated debug and trace IP for RISC-V processor cores, enabling faster silicon bring-up, software/hardware integration, and application development. The Hardware Crypto Accelerator component already within SiFive processors (SiFive Shield) has been further extended with the addition of Public key accelerator (HCA-PKA).
Uniquely, SiFive Insight features native Arm® CoreSight™ compatibility. By seamlessly integrating with Arm® CoreSight™, developers can integrate SiFive RISC-V based cores into mixed ISA designs and maintain their existing development environment. SiFive Insight has broad industry support from leading software companies such as Green Hills Software, IAR Systems, Lauterbach, SEGGER, with SiFive Freedom Studio free tools also available.
With this release, the Trace capability has been greatly enhanced with a variety of new capabilities. The type of tracing (history or branch) is now selectable, as well as the number of communication channels and trace buffer size. The History Trace Messages (HTM) offers 5x compression capability that is recommended for High-Performance multi-core implementations where large amounts of trace data is generated.
SiFive’s Best Portfolio Is Here
The SiFive 21G1 release offers new advanced computation capability with bit manipulation packages, half precision floating point, as well as code size reduction by up to 25%. SoC integration in terms of hardware and software has been optimized for more efficient computation, smaller size and faster time to market.
By using SiFive’s latest release of Core IP, defining and adopting a high-performance, high-efficiency, secure RISC-V processor for your next application or real-time SoC has never been more attractive. Save time and effort with SiFive’s unique support for Arm CoreSight to minimize workflow disruption, and broad tool ecosystem support for SiFive Insight Advanced Trace and Debug.
We can’t wait to engage with customers on the incredible new devices they’ll build using the substantial new capabilities of the faster, more efficient, more capable than ever SiFive Core IP portfolio.
(1) – 35% improved performance for bit manipulation computation algorithms based on SiFive internal engineering measurement of cryptographic hash function (nettle-sha256) running on a SiFive U7-Series (21G1) processor core.
(2) – 25% smaller code size with update tools and C-libraries with 21G1 release, in comparison to same toolchain release in 20G1 release. The 25% is the best, largest amount of code size savings.
(3) – Support for Half precision floating point for a wide range of applications including AI algorithm computation.
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