The Next Leap in Datacenter AI: Orchestrating Custom Accelerators with SiFive Intelligent Control Units (ACUs)

How programmable RISC-V solutions optimize, control and direct custom accelerator functionality, unlocking the next generation of AI performance with SiFive intelligent control.

As agentic AI, multimodal models, and real-time inference expand across data center and edge systems, workloads are becoming more complex, diverse and demanding. These demands are driving compute architects toward specialized custom accelerators that deliver performance and efficiency for targeted operations, such as matrix multiplication. They still must be configured, fed, synchronized, monitored, and supported by software beyond their datapaths.

"Traditional" Accelerator Control has Limits

Traditional methods and designs create a design challenge. The datacenter system level processor remains essential for system level orchestration, but routing every low level control decision through it consumes resources, increases complexity and adds latency.

Hardwired local control, such as dedicated system bus, mapped control registers, and Direct Memory Access (DMA), provides efficient, deterministic sequencing, but is typically a custom proprietary solution and is difficult to adapt for any needed future modification requirements as algorithms, data formats, and system requirements change. Traditional custom accelerator control architectures suffer from:

• Rigid, Fixed Functionality: Hardwired state machines mean that if an algorithm changes or a bug is found, you are often looking at costly hardware respins.
• Shared Bus Bottlenecks: Frequent data movements across common shared buses introduce unacceptable latency and stall memory execution pipelines.
• High Host CPU Overhead: Forcing the primary processor to manage complex orchestration limits overall system performance and efficiency.

To build the next generation of datacenter AI infrastructure, we need a paradigm shift. We must move away from fixed state machines. Augmenting or increasing the system level processor capabilities, load and associated data infrastructure is not the answer.

The answer is to add a programmable control and compute layer close to the custom accelerator, offloading the system level processor. This layer manages low latency command dispatch, data movement, pre/post processing, and workload/algorithm modifications, while complementing the system level processor and directly optimizing the specialized custom accelerator engine(s).

Enter the SiFive Intelligence Series Accelerator Control Units (ACUs)

To address this challenge, SiFive has developed its SiFive Intelligence Family compute engines to be the ideal Accelerator Control Unit (ACU), combining programmable RISC-V scalar and vector compute with direct custom accelerator connectivity. Although the Intelligence compute IP can be a great edge inference engine on its own, these cores and core complexes have also been specifically designed to be the preferred solution to act as a dedicated, programmable RISC-V front end controller to command and control custom accelerators.

The SiFive ACU functions as an intelligent orchestration layer. By taking over task scheduling, resource allocation, command dispatches, and pre/post data formatting, the SiFive ACU offloads the host processor. This allows AI architects to focus entirely on designing their specialized AI custom accelerator engines, while a proven SiFive IP ACU solution handles the control, coordination, software programmability and supports ever evolving workloads.

By replacing legacy control with a SiFive Intelligence Series based ACU, datacenter architects immediately gain future proofing. Because the ACU is built on a programmable RISC-V core, updates and bug fixes can be deployed via simple software and firmware patching rather than expensive hardware cycles. Furthermore, our open standard 100% RISC-V ISA and RVA23.1 (RTOS, Linux) compatibility taps directly into a rich, industry software ecosystem, dramatically reducing time-to-market.

• Programmable RISC-V Controller: Acts as a flexible frontend controller to manage custom AI accelerators.
• Host Processor Offloading: Handles scheduling, dispatches, and data formatting, freeing or replacing the primary host CPU (including running Linux).
• Software-Driven Adaptability: Enables easy updates via firmware patches while leveraging the open RISC-V software ecosystem for faster time to market.

Overcoming the Data Movement Wall with SSCI, VCIX, and CLP

In AI hardware design, attempting to handle both low latency engine control and massive high bandwidth data transfers over a single shared bus is a recipe for performance degradation. SiFive solves this by using three industry leading, direct pipeline interfaces to create a synchronized orchestration workflow:

• Vector ACU/Coprocessor Interface (VCIX): Designed to keep heavy compute engines constantly fed, VCIX provides a high bandwidth direct interface to the SiFIve Intelligence core vector registers. It can rapidly stream packed tensor and matrix datasets straight into the custom hardware accelerator at core clock frequency.
• SiFive Scalar ACU/Coprocessor Interface (SSCI): Designed for low-latency control, SSCI connects directly into the SiFive scalar CPU execution pipeline. It keeps the custom accelerator engine responsive by dispatching custom scalar instructions, handling data-dependent decisions, and reading/writing control registers with single-cycle or ultra-low-latency round trips.
• Core Local Port (CLP): When the AI core requires bypass-level speed, the CLP offers a high bandwidth, low latency path directly to local or customer RAM bypassing the L2 subsystem entirely.

In practice, this enables well orchestrated AI workflows across different IP and memory hierarchies. The SiFive ACU leverages its vector units and VCIX to rapidly preload weights or input tensors straight into the accelerator's local memory. Once staged, the scalar core dispatches a custom instruction via SSCI to trigger the matrix computation.

Most importantly, if your AI workload requires pre or post data formatting, Softmax, activation functions, or entirely new algorithms that the custom accelerator wasn't originally designed to handle, the SiFive Intelligence core can simultaneously perform these functions.

Not Just for the Datacenter

While custom AI accelerators are heavily associated with cloud and datacenter workloads, ACUs, like the SiFive Intelligence Series, are engineered to span the entire spectrum of computing. From far edge IoT, automotive ADAS, physical AI and robotics, smart edge IoT, and consumer wearables like AR/VR headsets and other battery powered devices, the ACU provides many solutions and flexibility.

Here is Why the ACU extends Far Beyond the Datacenter:

• Power & Thermal Constraints at the Edge: Datacenters have megawatts of power, but edge devices operate on strict thermal and power budgets. An ACU manages power states, schedules tasks efficiently, and prevents energy hungry custom accelerators from idling while waiting on host instructions.
• Deterministic, Real-Time Latency: Applications like robotics and autonomous vehicles require instant responsiveness. Using an ACU as a low latency, dedicated front end controller ensures predictable command dispatch without waiting on a heavy host OS.
• Standalone Host Capability: Smaller SiFive ACU cores can run real time operating systems (RTOS) using Tightly Coupled Memory (TCM/SRAM), while higher end cores feature a full MMU capable of running Linux directly. This allows the ACU to completely replace the host processor, drastically saving die area, cost, and power in compact edge hardware. Physical AI & Sensor Fusion Coordination: Edge AI relies on heterogeneous compute (combining vision, audio, radar, and sensor data). The ACU acts as the orchestration layer that formats pre/post data and feeds specialized processing units in real time.

The ACU isn’t tied to datacenters. It’s a programmable RISC-V control layer for a custom accelerator, useful anywhere a system needs to manage accelerator work, move data, and reduce the main CPU’s low level workload. That can mean a compact embedded SoC just as well as a server.

Sizing the Right ACU for Your Datacenter Workload

There is no one-size-fits-all in custom silicon, which is why the SiFive Intelligence portfolio is built to scale based on control complexity, data movement bandwidth, and fallback compute needs . Sizing the right SiFive Intelligence core for an Accelerator Control Unit (ACU) solution depends on balancing three primary factors:

• Data Movement Bandwidth
• Control Complexity
• Ancillary/Fallback Compute Needs

The vector length (VLEN) and datapath width (DLEN) of the selected core determine both the data movement bandwidth available over coprocessor interfaces and the onboard computational capability of the ACU.

The X100 Series: Ideal for control heavy or efficient edge accelerators that primarily need instruction dispatches and status checks over SSCI. It provides minimal latency without wasting die area and can run on scalable Tightly Coupled Memory (TCM/SRAM) with an RTOS.

Case Study - Tier 1 US Semiconductor Company Licensed SiFive Intelligence X100 for Industrial Edge AI Applications.

The X200 & X300 Series: Designed for heavy data movement and significant fallback workloads. With wider VCIX datapaths (e.g., 256-bit, 512-bit, or 1024-bit VLEN), these cores can double or quadruple data transfer capacity to keep massive matrix engines busy, while providing a full MMU for a Linux environment.

Case Study - Google Datacenter, SiFive Intelligence X200 as AI Compute Host.

The Future of Custom Accelerator Hardware is Software

Optimizing custom accelerator control is no longer a secondary consideration, it is becoming a critical success factor for the AI era. The data throughput of the accelerator engine must be independent of the host processor, enabling custom engines to scale larger and process data faster to match ever increasing requirements.

The rapid evolution of artificial intelligence and high performance computing workloads demands an architecture that combines long term software stability with rapid hardware innovation. The RISC-V software ecosystem resolves the historical conflict between proprietary lockin and ecosystem fragmentation by establishing a standard software baseline that protects development investments while enabling domain specific acceleration and innovation.

Standards Base

• Compatibility and Portability: Provides a global standardized ISA and consistent extensions. The standardized RISC-V ISA provides a common foundation for operating systems (like Linux and RTOS), compilers (GCC and LLVM, development tools, and applications, enabling software reuse and portability across RISC-V implementations, without ecosystem fragmentation.

Open Ecosystem

• Collaboration and Choice: Powered by a collaborative community and global RISC-V ecosystem encourages innovation across hardware vendors, software developers, and industry partners, reducing vendor lock-in and accelerating the development of tools, open source compilers (such as LLVM), AI frameworks (including MLIR, ONNX Runtime, and TFLite), and solutions unencumbered by proprietary licensing fees.

Customized Innovation

• Flexibility and Differentiation: Designers can extend the standard RISC-V ISA with specialized instructions, vector/matrix extensions, and specialized accelerator control logic interfaces (such as SSCI and VCIX) using C compiler intrinsics to accelerate rapidly evolving AI, HPC, automotive, and embedded computing without breaking base software stack compatibility or losing affinity with standard development tools.

RISC-V combines the compatibility of a standardized architecture, the strength of an open ecosystem, and the freedom to innovate, enabling differentiated computing solutions without sacrificing a common software foundation.

The SiFive Intelligence Series ACU is built to drive this next wave of innovation. By combining the flexibility of RISC-V with unmatched connectivity, we are allowing system architects to focus on what they do best and provide the power to unleash their custom AI hardware, from the datacenter to edge, to direct consumer, and all points in between.

Ready to streamline your hardware integration, accelerate your design process and maximize system efficiency? Contact the SiFive sales team today to schedule an architecture review and explore how our Intelligence Series IP can accelerate your next datacenter or other AI technology breakthrough.