SiFive Blog

SiFive has developed its Intelligence Family compute engines to be the ideal Accelerator Control Unit (ACU) to work with customers' custom accelerators. Although the Intelligence compute IP can be a great edge inference engine on its own, these core and core complexes have also been specifically designed to be the ideal solution to act as a dedicated, programmable RISC-V front-end controller to command and control custom accelerators.

SiFive explains how Ratification of the SPMP specification is good news for embedded security.

SiFive makes available an open-source collection of highly-optimized computational routines for the RISC-V Vector ISA (RVV) and its various extensions, including SiFive’s matrix engines

I recently returned from the RISC-V Europe Summit 2026 in Bologna and, like many attendees, I came away energized by the announcements, the technical discussions and the sheer number of people building products around RISC-V.

SiFive is evolving the building blocks of RISC-V-based IP that are reimagining and democratizing every computing platform. We take a closer look at the new Performance P570 Gen 3 and its next-gen applications.

RISC-V is maturing fast, and the P570 Gen 3 is proof — here's what that means for the developers and system designers who've been waiting for it.