SiFive Blog

The latest insights, and deeper technology dives, from RISC-V leaders

The SiFive blog is your go-to-source for updates on all things RISC-V including processor IP, chip architecture, software and other innovations. Whether you’re producing the next great consumer device, optimizing a datacenter or building next-generation autos check back often to hear the latest from our experts.

Introducing SiFive Insight

Mar 17, 2020

Access, Observe, Control The term ‘debug’ has a storied history. It’s widely reported as being coined by computing pioneer, US Navy Rear Admiral Grace Hopper, when she removed a moth from Harvard’s Mark II computer in 1945. Use of the word bug can also be traced to the great inventor, Thomas Edison,...

The RISC-V Revolution is Going Strong in Ahmedabad

Mar 04, 2020

As part of our ongoing effort to spread knowledge about the RISC-V ISA around the globe, we hosted a two-day long RISC-V Symposium/Workshop in the ancient city of Ahmedabad, India. The event was co-hosted by Nirma University at their campus at Ahmedabad. The first day of the event was the symposium ...

Our SiFive Tech Symposiums in Costa Rica and Mexico Underscore the Global Adoption of the RISC-V ISA in Industry and Academia

Feb 29, 2020

Our SiFive Tech Symposiums in San José, Costa Rica and Mexico City, Mexico were well attended by not only those in industry, but in academia as well. There is a great deal of enthusiasm and engagement in RISC-V in both of these regions. Many new friendships were formed, and we look forward to the co...

Part 4: High-Performance Interconnect for Accelerators: Enabling Optimized Data Transfers with RISC-V

Feb 24, 2020

This is the fourth in a series of blogs about Domain-specific accelerators (DSAs), which are becoming increasingly common in systems-on-chip (SoCs). Parts 1, 2 and 3 addressed key challenges such as data transfers between DSAs and the core complex, point-to-point ordering between cores and DSA memor...

Part 3: High-Bandwidth Accelerator Access to Memory: Enabling Optimized Data Transfers with RISC-V

Jan 30, 2020

This is the third in a series of blogs about Domain-specific accelerators (DSAs), which are becoming increasingly common in system-on-chip (SoC) designs. Part #1 addressed the challenges associated with data transfers between DSAs and the core complex, and showed how RISC-V offers a unique opportuni...

Part 1: High-Bandwidth Accelerator Access to Memory: Enabling Optimized Data Transfers with RISC-V

Jan 30, 2020

Domain-specific accelerators (DSAs) are becoming increasingly common in system-on-chip (SoC) designs. A DSA provides higher performance per watt by optimizing the specialized function it implements. Examples of DSAs include compression/decompression units, random number generators and network packe...

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