Resources & Support
About Us

SiFive Blog

The latest insights, and deeper technology dives, from RISC-V leaders

September 12, 2017

The DesignShare Ecosystem Grows with the Addition of UltraSoC’s Embedded Analytics IP

It’s been a busy summer for us. Our days have been filled with many prospect, customer and partner meetings with teams looking to leverage RISC-V in their roadmap. Last week, we announced the outcome of one of those meetings: UltraSoC, a provider of on-chip monitoring and analytics IP, is the latest company to join the DesignShare movement.

If you missed our previous blog post, 'Our New Partnership with Rambus and the DesignShare Economy,' Designshare is a concept that enables an entirely new range of applications. Companies like SiFive, UltraSoC and Rambus have developed efficient, pre-integrated solutions that lower the upfront engineering expense required to bring custom silicon based on the SiFive Freedom platform to realization. We aim to do for open source hardware what the foundry model did to enable a new class of fabless semiconductor companies.

Through its participation in the DesignShare ecosystem, UltraSoC will provide IP that simplifies the development of SoCs and delivers embedded analytics features that enable chip makers to dramatically reduce development costs. Like SiFive, UltraSoC has been at the forefront of development of the RISC-V specification, especially in the area of processor trace functionality, which is a fundamental requirement for developers working with any processor architecture.

We’re excited to see the DesignShare ecosystem grow, and will have more exciting news to share with the community in the next few weeks. Stay tuned!

Learn more about SiFive and UltraSoC’s partnership.

Jack Kang
Jack Kang
SVP, WW Business Development, Sales, and Customer Experience (CX)

A member of the founding team at SiFive, Jack oversees the Business Development (BD), Customer Experience (CX), and Corporate Marketing groups at SiFive. He is responsible for strategic business initiatives and partnerships, technical pre-sales activities and post-sales support, and corporate messaging and campaigns at SiFive. Prior to SiFive, Jack held a variety of senior business development, product management, and product marketing roles at NVIDIA and Marvell with a long track record of successful, large-scale design wins. Jack received his BS degree in Electrical Engineering and Computer Science from UC Berkeley and has over 20 U.S. patents from his time as a CPU design engineer.

Read more Insights from the RISC-V Experts

The Next Leap in Datacenter AI: Orchestrating Custom Accelerators with SiFive Intelligent Control Units (ACUs)
Blog Post
The Next Leap in Datacenter AI: Orchestrating Custom Accelerators with SiFive Intelligent Control Units (ACUs)
SiFive has developed its Intelligence Family compute engines to be the ideal Accelerator Control Unit (ACU) to work with customers' custom accelerators. Although the Intelligence compute IP can be a great edge inference engine on its own, these core and core complexes have also been specifically designed to be the ideal solution to act as a dedicated, programmable RISC-V front-end controller to command and control custom accelerators.
SiFive Perspective: RISC-V SPMP Specification Ratification is a Leap Forward for Embedded Security
Blog Post
SiFive Perspective: RISC-V SPMP Specification Ratification is a Leap Forward for Embedded Security
SiFive explains how Ratification of the SPMP specification is good news for embedded security.
Introducing SKL: The SiFive Kernel Library
Blog Post
Introducing SKL: The SiFive Kernel Library
SiFive makes available an open-source collection of highly-optimized computational routines for the RISC-V Vector ISA (RVV) and its various extensions, including SiFive’s matrix engines