SiFive Blog

The heart of SiFive is RISC-V, the ISA invented by SiFive’s founders 5 years prior to starting the company! SiFive is evolving the building blocks of RISC-V-based IP that are reimagining and democratizing every computing platform. In technology, evolution is not merely a timeline of random changes. It is a well-planned ladder of interdependent milestones. Each step creates a new set of environmental conditions that make the next, more complex, leap inevitable. Winning requires flexibility and innovation to adapt. Both are core values of SiFive and RISC-V.

RISC-V is maturing fast, and the P570 Gen 3 is proof — here's what that means for the developers and system designers who've been waiting for it.

Today, we are proud to announce one of the most significant milestones in our journey: a $400M funding round led by Atreides Management with other A-list investors, valuing the company at $3.65 billion and will accelerate SiFive’s RISC-V CPU and AI IP solutions into the heart of the data center and AI infrastructure markets.

Learn how RISC-V code models work in modern toolchains. This guide explains medlow, medany, and the new large code model, including addressing modes, relocations, and linker behavior.

SiFive and NVIDIA announced a major milestone: we are working together to integrate NVIDIA NVLink Fusion into SiFive’s high-performance RISC-V data center solutions.

Discover how SiFive’s Intelligence X100 product family delivers advanced security for Edge AI systems. Learn how RISC-V–based architectures, WorldGuard isolation, and hardware cryptographic acceleration enable secure, real-time AI processing at the network edge—reducing latency, enhancing privacy, and protecting data across devices.