Formal Verification Engineer
As the pioneers who introduced RISC-V to the world, SiFive is transforming the future of compute by bringing the limitless potential of RISC-V to the highest performance and most data-intensive applications in the world. SiFive’s unrivaled compute platforms have enabled leading technology companies around the world to innovate, optimize, and deliver the most advanced solutions of tomorrow across every market segment of chip design, including artificial intelligence, machine learning, automotive, datacenter, mobile, and consumer. With SiFive, the future of RISC-V has no limits. For more information, please visit www.sifive.com.
We at SiFive are looking for a Formal Verification Engineer to join our growing team working on implementing a novel application of formal verification methodologies to parameterizable CPU IP generators. SiFive is looking for someone with outstanding knowledge and skills in formal verification who will build a formal environment to be used specifically with SiFive’s functional programming-based hardware design suite.
Location: The ideal candidate for this position can work out of one of our US offices or remotely from home, collaborating with the HQ in San Mateo, CA. However, all positions are currently remote until further notice.
- Leading the application of formal methodologies to parameterizable high-performance RISC-V CPU IP generators.
- Creating a reusable formal verification methodology library to be used in SiFive’s novel hardware design flow.
- Building a compiler-based hardware design suite that would automatically generate the appropriate test bench when given a parameterized instance of a chip design.
- Establishing through formal mathematical modeling or proofs the fidelity of given CPU IP blocks.
- Ensuring that CPU designs will meet given targets for power, performance, and area, by applying formal methods.
- Mentoring junior members of the team in the use of formal verification methodologies and tools.
- 7+ years of recent experience in formal verification and related tools (model checking, property verification, JasperGold, Hector DPV, and others) and methodologies.
- Knowledge of CPU or GPU architectures (floating point, load-store, branch prediction, out-of-order execution) and cache coherence protocols.
- Experience in functional verification, such as constrained random verification, test bench generation, etc.
- Fluency in hardware description languages such as Verilog, VHDL, or SystemVerilog.
- Knowledge of Register-Transfer Level circuitry (registers, combinatorial function blocks (e.g. adders and multiplexers), finite state machines.
- Knowledge of Traditional test bench environments - UVM, Verdi/DVE.
- Functional programming languages, such as Scala, Chisel, Haskell, etc.