Senior Engineer (STA/PD)

At Open-Silicon, a SiFive company, we design, develop and deliver advanced semiconductor solutions for a range of verticals and industries. We invented RISC-V, and our extensive line-up of best-in-class RISC-V processor cores has over 150 adoptees worldwide, including tier-1 semiconductor companies.  Our custom SoC division delivers ASICs in the most advanced technology nodes and enjoys close partnerships with all leading silicon foundries. We push the envelope on advanced ASICs for artificial intelligence and machine learning. Our ASICs are also seen in satellite communication systems, IoT and extreme low-power mobile devices.  We are leaders in high-speed networking and memory interface IP. With our expertise in package-silicon codesign, we belong to the technology elite that can deliver leading-edge products based on 2.5D interposer technology and 3D packaging. We have a global presence with multiple development centers in North America, Europe, China, Korea and India. Our design centers in India, located in Bangalore and Pune with additional sites under development, drive innovation and deliver solutions across our product portfolio. To support our growth and expansion plans, we are hiring across disciplines, including SoC architecture, analog design, logic design and verification, DFT, physical design, embedded software and board and system design.
Job Description:
(3-6 years of Experience)
-Should be a Hands on PD expert with through understanding  of timing closure
-Should be able to read a spec and write timing constraints  
-Should have experience in Full chip timing closure and should be able to define timing signoff criteria & timing closure strategy. 
-Should  be able to debug  is Placement, CTS and timing closure issues in PnR. 
-Should have good understanding on PPA optimization. 
-Experience in Spice simulation and 2.5D level system timing analysis and power analysis is a plus