SiFive Blog

I recently returned from the RISC-V Europe Summit 2026 in Bologna and, like many attendees, I came away energized by the announcements, the technical discussions and the sheer number of people building products around RISC-V.

SiFive is evolving the building blocks of RISC-V-based IP that are reimagining and democratizing every computing platform. We take a closer look at the new Performance P570 Gen 3 and its next-gen applications.

RISC-V is maturing fast, and the P570 Gen 3 is proof — here's what that means for the developers and system designers who've been waiting for it.

Today, we are proud to announce one of the most significant milestones in our journey: a $400M funding round led by Atreides Management with other A-list investors, valuing the company at $3.65 billion and will accelerate SiFive’s RISC-V CPU and AI IP solutions into the heart of the data center and AI infrastructure markets.

Learn how RISC-V code models work in modern toolchains. This guide explains medlow, medany, and the new large code model, including addressing modes, relocations, and linker behavior.

SiFive and NVIDIA announced a major milestone: we are working together to integrate NVIDIA NVLink Fusion into SiFive’s high-performance RISC-V data center solutions.