Senior CPU Design Verification Engineer
As the pioneers who introduced RISC-V to the world, SiFive is transforming the future of compute by bringing the limitless potential of RISC-V to the highest performance and most data-intensive applications in the world. SiFive’s unrivaled compute platforms have enabled leading technology companies around the world to innovate, optimize, and deliver the most advanced solutions of tomorrow across every market segment of chip design, including artificial intelligence, machine learning, automotive, datacenter, mobile, and consumer. With SiFive, the future of RISC-V has no limits. For more information, please visit www.sifive.com.
As a Design Verification Engineer, you will work with CPU designers, compiler team, performance team, and system verification team to generate the test cases automatically to fit those teams verification requirements in different perspectives. Your responsibilities will target establishing a random instruction test generator that produces self-checking direct test cases.
- Design, develop, documentation and deploy random instruction generator and support multiple projects.
- Support execution of the generator and flows in the RTL design process.
- Integrate and ramp up on an existing instruction level verification flows.
- Master’s or PhD degree in Electrical Engineering, Computer Science or equivalent practical experience.
- Familiar with CPU micro-architecture, memory sub-system and system software ( such as exception/interrupt handling, memory paging system.)
- Familiar with baremetal/system software programming and Experience with creating direct test cases or porting microbenchmarks to measure system power or performance for design verification.
- Basic understanding of Verilog, System-Verilog RTL, UVM and constrain random verification.
- Experience with software project architecture/design and python/C++11 above programming.