As the pioneers who introduced RISC-V to the world, SiFive is transforming the future of compute by bringing the limitless potential of RISC-V to the highest performance and most data-intensive applications in the world. SiFive’s unrivaled compute platforms have enabled leading technology companies around the world to innovate, optimize, and deliver the most advanced solutions of tomorrow across every market segment of chip design, including artificial intelligence, machine learning, automotive, datacenter, mobile, and consumer. With SiFive, the future of RISC-V has no limits. For more information, please visit www.sifive.com.
The SiFive Platform Engineering team is building an ambitious new infrastructure to support accelerated ASIC and FPGA design flows, IP delivery and SoC development - driving the next generation of SiFive's "Silicon at the speed of Software" mission. This infrastructure leverages state of the art compiler algorithms (built on open source MLIR and LLVM technologies), novel build system integration, and new Verilog RTL generation techniques.
Our team combines many different perspectives and experiences, and we love working with people who combine a passion for learning and growth with product focus, practical experience, and a desire to build world-changing technologies.
We encourage applicants from traditionally underrepresented groups in computer science to apply!
- Evolve, design and build new compiler intermediate representations for hardware design and tool flows.
- Implement specific compiler optimization and lowering algorithms for chip design flows.
- Implement state of the art mechanisms for hierarchical caching that crosscut compiler and build systems.
- Participate in design discussions, planning, code review, documentation, open source processes, and other standard software practices.
- Collaborate with hardware architects to develop the approach and design flows.
- Manage your individual project priorities, deadlines and deliverables.
- We are hiring for several positions with different levels of seniority, but require a minimum of 2 years of compiler engineering experience.
- Strong oral and written communication skills, excellent team collaboration.
- Experience with C++ programming and git-based development workflows.
- Experience with Verilog and other chip design technologies is NOT required.