PD and Automation Engineer
As the pioneers who introduced RISC-V to the world, SiFive is transforming the future of compute by bringing the limitless potential of RISC-V to the highest performance and most data-intensive applications in the world. SiFive’s unrivaled compute platforms have enabled leading technology companies around the world to innovate, optimize, and deliver the most advanced solutions of tomorrow across every market segment of chip design, including artificial intelligence, machine learning, automotive, datacenter, mobile, and consumer. With SiFive, the future of RISC-V has no limits. For more information, please visit www.sifive.com.
As a Physical Design Automation Engineer in the Implementation team, you will contribute to the development of industry-leading CPU IP to support the SiFive vision of enabling chip design by anyone. We are looking for people who are as excited as we are about working in a fast-paced dynamic environment to bring new hardware IP to market quickly, with high quality and exceptional performance.
- Develop automation to improve the productivity of Physical Design and RTL Engineers;
- Implement and optimize our broad portfolio of RISC-V CPU's from RTL to GDSII;
- Close aggressive performance, power, and area (PPA) goals at block and/or CPU level;
- Collaborate with the microarchitecture and RTL teams to optimize PPA trade off's.
- 7+ years of physical design and automation experience; Experience with CPU designs and advanced process nodes (16nm and below) is a plus
- TCL and Python scripting
- Experience in synthesis, DFT insertion, floor planning, place and route, clock tree synthesis, static timing, power analysis, and signal and power integrity
- Knowledge and skill in optimizing PPA through floor planning, placement and timing constraints, useful skew, and similar techniques
- Attention to detail and a focus on high-quality design
- Ability to work well with others and a belief that engineering is a team sport
- Bachelor’s degree in Electrical Engineering or Computer Engineering, Master’s preferred