Senior Design Verification Engineer
As the pioneers who introduced RISC-V to the world, SiFive is transforming the future of compute by bringing the limitless potential of RISC-V to the highest performance and most data-intensive applications in the world. SiFive’s unrivaled compute platforms have enabled leading technology companies around the world to innovate, optimize, and deliver the most advanced solutions of tomorrow across every market segment of chip design, including artificial intelligence, machine learning, automotive, datacenter, mobile, and consumer. With SiFive, the future of RISC-V has no limits. For more information, please visit www.sifive.com.
This verification position is a highly visible role, the simple purpose of which is to ensure the silicon works. What will you work on when you join our team? By its design philosophy, RISC-V is highly configurable, and we have several different configurations in our design pipeline, with various combinations of supported instruction set and with various peripherals and bus interconnect architectures. Implementing design verification methodologies that can accommodate such variation is a challenging task, to be addressed in this role.
- Architecting test methodologies applicable to a wide range of processor and SoC designs including memory virtualization (Paging and Hypervisors), various levels of caches and industry standard bus protocols (e.g., AMBA, TileLink, PCIe).
- Developing tools, test benches, and test suites (UVM, C++/C or otherwise, as needed) to execute test plans.
- Writing functional coverage, analyze both code and functional coverage, and close coverage holes.
- Developing and using unit level test benches that use constrained random stimulus.
- Writing directed assembly tests as appropriate to test CPU functions.
- Driving the execution of test suites and analyze test results, including RTL or higher-level debug of test failures
- Collaborating closely with the design team on feature specifications, test plans and failure analysis.
- Building test plans to implement these strategies, considering issues such as design feature priority, potential customer impact, coverage metrics generation and measurability, etc.
- A minimum of 5 years of recent experience with standard verification tools and methodologies (SystemVerification/UVM, Verdi/DVE, Verilog, Makefiles, scripting languages, etc.).
- Familiarity with and/or ability to learn languages and methodologies that are not part of the industry-standard approach to verification (Scala, Chisel, etc.).
- A conscientious and thorough approach to Design Verification.
- Solid understanding of processor and SoC architecture, or a strong desire and ability to learn the same.
- A thorough understanding of the high-level verification flow methodology (test plan generation, test generation, failure analysis, coverage analysis and closure).
- Good interpersonal skills to listen to diverse points of view and influence people from different disciplines.
- Ability to effectively assess the current state of a design’s verification posture, remaining state space to be covered, and efficient methods to achieve verification closure
- An unwavering dedication to product quality.