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SiFive is an idea-to-silicon company founded by the inventors of RISC-V to simplify the design and production of custom SoCs.
As the leading commercial provider of RISC-V processor IP, SiFive is on a mission to help engineers design custom chips for domain-specific solutions for many markets, including 5G, edge AI, enterprise networking, storage, and consumer devices.
Industry-leading innovators, including six of the top ten semiconductor companies, are working with SiFive thanks to our proven success, deep expertise, and rich partner ecosystem. With SiFive’s rich IP ecosystem and accessible design platform, every market has access to the development of workload-focused hardware needed to design next-generation products.
The Error Architect will be responsible for spearheading SiFive’s Error Architecture roadmap across multiple vertical markets. This is an exciting role that will give the candidate a chance for cross-functional leadership across the company and work with RISC-V International to standardize parts of the Error Architecture exposed to software.
- Creating the Error Architecture for cores and other SiFive IPs. Error Architecture is also referred to RAS (Reliability, Serviceability, and Availability) architecture outside of SiFive. The Error Architecture specifies how an IP handles errors and responds to them.
- Working on the RISC-V specifications of various aspects of the Error Architecture.
- Researching and analyzing emerging needs for new error architecture.
- The Error Architect will have a chance to analyze market verticals and design architectures specifically tailored for upcoming use cases in Automotive and Space computing.
- Working with customers to tailor the SiFive Error Architecture to their needs.
- Opportunity to work directly with customers (which include Fortune 500 companies as well as prominent, innovative startups) to brainstorm and troubleshoot the Error Architecture.
- 10+ years of experience in Error Architectures.
- Familiarity with advanced CPU architectures and pipelines.
- Experience in core design flow, including spec definition, and architecture design.
- Familiarity with instruction set architecture, advanced and high-performance pipeline design concepts.
- You should be familiar with memory coherence, consistency, and ordering.
- Basic understanding of RTL design & SoC tool flows.
- Basic understanding of foundry lib, IP, and process technology limitation.