Junior Flow Development Engineer
As the pioneers who introduced RISC-V to the world, SiFive is transforming the future of compute by bringing the limitless potential of RISC-V to the highest performance and most data-intensive applications in the world. SiFive’s unrivaled compute platforms have enabled leading technology companies around the world to innovate, optimize, and deliver the most advanced solutions of tomorrow across every market segment of chip design, including artificial intelligence, machine learning, automotive, datacenter, mobile, and consumer. With SiFive, the future of RISC-V has no limits. For more information, please visit www.sifive.com.
As a Junior Engineer on the Platform Engineering Execution team, you will be working with an experienced team to build and support the systems and infrastructure that SiFive uses to build our products. You will work closely with a mentor in a small group to build automated flows that support the design, verification and modeling of SiFive's RISC-V Core IP. This is an excellent opportunity to get exposure to cutting-edge technology in RTL generation flows, modeling and and verification.
- Developing modular, reusable and scalable flows with a high level of automation to support design and verification of SiFive’s RISC-V Core IP product
- Working on a team designing, deploying and supporting mission-critical infrastructure for continuous integration and continuous delivery of a hardware product, FPGA modeling, physical design and more in a cloud compute environment.
- BS in Computer Engineering, Computer Science, or Electrical Engineering
- Experience building systems in Python, Scala, C++ or other languages.
- Interest in building modular, scalable and resilient flows and tools.