Lead RTL Design Engineer - RISC-V CPU
As the pioneers who introduced RISC-V to the world, SiFive is transforming the future of compute by bringing the limitless potential of RISC-V to the highest performance and most data-intensive applications in the world. SiFive’s unrivaled compute platforms have enabled leading technology companies around the world to innovate, optimize, and deliver the most advanced solutions of tomorrow across every market segment of chip design, including artificial intelligence, machine learning, automotive, datacenter, mobile, and consumer. With SiFive, the future of RISC-V has no limits.
SiFive is expanding into the UK, providing a unique opportunity for strong candidates with a passion for innovation and product delivery to be part of this exciting new engineering team.
As an experienced Lead RISC-V CPU Design engineer at SiFive you will be part of a team of engineers who are passionate about designing industry-leading CPU cores, based on the revolutionary open-source RISC-V architecture. We are looking for people who are as excited as we are about working in a fast-paced dynamic environment to bring new hardware IP to market quickly, with high quality and exceptional performance.
- Architecting, designing and implementing key parts of new high performance CPU cores in SiFive's RISC-V CPU core generators, and enhancing features and performance in existing ones.
- Ensuring that knowledge is shared via great documentation and participation in a collaborative design culture.
- Performing initial designer-led verification and working closely with the verification team to create and execute detailed verification test plans.
- Working with the physical implementation team to implement and optimise physical design to meet frequency, area and power goals.
- Collaborating with the performance modelling team for performance exploration and optimisation to meet performance goals.
- Mentoring junior engineers and guiding their day to day technical activities, working together to achieve a common goal.
- In depth experience working on complex high-performance RTL designs within a GPU or CPU subsystem.
- Technical leadership experience, and understanding that engineering is a team sport.
- Expert in hardware (RTL) design in Verilog, System Verilog or VHDL.
- Experience with and/or interest in learning at least one object-oriented and/or functional programming language.
- Attention to detail and a focus on high-quality design.
- Ability to work well in a team and collaborate with your colleagues worldwide.
- A Master's or PhD in a related technical discipline or equivalent industrial experience.
- Experience with at least one of the following:
- CPU architecture and design.
- Complex cache subsystems and interconnects (e.g. TileLink, ACE, CHI)
- IP verification tools and methodologies such as UVM/SV and Formal.