As the pioneers who introduced RISC-V to the world, SiFive is transforming the future of compute by bringing the limitless potential of RISC-V to the highest performance and most data-intensive applications in the world. SiFive’s unrivaled compute platforms have enabled leading technology companies around the world to innovate, optimize, and deliver the most advanced solutions of tomorrow across every market segment of chip design, including artificial intelligence, machine learning, automotive, datacenter, mobile, and consumer. With SiFive, the future of RISC-V has no limits.
As the SoC Architect, you will be especially vital to SiFive’s effort to create silicon at the speed of software, as you will create the basic collateral and specifications that can be reused across the SoC design ecosystem. In developing this collateral, the Architect will have the opportunity to lead the use of a novel set of electronic design automation (EDA) tools, which will draw on modern compiling technology and other innovations to create SiFive’s SoC and core library. We are looking for an architect who will create new, highly configurable SoCs designs, based on the open-source RISC-V ISA, for SiFive’s clients, who are taking on exciting new use cases—like autonomous driving, 5G networking, and data centers.
- Designing SoC architecture. Developing upcoming SiFive platforms, which will connect many cores together on a chip, support large bandwidth as well as new applications and workloads
- Creating SoC IP blocks. Designing the IP blocks to be integrated into new SoCs (e.g. interrupt controllers, network on chip, accelerators,, memory cache, I/O devices, and IP subsystems).
- Researching and analyzing emerging needs for new SoC architecture.
- Collaborating directly with customers to tailor SoCs to their needs.
- 8+ years’ experience in ASIC/SoC development and chip architecture definition.
- Familiar with advanced CPU architectures and pipelines.
- Experience in SoC design flow, including spec definition, microarchitecture design, and performance modeling.
- Familiarity with SoC components, such as UART, DDR, PCI Express, etc.
- Basic understanding of RTL design & SoC tool flows.
- Basic understanding of foundry lib, IP, and process technology limitation.