Senior RISC-V ALU Design Engineer

About SiFive

As the pioneers who introduced RISC-V to the world, SiFive is transforming the future of compute by bringing the limitless potential of RISC-V to the highest performance and most data-intensive applications in the world. SiFive’s unrivaled compute platforms have enabled leading technology companies around the world to innovate, optimize, and deliver the most advanced solutions of tomorrow across every market segment of chip design, including artificial intelligence, machine learning, automotive, datacenter, mobile, and consumer. With SiFive, the future of RISC-V has no limits. For more information, please visit www.sifive.com.

As an ALU Design Engineer at SiFive, you will be part of a global team designing the best CPU cores in the world, based on the revolutionary open RISC-V architecture. You will master the art of designing hardware as configurable generators in a hardware-enhanced software language. You will be working in a fast-paced dynamic environment to bring new hardware IP to market quickly, with high quality and exceptional performance.

Responsibilities:

• Architecting, designing and implementing enhanced and new arithmetic functional units for RISC-V CPU Core generators in Chisel.
• Creating more efficient shared arithmetic units; combining capabilities for single/double/half-precision floating point, integer, and/or fixed-point operations.
• Designing in extensive configurability as a first-class consideration, including reuse of ALU designs for vector and scalar operations.
• “Plumb” new design content into the SiFive’s Chisel/FIRRTL framework to enable automatic configuration/generation of documentation, verification testbenches and tests, and packaged software.
• Performing initial sandbox verification, and work with design verification team to create and execute thorough verification test plans.
• Ensuring that knowledge is shared via great documentation and a participation in a culture of collaborative design.

Requirements:

• 5+ years of experience in complex ALU/Datapath design.
• Prior experience designing high-performance arithmetic units
• Proficiency with hardware (RTL) design in Verilog, System Verilog, or VHDL. 
• Experience with Scala and/or Chisel is a plus.
• Knowledge of at least one object-oriented and/or functional programming language.
• Attention to detail and a focus on high-quality design.
• Ability to work well with others and a belief that engineering is a team sport.
• Masters or PhD in EE, CE, CS , Math, or a related technical discipline; or equivalent experience.