Uncore & NoC Architect and Modeler
About SiFive
As the pioneers who introduced RISC-V to the world, SiFive is transforming the future of compute by bringing the limitless potential of RISC-V to the highest performance and most data-intensive applications in the world. SiFive’s unrivaled compute platforms have enabled leading technology companies around the world to innovate, optimize, and deliver the most advanced solutions of tomorrow across every market segment of chip design, including artificial intelligence, machine learning, automotive, datacenter, mobile, and consumer. With SiFive, the future of RISC-V has no limits.
As the Uncore & NoC Architect and Modeler at SiFive, you will be responsible for designing and modeling high-performance uncore and network-on-chip architectures across the breadth of SiFive's core complex portfolio. Hierarchical cluster architectures are essential to producing high-performance multicore architectures that can scale to 128+ cores. This architect will work with a team for the development of such highly scalable multicore architectures.
Responsibilities:
- Modeling Uncore & NoC Architecture. As the Uncore & NoC Modeler, you will be responsible for the performance modeling of various aspects of high-performance uncore & NoC architectures. Examples include the modeling core-to-core coherence protocols and interconnects, cluster architecture, shared cluster and system cache architectures, and interaction with memory system.
- Act as a key person in developing the upcoming RISC-V platforms, which will connect numerous cores together on a chip, support large bandwidth, as well as new applications and workloads
- If interested, you will have a unique opportunity to analyze market verticals and design architectures specifically tailored for upcoming use cases.
Requirements:
- 3+ years of experience in uncore & NoC architecture modeling.
- MS or PhD in computer architecture.
- Strong ability to comprehend various architectural ingredients, such as virtualization, security, power management, and others, when architecting the uncore & NoC components.
- Experience with uncore & NoC design flow, including spec definition, architecture design, and performance modeling
- Familiarity with advanced CPU architectures and pipelines, coherence protocols, interconnect architectures, and system architectures.
