Senior Engineer - Physical Design Low Power
About SiFive
As the pioneers who introduced RISC-V to the world, SiFive is transforming the future of compute by bringing the limitless potential of RISC-V to the highest performance and most data-intensive applications in the world. SiFive’s unrivaled compute platforms have enabled leading technology companies around the world to innovate, optimize, and deliver the most advanced solutions of tomorrow across every market segment of chip design, including artificial intelligence, machine learning, automotive, datacenter, mobile, and consumer. With SiFive, the future of RISC-V has no limits.
Responsibilities:
• Drive the power convergence of high-performance designs from RTL to signoff power analysis,
working closely with the RTL and physical design teams
• Contribute towards the low power methodology development for early and accurate power
prediction, and reliable pre-silicon to post-silicon correlation
• Develop the power analysis infrastructure to enable detailed tracking of power convergence,
improve productivity of physical design team, and identify across the board optimizations.
Requirements:
• 3+ years of experience in power analysis and optimization, with multiple tape outs in a wide
range of technologies (28nm - 3nm); Experience with CPU implementation and advanced
process nodes (16nm and below) is strongly preferred.
• Detailed understanding of power analysis tools, such as PTPX, and power analysis
methodologies
• Prior experience in developing power analytics and detailed dashboards is strongly preferred
• TCL scripting; Python scripting is a plus.
• Attention to detail and a focus on high-quality design.
• Ability to work well with others and a belief that engineering is a team sport.
• Bachelor’s degree in Electrical Engineering or Computer Engineering
