Senior Engineer - Physical Design STA
As the pioneers who introduced RISC-V to the world, SiFive is transforming the future of compute by bringing the limitless potential of RISC-V to the highest performance and most data-intensive applications in the world. SiFive’s unrivaled compute platforms have enabled leading technology companies around the world to innovate, optimize, and deliver the most advanced solutions of tomorrow across every market segment of chip design, including artificial intelligence, machine learning, automotive, datacenter, mobile, and consumer. With SiFive, the future of RISC-V has no limits.
• Drive the timing convergence of high-performance designs from architecture spec to
signoff timing analysis working closely with RTL and physical design teams
• Contribute towards the timing methodology development for reliable pre-silicon to post-silicon correlation
• Develop the timing analysis infrastructure to enable detailed tracking of timing
convergence, improve productivity of physical design team, and identify across the board
• Experience in Static Timing Analysis with multiple tape outs in a wide range of
technologies; Experience with CPU implementation and advanced process nodes (7nm
and below) is strongly preferred.
• Detailed understanding of timing tools, such as primetime or Tempus, and STA
• Prior experience in developing timing analytics and detailed dashboards is strongly
• TCL scripting: Python scripting is a plus.
• Attention to detail and a focus on high-quality design.
• Ability to work well with others and a belief that engineering is a team sport.
• Bachelor’s degree in Electrical Engineering or Computer Engineering