Director of Hardware Design
As the pioneers who introduced RISC-V to the world, SiFive is transforming the future of compute by bringing the limitless potential of RISC-V to the highest performance and most data-intensive applications in the world. SiFive’s unrivaled compute platforms have enabled leading technology companies around the world to innovate, optimize, and deliver the most advanced solutions of tomorrow across every market segment of chip design, including artificial intelligence, machine learning, automotive, datacenter, mobile, and consumer. With SiFive, the future of RISC-V has no limits.
SiFive is expanding our worldwide hardware design organization to include an RTL development team in Bangalore and is looking for a seasoned engineering leader, who is passionate about designing industry leading CPUs, to build and lead that team. As the leader of the India RTL Design Team, you will help drive the tidal wave of adoption of RISC-V as the architecture of choice, and SiFive as the supplier of choice, for SOC designs across a broad variety of vertical applications. We’re creating massively customizable IP and improving time-to-market by designing hardware as highly configurable generators. We're leveraging technology and ideas from the software industry to execute hardware design with the speed and agility of software development.
We are looking for a leader who is as excited as we are about working in a fast-paced dynamic environment to bring new hardware IP to market quickly, with high quality and exceptional performance; both enhancing our existing CPU lines as well as developing new ones.
Join us, and surf the RISC-V wave with SiFive!
- Recruit and build a high-performing team of RTL design engineers
- Lead and manage that team in architecture, design and implementation of enhanced and new RISC-V CPU Core generators in Chisel
- Work with software, compiler and performance analysis teams to optimize performance of CPU cores on key applications and kernels
- Design in extensive configurability as a first-class consideration
- “Plumb” new design content into the SiFive’s innovative design flow to enable automatic configuration/generation of documentation, verification testbenches and tests, and packaged software.
- Perform initial sandbox verification, and work with design verification team to create and execute thorough verification test plans
- Working with the physical implementation team to implement and optimize physical design to meet frequency, area and power goals
- Ensure that knowledge is shared via great documentation and a participation in a culture of collaborative design
- 15+ years of RTL design and development experience, ideally with experience in CPU and/or GPU design
- Experience managing teams of 20+ engineers, and collaborating with globally distributed engineering teams
- Proficiency with hardware (RTL) design in Verilog, System Verilog, or VHDL
- Experience with and/or interest in learning at least one object-oriented and/or functional programming language
- Attention to detail and a focus on high-quality design
- Ability to inspire and motivate an engineering team and a belief that engineering is a team sport
- Knowledge of one or more of: Chisel/Scala, RISC-V architecture, Git/Jira/Confluence is a plus
- BS/MS in EE, CE, CS or a related technical discipline, or equivalent experience
If you yearn to be challenged and wish to work in an environment where the boundaries of your creativity and skills will be tested, then SiFive is the place for you!