Senior Power Engineer
As the pioneers who introduced RISC-V to the world, SiFive is transforming the future of compute by bringing the limitless potential of RISC-V to the highest performance and most data-intensive applications in the world. SiFive’s unrivaled compute platforms have enabled leading technology companies around the world to innovate, optimize, and deliver the most advanced solutions of tomorrow across every market segment of chip design, including artificial intelligence, machine learning, automotive, datacenter, mobile, and consumer. With SiFive, the future of RISC-V has no limits.
SiFive is looking for hardware engineers who will be responsible for defining Low Power architecture and drive the micro architecture, design, development for Core IPs. Candidates will be collaborating across Architecture and RTL teams to establish methodologies, workflows & processes to ensure efficient Energy tracking.
- Defining the power budget/spec for IPs, and coming up with new micro architecture initiatives, rolling up of the power numbers and maintaining the chip power dashboard for various applications.
- Use existing workflows to analyze Energy and make high ROI RTL modifications to improve Energy.
- Work with logic teams to determine the correct functionality or enhance functionality for power reduction.
- Select and run a wide variety of workloads for power analysis.
- Develop IP power model on new architecture design, providing power data for performance/power/area treads-offs.
- Work with multi-functional teams on improving power modeling.
- Experience with power simulation and modeling
- Experience with ASIC power analysis and optimization.
- Experience with script writing in Python, Perl or Tcl.
- Experience with power impact at architecture, logic design, and circuit levels.
- Strong problem solving, organizational and communication skills, and ability to work in a dynamic and diverse environment
- All skill levels with low power architecture, micro-architecture, Design, Power Intent/implementation, power optimization and power estimation