As the pioneers who introduced RISC-V to the world, SiFive is transforming the future of compute by bringing the limitless potential of RISC-V to the highest performance and most data-intensive applications in the world. SiFive’s unrivaled compute platforms have enabled leading technology companies around the world to innovate, optimize, and deliver the most advanced solutions of tomorrow across every market segment of chip design, including artificial intelligence, machine learning, automotive, datacenter, mobile, and consumer. With SiFive, the future of RISC-V has no limits.
As a Release Manager, you will be joining the Release Management team, working with Technical Program Managers (TPM) and Release Technical Program Managers (Rel TPM) and engineering teams to release and support SiFive CoreIP products to customers. You will participate in the definition, implementation and execution of the Operations strategy to build, enhance and support all release operations. RISC-V is highly configurable by its design philosophy. Your role is to help guide our Field Application Engineers/Customers to create a design pipeline, with various combinations of supported instruction sets and with various peripherals and bus interconnect architectures. This is a perfect role for an individual looking to grow their career towards Product Management, Applications Engineering or Pre-Sales roles.
* Manage, coordinate, and release customer deliverables
* Manage release branches and generators to ensure designs are stable while balancing priorities and timelines.
* Manage the release procedures and policy to ensure SiFive delivers high quality products for our customers .
* Participate in defining and implementing release strategy.
* Collaborate with engineering and sales teams to ensure customer requirements are met and delivered.
* Manage a team of Customer Experience Operations and Quality Assurance Engineers
* 5-7 years of practical experience in hardware, semiconductor, or related industry.
* BS/MS in Electrical Engineering or Computer Science.
* Good understanding of CPU IP, such as RISC-V, ARM, MIPS, and ASIC Design Flow and Integration related issues.
* Knowledge of CPU and SoC designs from an architectural level and configuring specific designs with our Core IP generators.
* 2-3 years prior experience as a manager or a team lead
* Proficiency in Linux and its command lines.
* Proficiency of Git, JIRA, RTL simulators like Verilator, VCS, and FPGA flashing tools
* Experience with embedded software and development tools.
* Excellent verbal and written communication skills