RTL Design Engineer, CPU
As the pioneers who introduced RISC-V to the world, SiFive is transforming the future of compute by bringing the limitless potential of RISC-V to the highest performance and most data-intensive applications in the world. SiFive’s unrivaled compute platforms have enabled leading technology companies around the world to innovate, optimize, and deliver the most advanced solutions of tomorrow across every market segment of chip design, including artificial intelligence, machine learning, automotive, datacenter, mobile, and consumer. With SiFive, the future of RISC-V has no limits.
RTL DESIGN, MICROARCHITECTURE
Location : Bangalore / Hyderabad
SiFive is looking for hardware engineers who are passionate about designing industry-leading CPUs based on revolutionary open-source RISC-V Architecture. We are looking for people who are as excited as we are about working in a fast-paced dynamic environment to bring new CPU IP to market quickly, with high quality and exceptional performance.
We have multiple positions open at various levels. Join us and surf the RISC-V wave with SiFive!
- Architect, design and implement new features, performance improvements, and ISA extensions in RISC-V CPU core generators.
- Microarchitecture development and specification. Ensure that knowledge is shared via great documentation and participation in a culture of collaborative design.
- Perform initial sandbox verification, and work with design verification team to create and execute thorough verification test plans.
- Work with physical implementation team to implement and optimize physical design to meet frequency, area, power goals.
- Collaborate with performance modelling team for performance exploration and optimization to meet performance goals.
- 2 to 8 yrs of experience in RTL design and microarchitecture development of high-performance, energy-efficient CPUs.
- Knowledge of CPU processor designs with hands on experience in one or more of the following areas: instruction fetch and decode; branch prediction; register renaming and instruction scheduling; integer; floating-point, and vector units; load-store unit; cache and memory subsystems.
- Knowledge of RISC-V architecture is a plus.
- Proficiency with hardware (RTL) design in Verilog, System Verilog, or VHDL.
- Experience with Scala and/or Chisel is a plus.
- Attention to detail and ability to learn and ramp up on new design concepts.
- Ability to work well with others and a belief that engineering is a team sport.
- Knowledge of at least one object-oriented and/or functional programming language.
- BS/MS degree in EE, CE, CS or a related technical discipline, or equivalent experience.