Physical Design Engineer
As the pioneers who introduced RISC-V to the world, SiFive is transforming the future of compute by bringing the limitless potential of RISC-V to the highest performance and most data-intensive applications in the world. SiFive’s unrivaled compute platforms have enabled leading technology companies around the world to innovate, optimize, and deliver the most advanced solutions of tomorrow across every market segment of chip design, including artificial intelligence, machine learning, automotive, datacenter, mobile, and consumer. With SiFive, the future of RISC-V has no limits.
- Implementing and optimizing our broad portfolio of RISC-V CPU's from RTL to GDSII.
- Closing ambitious performance, power, and area (PPA) goals at block and/or CPU level.
- Collaborating with the microarchitecture and RTL teams to optimize PPA trade offs.
- Contributing to physical implementation flow development to drive best-in-class automation and PPA.
- 5+ years of physical implementation experience with multiple tape outs in a wide range of technologies; Experience with CPU implementation and advanced process nodes (7nm and below) is strongly preferred;
- Expertise in aggressive PPA optimization through physical design techniques
- Understanding of logic design and CPU architecture is a strong plus
- Attention to detail and a focus on high-quality design.
- Ability to work well with others and a belief that engineering is a team sport.
- Bachelor’s degree in Electrical Engineering or Computer Engineering.