E2 series

E20

The SiFive E20 Standard Core is an extremely efficient implementation of the E2 Series configured for very low area and power. The E20 brings the power of the RISC-V software ecosystem to efficiently address traditional 8-bit and 32-bit microcontroller applications such as IoT, Analog Mixed Signal, and Programmable Finite State Machines.

Further optimize the E2 Core for the smallest area using SiFive Core Designer.

E20
Key Features
  • RISC-V ISA - RV32IMC
  • Machine Mode only
  • 2-stage pipeline
  • System Port for external memory accesses
  • Core Local Interrupt Controller (CLIC) with 32 interrupts
  • Advanced debug with 4 hardware breakpoints/watchpoints
  • 1.84/1.22 DMIPS/MHz (Best Effort/Legal)

  • 2.51 CoreMark/MHz

Power, Performance
and Area

28nm HPC
55nm LP
Core-Only Areaa
0.012 mm²
0.033 mm²
Core Complex Areab
0.02 mm²
0.055 mm²
Frequency
725 MHz (Worst)
250 MHz (Worst)
Core Complex Powerc
0.58 mW
1.3 mW

Note: Area and power numbers do not include RAMs. Area numbers are from 50MHz Post-Route at worst setup corner.

a. Core only includes the core pipeline only.

b. Core Complex includes the Core plus CLIC w/32 irq and 2 priority bits, Debug w/ 4 hw breakpoints, internal bus and AHB-Lite ports.

c. Dhyrstone @ 50MHz TT Vnom 25C.

Compare to Cortex-M0+

E2 Series
Cortex-M0+
Dhrystone Performance
1.22/1.84 DMIPS/MHza
0.9 DMIPS/MHz
CoreMark Performance with GCC
2.51 CoreMarks/MHzb
1.8 CoreMarks/MHz
Floating-Point Unit
Optional
None
Memory Map
Customizable
Fixed ARMv6-M
Interrupts
Up to 1024 interrupts
32 interrupts
Interrupt latency to C handler
6-cyclec
15-cycle
Tightly Integrated Memory
2 Banks of TIM (optional)
None

a. E20 Standard Core Configuration, using GCC. The first score is using legal dhrystone compiler flags. The second score uses function inlining and link time optimizations.

b. E20 Standard Core Configuration, using GCC

c. CLIC Vectored Mode

E20
Development Kit

Dev Kit Deliverables

  • RTL Evaluation
  • Test Bench RTL
  • Software Development Kit
  • FPGA Bitstream
  • Documentation
E2
Series Overview

E2 Series

The E2 Series is highly-optimized for area and power while still offering class-leading performance. Targeted for microcontroller and embedded devices, the E2 Core can be configured to be as small as 13.5k gates with an efficient 2‑stage pipeline or configured for higher performance with a 3‑stage pipeline, hardware floating-point, instruction cache, and more.

Using SiFive Core Designer the E2 Series can be fully customized to meet your specific requirements.

E2 Series
Highlights

Key Features

  • Configurable core performance
  • Single precision Floating Point Unit
  • Custom memory map and ports
  • Optional Tightly Integrated Memory (TIM)
  • RV32E support with the smallest core configuration as small as 13.5k gates and is .005mm2 in 28nm

Applications

  • MEMS Sensors
  • Power managment
  • Digital motor control
  • Low-power MCUs
  • Health wearable monitors
  • Environmental monitors

All Standard
Cores

Area
Standard Cores
ARM Comparison
E2 Series
M0, M0+, M3, M4, M23, M33
E3 Series
R4, R5
E7 Series
M7, R7, R8
S2 Series
***
S5 Series
R4, R5
S7 Series
M7, R7, R8
U5 Series
A5, A7, A35, A53
U7 Series
A55
Core Evaluation

From idea
to reality.

Ready to see your code in action? The E20 Development Kit enables free evaluation of SiFive RISC-V Core IP.

Key
Deliverables

Evaluation RTL

  • Full-Functional, synthesizable Verilog RTL
  • Run it in your own simulator
  • Simple, no-cost evaluation license
Start E20 Free Trial

FPGA Bitstream

  • Fully-functional SiFive RISC-V Core Complex with system peripherals
  • High Performance - 32.5 MHz emulation
  • Upload your own programs using the Freedom E SDK

Compatible with the Arty A7-100T FPGA Development Board: