The SiFive E20 Standard Core is an extremely efficient implementation of the E2 Series configured for very low area and power. The E20 brings the power of the RISC-V software ecosystem to efficiently address traditional 8-bit and 32-bit microcontroller applications such as IoT, Analog Mixed Signal, and Programmable Finite State Machines.
Further optimize the E2 Core for the smallest area using SiFive Core Designer.
- RISC-V ISA - RV32IMC
- Machine Mode only
- 2-stage pipeline
- System Port for external memory accesses
- Core Local Interrupt Controller (CLIC) with 32 interrupts
- Advanced debug with 4 hardware breakpoints/watchpoints
- 1.84/1.22 DMIPS/MHz (Best Effort/Legal)
- 2.51 CoreMark/MHz
Note: Area and power numbers do not include RAMs and are Post-Route
a. Frequency is reported at Worst 0.81v, -40°C
b. Core-Only includes the core pipeline and memory interfaces
c. Reported at Typical 0.9v, 25°C for Dhrystone
d. Core-Complex includes the Core plus CLIC w/32 irq and 2 priority bits, Debug w/4 hw breakpoints, internal bus and AHB-Lite ports.
e. Core-Complex total power includes dynamic and leakage and is reported at Typical 0.9v, 25°C for Dhrystone
a. E20 Standard Core Configuration, using GCC. The first score is using legal dhrystone compiler flags. The second score uses function inlining and link time optimizations.
b. E20 Standard Core Configuration, using GCC
c. CLIC Vectored Mode
The E2 Series is highly optimized for area and power while still offering class-leading performance. Targeted for microcontroller and embedded devices, the E2 Core can be configured to be as small as 13.5k gates with an efficient 2‑stage pipeline or configured for higher performance with a 3‑stage pipeline, hardware floating-point, instruction cache, and more.
With SiFive Core Designer, the E2 Series can be fully customized to meet your specific requirements.
- Configurable core performance
- Single precision Floating Point Unit
- Custom memory map and ports
- Optional Tightly Integrated Memory (TIM)
- RV32E support with the smallest core configuration as small as 13.5k gates and is .005mm2 in 28nm
- MEMS Sensors
- Power managment
- Digital motor control
- Low-power MCUs
- Health wearable monitors
- Environmental monitors
Ready to see your code in action? The E20 Development Kit enables free evaluation of SiFive RISC-V Core IP.
- Full-Functional, synthesizable Verilog RTL
- Run it in your own simulator
- Simple, no-cost evaluation license