The SiFive E21 Standard Core is a high-performance, full-featured embedded processor designed to address advanced microcontroller applications such as Sensor Fusion, Smart IoT, Wearables, Connected Toys, and more. Separate Instruction and Data Buses, along with 2 banks of Tightly Integrated Memory (TIMs) make the E21 an ideal choice for applications with deterministic or demanding memory requirements.
- RISC-V ISA - RV32IMAC
- Machine and User Mode with 4 Region Physical Memory Protection
- 3-stage pipeline with Simultaneous Instruction and Data Access
- 2 Banks of Tightly Integrated Memory
- System, Peripheral, and Front Ports
- CLIC interrupt controller with 127 interrupts
- Advanced debug with 4 hardware breakpoints/watchpoints
- 2.27/1.46 DMIPS/MHz (Best Effort/Legal)
- 3.1 CoreMark/MHz
Note: Area and power numbers do not include RAMs and are Post-Route
a. Example Implementations; Area Optimized and Balanced. Frequency is reported at Worst 0.81v, -40°C
b. Core-Only includes the core pipeline and memory interfaces
c. Power is reported at Typical 0.9v, 25°C for Dhrystone
d. Core-Complex includes the Core plus CLIC w/127 irq and 4 priority bits, Debug w/4 hw breakpoints, 4 Region PMP, TIM Logic, internal bus and AHB-Lite ports.
e. Core-Complex total power includes dynamic and leakage and is reported at Typical 0.9v, 25°C for Dhrystone
a. E21 Standard Core Configuration, using GCC. The first score is using legal dhrystone compiler flags. The second score uses function inlining and link time optimizations.
b. E21 Standard Core Configuration, using GCC
c. CLIC Vectored Mode
The E2 Series is highly optimized for area and power while still offering class-leading performance. Targeted for microcontroller and embedded devices, the E2 Core can be configured to be as small as 13.5k gates with an efficient 2‑stage pipeline or configured for higher performance with a 3‑stage pipeline, hardware floating-point, instruction cache, and more.
With SiFive Core Designer, the E2 Series can be fully customized to meet your specific requirements.
- Configurable core performance
- Single precision Floating Point Unit
- Custom memory map and ports
- Optional Tightly Integrated Memory (TIM)
- RV32E support with the smallest core configuration as small as 13.5k gates and is .005mm2 in 28nm
- MEMS Sensors
- Power managment
- Digital motor control
- Low-power MCUs
- Health wearable monitors
- Environmental monitors
From idea to reality.
Ready to see your code in action? The E21 Development Kit enables free evaluation of SiFive RISC-V Core IP.
- Full-Functional, synthesizable Verilog RTL
- Run it in your own simulator
- Simple, no-cost evaluation license