E2 series
E21
The SiFive E21 Standard Core is a high-performance, full-featured embedded processor designed to address advanced microcontroller applications such as Sensor Fusion, Smart IoT, Wearables, Connected Toys, and more. Separate Instruction and Data Buses, along with 2 banks of Tightly Integrated Memory (TIMs) make the E21 an ideal choice for applications with deterministic or demanding memory requirements.
E21
Key Features
- RISC-V ISA - RV32IMABC
- Machine and User Mode with 4 Region Physical Memory Protection
- 3-stage pipeline with Simultaneous Instruction and Data Access
- 2 Banks of Tightly Integrated Memory
- System, Peripheral, and Front Ports
- CLIC interrupt controller with 127 interrupts
- Advanced debug with 4 hardware breakpoints/watchpoints
- 2.27/1.62 DMIPS/MHz (Best Effort/Legal)
- 3.31 CoreMark/MHz
- Detailed Power, Performance, and Area (PPA) Information
a. E21 Standard Core Configuration, using GCC. The first score is using legal dhrystone compiler flags. The second score uses function inlining and link time optimizations.
b. E21 Standard Core Configuration, using GCC
c. CLIC Vectored Mode
E21
Development Kit
Dev Kit Deliverables
- RTL Evaluation
- Test Bench RTL
- Software Development Kit
- FPGA Bitstream
- Documentation
Series Overview
E2 Series
The E2 Series is highly optimized for area and power while still offering class-leading performance. Targeted for microcontroller and embedded devices, the E2 Core can be configured to be as small as 13.5k gates with an efficient 2‑stage pipeline or configured for higher performance with a 3‑stage pipeline, hardware floating-point, instruction cache, and more.
With SiFive Core Designer, the E2 Series can be fully customized to meet your specific requirements.
E2 Series
Highlights
Key Features
- Configurable core performance
- Floating Point Unit, supporting Double, Single and Half precision
- Custom memory map and ports
- Optional Tightly Integrated Memory (TIM)
- RV32E support with the smallest core configuration as small as 13.5k gates and is .005mm2 in 28nm
- SiFive Insight Advanced Trace and Debug
- Bit manipulation extension
Applications
- MEMS Sensors
- Power managment
- Digital motor control
- Low-power MCUs
- Health wearable monitors
- Environmental monitors
Core Evaluation
From idea to reality.
Ready to see your code in action? The E21 Development Kit enables free evaluation of SiFive RISC-V Core IP.
Key
Deliverables
Evaluation RTL
- Full-Functional, synthesizable Verilog RTL
- Run it in your own simulator
- Simple, no-cost evaluation license
FPGA Bitstream
- Fully-functional SiFive RISC-V Core Complex with system peripherals
- High Performance - 32.5 MHz emulation
- Upload your own programs using the Freedom E SDK
Compatible with the Arty A7-100T and Xilinx VCU118 FPGA Development Boards:
